Chapter 5
Synchronous
Sequential Logic
Chih-Tsun Huang (黃稚存)
http://nthucad.cs.nthu.edu.tw/~cthuang/
Department of Computer Science
National Tsing Hua University
Outline
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Introduction
Storage Elements: Latches
Storage Elements: Flip-Flops
Analysis of Clocked Sequential Circuits
State Reduction and Assignment
Design Procedure
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Sequential Circuits
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A sequential circuit consists of a combinational
circuit to which storage elements are connected
to form a feedback path
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Binary information stored in the memory elements at any given
time defines the state of the sequential circuit.
(inputs, current state) => (outputs, next state)
The behavior is specified by a time sequence of inputs and
internal states.
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Synchronous vs. Asynchronous
Sequential Circuits
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Synchronous
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Behavior is defined from the input signals at
discrete instants of time
Clocked sequential circuits
Most commonly used
No instability problems
Asynchronous
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Behavior depends on the value and change order
of input signals at any instant of time
Can be viewed as combinational circuit with
feedback
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Synchronous Sequential
Circuits
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Synchronization usually is achieved by a timing
device: clock generator
Clock generator generates a periodic train of
clock pulses distributed throughout the system to
trigger the memory elements (flip-flops)
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Latches
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Latches are level sensitive devices
Flip-flops are edge-sensitive devices
Latches are asynchronous sequential circuits
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State changes whenever inputs change
Building blocks of flip-flops
Not practical for use in synchronous sequential
circuits
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SR Latches
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SR latch is a basic memory element which
can store one bit of information
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Consists of two cross-coupled NOR gates or two
cross-couple NAND gates
two- input signals: set (S)/reset (R)
Two output signals: Q/Q’
Two useful states: set state (Q=1, Q’=0)/reset
state (Q=0, Q’=1)
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SR Latch with NOR Gates (1/2)
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(S, R) must go back to (0,0) before any other change
to avoid the occurrence of the undefined state
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SR Latch with NOR Gates (2/2)
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SR Latch with NAND Gates (1/2)
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(S,R) must go back to (1,1) before any other change
to avoid the occurrence of the undefined state
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SR Latch with NAND Gates (2/2)
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Gated SR Latch (Clocked SR Latch) (1/3)
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Use C (clock) to enable/disable the SR latch
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C=0, no change
C=1, operates as normal SR latch
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Gated SR Latch (Clocked SR Latch) (2/3)
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The designer must make sure that the input signals do
not change during the time window around falling edge
of C
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The window starts at setup time (tsetup) before the falling edge of
C and ends with hold time (thold) after the falling edge of C
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Gated SR Latch (Clocked SR Latch) (3/3)
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Gated D Latch (1/2)
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D latch has only one input D (the data input)
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Constructed from a gated SR latch by
connecting the D input to S input and D’ to R
Avoiding undesirable condition (S=R=1)
Transparent
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Gated D Latch (2/2)
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Flip-Flops
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Trigger
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Level sensitive (level-triggered)
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The state of a latch or flip-flop is switched by a change
of the control input
The state transition starts as soon as the clock is
during logic 1 (positive level-sensitive) or logic 0
(negative level-sensitive) level
Edge-triggered
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The state transition starts only at positive (positive
edge-triggered) or negative edge (negative edgetriggered) of the clock signal
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Edge-Trigger D Flip-Flop
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Master-slave D flip-flop
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Two separate latches
A master latch (positive-level sensitive)
A slave latch (negative-level sensitive)
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Edge-Trigger D Flip-Flop with
Three SR Latches
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Setup Time and Hold Time
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Setup time
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D input must be maintained at a constant value
prior to the application of the positive clock pulse
Data to the internal latches
Hold time
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Data input must not change after the application
of the positive clock pulse
Clock to the internal latch
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Graphic Symbol
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Edge-triggered D flip-flops
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The most economical and efficient
Positive-edge and negative-edge
Graphic symbol
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Types of Flip-Flops
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Four major commonly used FFs
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Characteristic table
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SR (set-reset), JK, D (data), T (toggle) FFs
(assume only positive-edge-triggered FFs)
Defines the next state Q(t+1) (i.e., the state that
results from a clock transition) as a function of the
inputs and the present state Q(t) (i.e., the state
present prior to the application of a clock edge)
Characteristic equation of each FF
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Can be derived from the characteristic table using
map method
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JK Flip-Flop
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T Flip-Flop
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Characteristic Tables and
Characteristic Equations
Characteristic Equations
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Direct Input
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The state of FFs are unknown when power is
on
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The direct input can force the FFs to a known
state before the system starts.
Preset/Set/PRS: set the FF to 1
Clear/Reset/CLR: set the FF to 0
Synchronous vs. asynchronous direct input
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Whether the input is controlled by the clock
(synchronous) or not (asynchronous)
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D Flip-Flip with Asynchronous Reset
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Analysis of Clocked Sequential
Circuits
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Obtain a table or a diagram for the time
sequence of inputs, outputs, and internal states
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State table or the state diagram
(inputs, current state) => (outputs, next state)
The same information available in state table
can be represented graphically in a state
diagram
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A state diagram is a directed graph, where the node
represents a unique state, and each arc a unique
state transition.
The derivation of a state diagram from a state table is
unique and vice versa.
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Analysis Procedure
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Derive excitation equations (input equations)
Derive state and output equations
Generate state and output tables
Generate state diagram
Develop timing diagram
Simulate logic schematic
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Example 1 (1/3)
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Flip-flop excitation/
input equation
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State equation
1
1
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Output equation
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Example 1 (2/3)
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Generate state
and output tables
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Example 1 (3/3)
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Generate state diagram
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Example 2: D Flip-Flops
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Excitation/input equation
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State equation
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State table
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Generate state diagram
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Example 3: JK Flip-Flops (1/2)
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Excitation/input equation
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State equation
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Example 3: JK Flip-Flops (2/2)
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State table
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Generate state
diagram
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Example 4: T Flip-Flops (1/2)
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Excitation/input equation
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State equation
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Output equation
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Example 4: T Flip-Flops (2/2)
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State table
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Generate state
diagram
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Mealy and Moore Models of
Finite State Machines
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Mealy model
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Outputs are functions of both the present state and input
Moore model
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Outputs are functions of the present state only
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State Reduction and Assignment
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State reduction
Reduction on the number of flip-flops (states) and the
number of gates
For an FSM with m gates, we need log
FFs
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Definition for FSM equivalence
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2.
Given any input sequence, starting from any identical
initial state, they produce the same output sequence
Two states, and
in an FSM are said to be
equivalent ( ≡ ), iff
,
, and
,
,
∀ ∈ ,
where f: output function, h: next-state function, x: set
of inputs
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State Reduction Procedure
1.
Find rows in the state table that have
identical next state and output entries.
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2.
They correspond to equivalent states.
If there are no equivalent states, stop.
When two states are equivalent, one of them
can be removed.
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Update the entries of the remaining table to reflect
the change.
Go to Step 1.
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State Reduction Example (1/2)
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state
input
output
a a b c d e f f g f g a
0 1 0 1 0 1 1 0 1 0 0
0 0 0 0 0 1 1 0 1 0 0
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State Reduction Example (2/2)
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state
input
output
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a a b c d e d d e d e a
0 1 0 1 0 1 1 0 1 0 0
0 0 0 0 0 1 1 0 1 0 0
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State Assignment
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Different state assignments (encodings) result in
different circuits for the intended FSM
There is no easy state-encoding procedure that
guarantees a minimal-cost or minimum-delay
combinational circuits
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Exploration of all possibilities is impossible
Heuristic approaches are often used
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Binary encoding
Minimum-bit change
Prioritized adjacency
One-hot encoding
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State Assignment Example
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Design Procedure
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Design description or timing diagram
Develop state diagram
Generate state and output tables
Minimize states
Encode inputs, states and outputs
Derive state and output equations
Choose memory elements (DFFs, JKFFs, TFFs)
Derive excitation equation and optimize logic
implementation
Derive logic schematic and timing diagrams
Simulate logic schematic
Verify functionality and timing
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Sequence Detector Example
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Detect three or more consecutive 1’s in a string of bits
through an input line
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If detected, output = 1; otherwise output = 0
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Synthesis Using D Flip-Flops (1/2)
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Flip-flop input equations
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Output equation:
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Synthesis Using D Flip-Flops (2/2)
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Logic diagram
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Excitation Tables
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Given the state transition table, we wish to
find the FF input conditions that will cause the
required transition
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Straightforward for D FFs
Excitation tables for JK and T FFs are needed
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Can be derived from the characteristic table/equation
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Synthesis Using JK Flip-Flops (1/3)
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Synthesis Using JK Flip-Flops (2/3)
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Synthesis Using JK Flip-Flops (3/3)
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Logic diagram
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Synthesis Using T Flip-Flops (1/2)
Flip-Flop
Inputs
TA
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TB
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Synthesis Using T Flip-Flops (2/2)
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Logic
diagram
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An n-bit Binary Counter
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3-bit binary counter
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No input (except clock)
The output can be
the states
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Synthesis Using T Flip-Flops (1/2)
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Synthesis Using T Flip-Flops (2/2)
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