Memory Elements
• Combinational logic cannot remember
 Output logic values are function of inputs only
 Feedback is needed to be able to remember a logic value
• Memory elements are needed in most digital logic
circuits to hold (remember) logic values
• 2 basic types of memory elements
 Latches
• Level-sensitive to inputs
 Flip-flops
• Edge-triggered on active edge of clock
C. E. Stroud
Latches & Flip-flops (10/12)
1
Reset-Set (RS) Latch (NOR)
• The simplest memory element
R
Q
 Aka set-reset (SR) latch
• Cross-coupled NOR gates
 Level sensitive
 Active high inputs
• R (reset)
• S (set)
• Only one input can be active
 To avoid undefined state
 Outputs: Q and Q’
• Q = current state of latch
C. E. Stroud
Q
S
R S Q
Q’
Function
0 0
Q
Q’
Storage
0 1
1
0
Set
1 0
0
1
Reset
1 1 0-? 0-? Undefined
Latches & Flip-flops (10/12)
2
Reset-Set (RS) Latch (NAND)
• Dual of NOR RS latch
• Cross-coupled NAND gates
R
 Level sensitive
 Active low inputs
• R (reset)
• S (set)
• Only one input can be active
 To avoid undefined state
 Outputs: Q and Q’
• Q = current state of latch
C. E. Stroud
Q
Q
S
R S Q
Q’
Function
0 0 1-? 1-? Undefined
0 1
0
1
Reset
1 0
1
0
Set
1 1
Q
Q’
Storage
Latches & Flip-flops (10/12)
3
Enabled Reset-Set (RS) Latch (NOR)
R
• Aka gated RS latch
 When enable E is inactive, RS latch
is forced into storage state
Q
E
• R and S can do nothing
Q
• AND gates plus NOR RS latch
 Level sensitive
 Active high inputs
•
•
•
•
S
E (enable)
R (reset)
S (set)
R and S cannot both be active when
E is active
 To avoid undefined state
 Outputs: Q and Q’
• Q = current state of latch
E R S Q
Q’
Function
0 X X Q
Q’
Storage
1 0 0
Q
Q’
Storage
1 0 1
1
0
Set
1 1 0
0
1
Reset
1 1 1 0-? 0-? Undefined
C. E. Stroud
Latches & Flip-flops (10/12)
4
Enabled Reset-Set (RS) Latch (NAND)
R
• Aka gated RS latch
 When enable E is inactive, RS latch
is forced into storage state
Q
E
• R and S can do nothing
Q
• OR gates plus NAND RS latch
 Level sensitive
 Active low inputs
•
•
•
•
S
E (enable)
R (reset)
S (set)
R and S cannot both be active when
E is active
 To avoid undefined state
 Outputs: Q and Q’
• Q = current state of latch
C. E. Stroud
E R S Q
Q’
Function
1 X X Q
Q’
Storage
0 0 0 1-? 1-? Undefined
0 0 1
0
1
Reset
0 1 0
1
0
Set
0 1 1
Q
Q’
Storage
Latches & Flip-flops (10/12)
5
Enabled Data or Delay (D) Latch
D
Q
• Aka transparent D latch
E
 Overcomes undefined state
Q
• R & S never active at same time
• Inverter plus enabled RS latch
 Level sensitive
• Active high enable for NOR latch
• Active low enable for NAND latch
D
E
E D Q Q’
Function
0 X Q Q’
Storage
1 0 0
1
Transparent
1 1 1
0
Transparent
Q E D Q Q’
Function
0 0 0
Transparent
1
Q 0 1 1 0 Transparent
1 X Q Q’
Storage
C. E. Stroud
Latches & Flip-flops (10/12)
logic
symbols
D Q
active
low
E Q’
D Q
active
high
E Q’
6
D Flip-Flop
D
• Aka Master-Slave flip-flop
• Two transparent D latches
Clk
 Sensitive to opposite levels of Clock
• One is always in storage and the other
transparent
D Q
active
low
E
D Q
active
high
E Q’
master
slave
 Data moves through on Clock transition
 Active-low latch followed by active-high D
 aka leading edge-triggered
Clk
 Active-high latch followed by active-low
• Falling edge-triggered
 aka trailing edge-triggered
C. E. Stroud
Q’
master transparent master storage
Clock slave storage slave transparent
• Edge-triggered
• Rising edge-triggered
Q
rising edge
D Q
active
high
E
D Q
active
low
E Q’
master
slave
Q
Q’
master transparent master storage
Clock slave storage slave transparent
Latches & Flip-flops (10/12)
falling edge
7
D Flip-Flop
• Gate-level implementation
 No need for inverter in slave latch since master has Q & Q’
D
active-high
active-low
Q
Rising edge-triggered
Q D flip-flop
Clk
D
active-high
Falling edge-triggered
D flip-flop
active-low
Q
Q
Clk
C. E. Stroud
Latches & Flip-flops (10/12)
8
Timing Considerations
• Set-up time (tsu) = minimum time data
(D) must be valid at input to flip-flop
prior to the active edge of the clock
• Hold time (th) = minimum time data
(D) must remain valid at input to flipD
flop after the active edge of the clock
• Clock-to-output delay (tco) =
Clk
maximum time before output data (Q)
Q
is valid after the active edge of the
clock
C. E. Stroud
Latches & Flip-flops (10/12)
tsu th
tco
9
Timing Considerations
• Set-up & hold time violations in a
real circuit result in metastability
Flip-flop goes to intermediate logic
levels (Q = Q’)
D
Eventually resolves to an unknown
state
Clk
• Set-up & hold time violations in a
vector set for simulation referred Q
to as clock-data-races
tsu th
tco
Leads to invalid simulation results
& manufacturing testing problems
C. E. Stroud
Latches & Flip-flops (10/12)
10
What is the Clock?
• Typically a periodic signal (a sequence of
pulses) used to:
sample data, and
store the sampled data in memory elements
• Clock frequency = 1/period
tco time for tsu
Pdel
fclk = 1/Tp
Tp  tco + Pdel + tsu
• Pdel  Tp - tco - tsu
1
period
Tp
time
0
C. E. Stroud
Latches & Flip-flops (10/12)
11
Serial Shift Register Example
• A series of D flip-flops whose outputs are connected
to the input of the next flip-flop
 serial-in, serial-out = data in on Din, data out on Qc
 serial-in, parallel-out = data in on Din, data out on Qa, Qb,
and Qc
Qa
Qb
Qc
Din
time
Clk
Timing diagram
Clk
Din
Qa
Qb
Qc
C. E. Stroud
Latches & Flip-flops (10/12)
12
Another Shift Register Example
• A series of multiplexers and D flip-flops whose outputs
are connected to the input of the next flip-flop
 parallel-in, parallel-out = data in on Da, Db, and Dc; data out
on Qa, Qb, and Qc (Shift/Load = 0)
 parallel-in, serial-out = data in on Da, Db, and Dc; data out
on Qc (Shift/Load = 0, then Shift/Load = 1)
 Serial-in, serial-out = data in on Din, data out on Qc
(Shift/Load = 1)
 Serial-in, parallel-out = data in on Din, data out on Qa, Qb,
Db
and Qc (Shift/Load = 1)
Da
Dc
Din
0
0
0
1
1
1
Clk
Shift/Load Qa
C. E. Stroud
Latches & Flip-flops (10/12)
Qb
Qc
13
PSIM Architecture
Sequential Logic:
Program Memory (MEM)
Program Counter (PC)
Address Register (AR)
Data Register (DR)
Input Register (IN)
Output Register (OR)
Accumulator (AC)
ALU Carry Register (C)
Instruction Register (IR)
Timing Counter (TC)
Combinational Logic:
Control Logic
Arithmetic/Logic Unit (ALU)
Multiplexers 1&2 (MUX)
C. E. Stroud
Latches & Flip-flops (10/12)
14
Another Register Example
• A series of multiplexers and D flip-flops whose
outputs are connected to the input of the MUX
Register with active high Load
• Load = 1 & rising edge of clock: parallel-in, parallel-out =
data in on Da, Db, and Dc; data out on Qa, Qb, and Qc
• Otherwise: Holds data; data out remains on Qa, Qb, and Qc
Basic register design used in PSIM for:
• AR, DR, OR, IN (all 8-bits) and IR (4-bits)
Da
Db
Dc
0
0
0
1
1
1
Clk
Load
C. E. Stroud
Qa
Qb
Latches & Flip-flops (10/12)
Qc
15
Accumulator Register Example
• Accumulator in PSIM AC-C2
 Functions controlled
by combinational
logic design
ACi
DRi
1
ACi
• Including holding data
when no operations
ACi
are specified
2
Cin
adder
 Via feedback of ACi
 Only need a flip-flop
at output of MUX
• AC register (8-bits)
• C register (1-bit)
 Similar to ACi
design shown here
C. E. Stroud
DRi
AC-C1
0
ACi
DRi
Sumi
ACi
DRi
3
ACi
Zi
4
5
6
ACi
DRi
7
3
AC_C2-0
Clock
Latches & Flip-flops (10/12)
16
Random Access Memory (RAM)
• Assuming MEM from PSIM
 8-bit address => 256 words
DR(7-0)
• MADD
8
 8-bit words
• Input data = 8-bits
MADD(7-0)
8
ADD
DIN
MEM
 From DR
• Output data = 8-bits
WR-MEM
 From MEM
WE
DOUT
8
 Active high write enable
• WR-MEM
MEM(7-0)
(to DR)
 When WR-MEM = 1, data
from DR is written into address
location specified by MADD
C. E. Stroud
Latches & Flip-flops (10/12)
17
RAM continued
• RAM consists of:
DIN
8
Registers with parallel
load
8
W255
WR
• Stores data associated
with specified address
DI
LD Word0
DO
DI
LD Word255
DO
MUX
ADD(7-0)
8
DECODE
• Produces active high
enables to registers
W0
ADD(7-0)
8
Address decoder with
enable
8
Read MUX
• Reads specified address
C. E. Stroud
Latches & Flip-flops (10/12)
18
DOUT
8
RAM continued
DIN
8
• Word Registers with
parallel load
Wi
8 D-latches with active high
enable
DI
LD Word0
DO
8
WORDi
DI0
D
Q
LDi
DI7
D Q
active
high
E Q’
D Q
active
high
E Q’
E
Q
C. E. Stroud
DO0
Latches & Flip-flops (10/12)
DO7
19
Word0
8
• Read MUX
256 9-input AND gates
8 inverters
DECODE
ADD(7-0)
8
WR
C. E. Stroud
example
W255
8
ADD(7-0)
example
ADD0’
ADD1’
ADD2’
ADD3’
ADD4’
ADD5’
ADD6’
ADD7’
Word0Bi
• Address decoder
ADD0’
ADD1’
ADD2
ADD3
ADD4’
ADD5’
ADD6’
ADD7’
WR
DOUT
8
Word255 8
8 256-to-1 MUXs
Functional equivalent
W0
MUX
RAM continued
DOUTi
W12
ADD0
ADD1
ADD2
ADD3
ADD4
ADD5
ADD6
ADD7
Word255Bi
Latches & Flip-flops (10/12)
20
What is Sequential Logic?
• A collection of logic gates and flip-flops
 The logic values stored in the flip-flops establish the
current state of the sequential logic circuit
 The logic values at the inputs in conjunction with the
current state determines the next state of the sequential
logic circuit after the active edge of the clock
Primary
Primary
Comb
Inputs
Outputs
Logic
generalized architecture
Current
State
C. E. Stroud
FlipFlips
Next
State
Latches & Flip-flops (10/12)
for sequential logic circuits
also known as
Huffman model
21
Flip-Flop Information for
Sequential Logic Design
• Types of flip-flops
D (data)
T (toggle)
SR (set-reset)
• Each type has associated:
Characteristic equation
Characteristic table
 sometimes called state table
• Also known as RS
(reset-set)
State diagram
Excitation table
JK (Jack Kilby)
All provide same basic
We will consider
information but in slightly
only edge-triggered
different forms
flip-flops
C. E. Stroud
Latches & Flip-flops (10/12)
22
State Diagrams & State Tables
• Describe complete operation of sequential logic circuit
 Vertices (nodes) represent states
 Edges represent state transitions on active edge of clock
based on primary input logic values
• State diagram & state tables provide exact same
information
 Diagram is graphical representation of same info as in state
table
• Given current state and primary input values we can
determine the next state after active edge of clock
C. E. Stroud
Latches & Flip-flops (10/12)
23
D Flip-Flop Specification
state diagram
1
0
0
1
characteristic equation
Q+ = D
1
D
Q
excitation table
0
Clk
Q
characteristic table
C. E. Stroud
logic diagram
Q
Q+
D
0
0
0
0
1
1
D
Q+
0
0
1
0
0
1
1
1
1
1
Latches & Flip-flops (10/12)
24
T Flip-Flop Specification
state diagram
1
0
0
1
0
characteristic equation
Q+ = TQ’ + T’Q
=TQ
T
Q
excitation table
1
Clk
Q
characteristic table
logic diagram
Q
Q+
T
0
0
0
0
1
1
T
Q+
Mode
0
Q
Storage
1
0
1
1
Q’
Toggle
1
1
0
C. E. Stroud
Latches & Flip-flops (10/12)
25
RS Flip-Flop Specification
state diagram
10
0X 0
characteristic equation
Q+ = S + R’Q
1 X0
01
input ordering = SR
R
S
Q
Clk
Q
characteristic table
excitation table
logic diagram
S
R
Q+
Mode
0
0
Q
Storage
0
0
0X
0
1
0
Reset
0
1
10
1
0
1
Set
1
0
01
1
1
?
Indeterminant
1
1
X0
C. E. Stroud
Latches & Flip-flops (10/12)
Q
Q+ SR
26
JK Flip-Flop Specification
state diagram
1X
0X 0
characteristic equation
Q+ = JQ’ + K’Q
1 X0
X1
input ordering = JK
J
K
Q
Clk
Q
characteristic table
J
K
Q+
Mode
0
0
Q
0
1
1
1
excitation table
logic diagram
Q
Q+
JK
Storage
0
0
0X
0
Reset
0
1
1X
0
1
Set
1
0
X1
1
Q’
Toggle
1
1
X0
C. E. Stroud
Latches & Flip-flops (10/12)
27
Flip-Flop Initialization
• Preset (aka set) => Q+ = 1
• Clear (aka reset) => Q+ = 0
• Some flip-flops have:
Typical logic symbol
with active high preset
and active low clear
Cannot determine sync Pre
or async from symbol
 Both preset and clear (set and reset)
 A preset or a clear
D
 Neither (JK & SR flops have set/reset functions)
• Preset and/or clear can be
Q
Q
Clk
 Active high or active low
 Synchronous => with respect to active edge of clock
 Asynchronous => independent of clock edges
Clr
• Initialization important for:
 logic simulation to remove undefined logic values (2, 3, U, etc.)
 system operation to put system in a known state
C. E. Stroud
Latches & Flip-flops (10/12)
28
Synchronous vs. Asynchronous
• Synchronous =>
states of memory
D
elements change only Example:
with respect to active assume sync preset Clk
edge of clock
and async clear
• Asynchronous =>
states of memory
Clk
elements can change
without an active
D
edge of clock
 Asynchronous designs
often have timing
problems
C. E. Stroud
Pre
Q
Q
Clr
Pre
Clr
Q
Latches & Flip-flops (10/12)
29