June, 2010
Using the Enhanced Local Bus Controller "eLBC"
in PowerQUICC and/or QorIQ Processors
FTF-NET-F0809
Zhongcai Zhou
Application Engineer
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Agenda
►eLBC
Overview
►General
Purpose Chipselect Machine (GPCM)
►NAND
Flash Control
Machine (FCM)
►User
Programmable
Machine (UPM)
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
2
How to Use the Enhanced Local Bus Controller (eLBC)
in PQ and/or QorIQ
►After the power is turned on, a typical system:
1.
2.
3.
Starts execution from non-volatile memory, typically flash memory
Copies/loads the code to main memory (DDRx)
Starts the execution from the main memory
1
U-boot/
BIOS
2
Flash
Storage
ROMzz/Hard Drive
Core
3
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Main Memory
DDRx
TM
3
System Must Talk to Flash Memory Without Any Configuration
►A
system must be able to talk to non-volatile memory without any
configuration steps
►eLBC
•
is the controller that does this initial booting job
eLBC has three controllers:
1.
General purpose chip-select machine (GPCM)
–
–
2.
NAND flash control machine (FCM)
–
3.
Regular NOR flash for booting
SRAM or FPGA
NAND memory for storage and/or booting
User programmable machine (UPM)
–
FPGA, ZBT RAM, etc.
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
4
eLBC Diagram
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Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
5
Basic Operation
►A
transaction request comes to the local bus with address/size/
read-write
► The address is compared against the BRx and ORx to determine which bank(#CS)
this address belongs to
•
There is one BR/OR pair for each bank(#CS)
► The
transaction is routed to the corresponding controlled determined by BR[MSEL]
BRx
ORx
AM
BA: Base Address
PS: Port Size
V : Valid
AM: Address Mask
MSEL: Machine Select
Controller dependent
000 GPCM
001 FCM
100: UPMA
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
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and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
101: UPMB
110: UPMC
others: Reserved
TM
6
Boot from eLBC
► Flexibility
of programming each CS to any one of the controllers (GPCM, FCM,
UPMA, UPMB, UPMC)
► CS0 is special
If the device is configured to boot from the local bus, then the boot ROM, either
flash or NAND, must be connected to /CS0
BR0 and OR0 will be set by the hardware automatically to appropriate value:
BR0[PS]
BR0[MSEL]
BR0[V]
FCM: OR0[PGS]
Boot from GPCM
8-bit ROM
8-bit(01)
GPCM(000)
1
x
Boot from GPCM
16-bit ROM
16-bit(10)
GPCM(000)
1
x
Boot from NAND
8-bit small page
8-bit(01)
FCM(001)
1
Small page(0)
Boot from NAND
8-bit large page
8-bit(01)
FCM(001)
1
Large page(1)
Boot from
non-eLBC interface
x
x
0
x
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
7
Boot from eLBC (cont.)
► OR[AM]
set to all 0
This means all the address bits are masked and not used for the
comparison. Any address hits bank 0. The bank size is 4 GB.
► How
about timing?
GPCM or FCM is set most conservatively in terms of timing out
of reset. This guarantees that GPCM or FCM can talk to any flash or
NAND.
► The
boot code should shrink the bank size and adjust the timing according
to the specific boot memory used to speed up the booting process.
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
8
Key Feature of eLBC
► Address
and data are big-endian indexed
LAD[0:31]: LAD[0] is the MSB; LAD[31] is the LSB
LA[16:31]: LA[16] is the MSB, LA[31] is the LSB
► Buffer
control
LBCTL: The LBCTL pin functions as a write/read control for a bus transceiver
connected to the LAD lines
► Register
writing and local bus request are two different ports. The race
condition is possible.
For example, in the code:
write(eLBC register)
read from eLBC
eLBC could start the read before write32 takes effect. Change to:
write(eLBC register)
read(same eLBC register)
read from eLBC
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
9
Key Feature of eLBC: It Is a Multiplexed Bus
► Address
and data are multiplexed in the same pins to reduce pin counts.
► LALE (Local bus Address Latch Enable): Indicates the address phase
•
There are two main variations:
32-bit bus:
16-bit bus:
LAD[0:31]
LA[25:31]
lad[0:26]
lale
LAD[0:15]
LA[16:31]
lad[0:15]
la[0:26]
latch
la[0:31]
lale
la[25:31]
Advantage: Higher performance
la[0:15]
latch
la[0:31]
la[16:31]
Advantage: Fewer pins, narrower latch
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
10
Key Feature of eLBC (cont.)
► Port
•
•
size and address connection
This applies to GPCM and UPM
1 MB Flash
LA[12]
A18
LA[12]
A18
LA[12]
A17
LA[30]
A0
LA[29]
A1
LA[28]
A1
LA[31]
A-1
LA[30]
A0
LA[29]
A0
LAD[0:7]
8-bit port
LAD[0:15]
16-bit port
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
LAD[0:31]
32-bit port
TM
Key FEATURE of eLBC
►Debug
•
feature
When an error happens, the transaction info is logged into:
ƒ
LTEAR ( Transfer Error Address Register)
ƒ LTEATR (Transfer Error Attributes Register)
►Bus
monitor
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
12
General Purpose Chip-select Machine (GPCM)
► The
simplest among the three controllers
► Designed
► Typical
to interface to flash devices
flash signals and timing (from a flash device datasheet)
Generic Flash Read Timing
Generic Flash Write/Program Timing
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
13
GPCM Timing Control
► GPCM
needs to control the relative timing between the address, /CS, /WE, /OE
signals
► All
the timings are controlled by OR register
CSNT:
ACS:
XACS:
TRLX:
EHTR:
EAD:
/LCS and LWE negation timing
Address to /CS setup time
Extra address to /CS setup time
Timing relaxed
Extended hold time on read access
LALE width control
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
14
How to Program GPCM Read Timing
There is a table in the manual listing the
timings for all the parameter combinations.
►
tARCS
•
•
•
►
tAOE
•
•
►
At least one cycle. Sufficient for flash
No programming needed
tRC/tCSRP
•
•
►
Mainly controlled with OR[ACS]
Recommended to set to ACS=00
tAwCS=0
This gives one cycle address to /CS setup
time (address starts with LALE assertion).
Sufficient for flash
Mainly determined by OR[SCY]
Programmed according to flash speed
tOEN
•
•
•
•
Controlled with OR[CSNT]
There is one automatic cycle between a read
and next transaction
Program to 0 for most flashes
Only flash that shuts off very slowly after read
needs to add extended cycles
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Read Timing
15
TM
How to Program GPCM Write Timing
There is a table in the manual listing the
timings for all the parameter combinations.
►
tAWCS
Mainly controlled with OR[ACS]
• Recommended to set to ACS=00
tAwCS=0
• This gives one cycle address to /CS setup
time (address starts with LALE assertion).
Sufficient for flash
•
►
tAWE
At least one cycle. Sufficient for flash
• No programming needed
•
►
tWC/tCSWP
Mainly determined by OR[SCY]
• Programmed according to flash speed
•
►
tWEN
Controlled with OR[CSNT]
• Program to 0 for most flashes
•
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Write Timing
16
TM
Connection Example: Both NAND and NOR
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Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
17
Key Feature of GPCM
►External
GTA termination
GPCM is terminated by programmed cycle number or LGPL4/GTA if
asserted earlier.
• OR[SETA] =‘1’: GPCM ignores OR[SCY] and terminated by GTA only.
• This feature is useful for some devices that have variable access time.
•
►Why
►No
•
do we need LA[27:31]?
support for burst
What happens if a burst request goes to GPCM?
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
18
NAND Flash
►Overview
of NAND flash
Higher density than regular flash (NOR flash)
• IO device using commands to read/write
•
ƒ
No address bus
ƒ Page-oriented, not suitable for random access
ƒ No execute in place
•
Possible bit error
ƒ
Usually a certain number of blocks are marked bad by the manufacturer
ƒ During the operation, more blocks can go bad
ƒ ECC is a must
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
19
NAND FCM Connection
CE: Chip Enable
WE: Write Enable
CLE: Command Latch Enable
RE: Read Enable
ALE: Address Latch Enable
Observation: There is no address bus
Note: Data bus must be bit reversed.
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
20
How to Read NAND
cmd1
cmd2
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
21
How to Write NAND
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Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
22
Observations
►Different
►The
vendors might have slightly different sequences.
commands might be different.
►In
order to talk to all the vendors, FCM takes a generic approach.
User has the flexibility/responsibility to define the command
sequence.
►512K
vs. 2K
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
23
How FCM Operates
►Internal
8K buffer. Data is exchanged through buffer normally. User
has the option to read/write single byte from MDR register.
4K
core
NAND
4K
•
For large page size NAND, 8K is split into two 4K-buffers.
4K-buffer: 2K for main region, 64 bytes for spare.
•
While one 4K buffer is exchanging data with NAND, the core can access
the other 4K-buffer.
•
For small page sizes, there are 8 1K-buffers.
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
24
How FCM Operates
►Write
1.
2.
3.
4.
5.
data
Initialize FCM registers for write
Set FMR[OP]=00, normal operation
Write to the buffer
Set FMR[OP]=11 after the data (usually one whole page)
is in the buffer
Dummy write to memory bank
or write to LSOR to start the write sequence
FCM reads data from buffer, writes to NAND
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
25
How FCM Operates
►Read
1.
2.
3.
4.
5.
data
Initialize FCM registers for read
Set FMR[OP]=11
Dummy write to memory bank
or write to LSOR to start the read sequence
When the data read is finished, the status bit is set
Set FMR[OP]=00, normal operation
read data from the buffer
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
26
Programming Model
►Command
►Timing
sequence control
control
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Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
27
Command Sequence Control
►Flash
instruction register (FIR)
FCM starts with OP0, until it encounters OPx=0000
User must program the sequence according to the NAND datasheet.
OP definition
0000: NOP. End of sequence
1000: WB. Write FBCR bytes
0001: CA. Column Address
1001: WS. Write one byte
0010: PA. Block+Page address
1010: RB. Read FBCR bytes
0011: User-defined address
1011: RS. Read one byte
0100: CM0. Cmd from FCR[CMD0]
1100: CW0. Wait R/B. Issue FCR[CMD0]
0101: CM1. Cmd from FCR[CMD1]
1101: CW1. Wait R/B. Issue FCR[CMD1]
0110: CM2. Cmd from FCR[CMD2]
1110: RBW. Wait R/B. Read FBCR bytes
0111: CM3. Cmd from FCR[CMD3]
1110: RSW. Wait R/B. Read one bytes
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TM
28
Command Sequence Control Example
►Read
FIR
FCR
sequence programming (slide 19)
OP0
OP1
OP2
OP3
OP4
OP5
CM0
CA
PA
CM1
RBW
NOP
0100
0001
0010
0101
1110
0000
CMD0
CMD1
0x00
0x30
CMD2
OP6
OP7
CMD3
For CA (column address), the controller handles the length
automatically according to ORx[PGS], the page size field.
It is one cycle for small-page NAND and two cycles for large-page NAND.
For PA (page address)
The controller handles the length based on FMR[AL].
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and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
29
Command Sequence Control Example
►Write
FIR
FCR
sequence programming (Slide 20)
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
CM1
CA
PA
WB
CM2
CW0
RS
NOP
0101
0001
0010
1000
0110
1100
1011
0000
CMD0
CMD1
CMD2
0x70
0x80
0x10
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CMD3
TM
30
Timing Control: Command/Address/Data Write
►The
•
timing is controlled by OR[CST], OR[CHT], OR[TRLX].
There is a table in the manual listing all the combinations.
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TM
31
Timing Control: Data Read
►The
•
timing is controlled by OR[RST], OR[TRLX].
There is a table in the manual listing all the combinations.
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TM
32
Boot from NAND
►When
eLBC is configured to boot from NAND
FCM automatically reads 4K data from NAND to the buffer
• Core waits until this 4K transfer finishes, then executes the code out of
this 4K buffer
• This 4K code cannot call the function outside of the 4K range. It needs
to copy the rest of the code to DDR and continue the bootstrap process
•
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and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
33
User Programmable Machine (UPM) Controller
►Very
flexible timing
►Supports
•
burst
Better performance than GPCM
►There
are three independent UPMs.
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TM
34
Basic Principle of Operation
UPM Routine
Start Address
Read single-beat
0x00
Read burst
0x08
Write single-beat
0x18
Write burst
0x20
Refresh Timer
0x30
Exception Condition
0x3C
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TM
35
Programming Model
►UPM
reads the appropriate RAM array based on the transaction
type: read/write, single/burst
►RAM
array instructs the controller what level to drive to each signal
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TM
36
Programming Model: RAM Array
►Basic
Timing
CST1-4: LCS level at phase 1-4
• BST1-4: LBS level at phase 1-4
•
These two signals can be controlled to a resolution of a quarter of LCLK.
G0L/H: LGPL0 level control
• G1-5T1: LGPL1-5 level at phase 1 and 2
• G1-5T3: LGPL1-5 level at phase 3 and 4
•
These signals have resolution of half clock
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and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
37
Basic Timing Control
I
N
D
E
X
C
C
C
C
B
B
B
B
G
G
S
S
S
S
S
S
S
S
0
T
T
T
T
T
T
T
T
L
1
2
3
4
1
2
3
4
0
1
0
1
1
1
1
0
0
10
1
1
1
0
0
0
0
1
1
11
LCLK
T1
T2
T3
T4
0
G G G
1 1 2
G
2
G
3
G
3
G
4
G
4
G
5
G
5
H
T T
T
T
T
T
T
T
T
T
1
3
1
3
1
3
1
3
1
3
11
0
1
0
1
0
1
0
1
0
1
10
0
0
1
0
1
0
1
0
1
0
T1
T2
T3
T4
LCS
LBS
LGPL0
LGPL1
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TM
38
RAM Array (cont.)
Advanced features:
►
There are only 8-entries for single read/write, 16-entries for burst read/write.
•
If this is insufficient, then
REDO: Redo current RAM array once, twice, three times
LOOP:
RAMx LOOP=1, loop start
………………
RAMy LOOP=1, loop end
Loop Number: MxMR[RLF] for read and MxMR[WLF] for write
•
If this is insufficient, then
REDO:
LOOP:
RAMx LOOP=1, loop start
………………
RAMy LOOP=1, loop end
Loop Number: MxMR[RLF] for read and MxMR[WLF] for write
NA: Next address. Increment LA[27:31]/
UTA: UPM TA assertion
LAST: Last entry
►
Less common/useful fields:
EXEN: Exception enable
• AMX: Address muxing
• TODT: Turn-on disable timer
•
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TM
39
UPWAIT
► LGPL4/UPWAIT
UPM supports wait signal to handle variable-speed devices
• LGPL4/UPWAIT can be programmed as either
•
ƒ
ƒ
LGPL4, an output
UPWAIT, an input
► Polarity
of UPWAIT is programmable (MxMR[UWPL)
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
TM
40
TM