TOSHIBA
Timing-Driven Flow (TDF™)
SLI ASIC Design Flow with
Commercial EDA Tools
Description
• Handles megacell (hard) cores
Toshiba’s Timing-Driven Flow (TDF ) is the first stateof-the-art design methodology based on open EDA
tools and standards to successfully address the
challenge of deep sub-micron timing convergence.
Without TDF it is not uncommon for a high-gate-count,
high-complexity design with tight timing specifications
to go through 10–20 iterations between synthesis and
layout and still fail to meet timing. TDF results in
reduced design cycle times and achieves optimal
clock performance with minimal die size. TDF is the
only flow appropriate for SLI (System-Level Integration)
ASIC designs.
™
TDF Flow Components
• Implementation (Synthesis)—Synopsys® Design
Compiler™
• Design Planning—Cadence Logical Design Planner
(LDP)
®
• Timing Driven Placement—Cadence ultra place
• Global Route—Cadence CGRoute
• Clock Tree Synthesis—Cadence CTGen
• Re-optimization—Cadence ultra place and
Synopsys Floorplan Manager
TDF Flow Features
• Timing (top-level design timing constraints) driven
placement
• System-level constraints (SLC) flow
• Concurrent timing-driven placement and
optimization
• Based on open EDA tools from leading EDA vendors
Cadence and Synopsys
• Based on EDA standards—SDF, PDEF, GCF, etc.
• Support for Verilog and VHDL
• Runs on Sun® Solaris 2.51 and HP-UX 10.2
workstation platforms
• Hierarchical placement
• Support for multiple instances of pre-routed hard
blocks
• Standard Cell, Embedded Array, and Gate Array flow
support
• ECO flow support
• Supports TC220 and TC240 product families
• Automated flows utilizing the Toshiba-developed
GUI-based sequencer makes design planning
(Cadence LDP) logic designer friendly
• Detailed Toshiba documentation and application
notes provide guidelines to help achieve timing
convergence
TDF Flow Benefits
• The synthesis tool operates on a more accurate
estimate of wire delays (custom wire load model)
based on actual placement, since statistical-based
wire load models are inaccurate.
• SLC-based timing-driven placement results in better
quality results as opposed to placement based
purely on minimizing wire lengths. Overall timing
slack is reduced by up to 50%.
• The logic designer has better control of the physical
design process during the implementation stage
(synthesis). Intelligent trade-offs can be made prior
to actual place & route.
• Tight links between logic synthesis and place & route
enables automatic timing convergence, resulting in a
dramatic reduction in design cycle time. Minimizing
iterations between layout and logic synthesis can
save a minimum of 4 weeks to many months.
• Routability analysis is completed early in design
planning stage; congestion analysis and identification of potential hot spots.
• Clock skew minimization using clock tree synthesis
program; <200ps for typical SLI Lite designs,
<400ps for SLI designs.
• Clock tree synthesis integrated in design planning
Target Applications
• Global route (same as in place & route) for
congestion and routability analysis
All designs that exceed 100K gates and 60MHz clock
rates will benefit from TDF. However, TDF is the only
solution for SLI ASIC designs.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Lease Option for LDP and FPM Tools
Toshiba Timing-Driven Design Flow
Toshiba has arranged for a nominal license fee to ASIC
customers for a 6-month trial of Cadence LDP and
Synopsys FPM.
RTL
SYN2GCF
write_script
DC Const.
Technology Resource Centers
Toshiba SLI ASIC Technology Resource Centers are
located throughout the U.S. to provide technical
support before, during, and after the design of a
Toshiba ASIC. This includes support for EDA flows,
design kits, Toshiba design methodologies, ASIC
technologies, and design implementation.
Design
Compiler
(AWLM)
Design
Planning
System
PDEF
set_load
In addition, Toshiba’s North America Semiconductor
Engineering Development Center based in San Jose,
CA is staffed with system, technology, and EDA design
experts who work with customers on advanced System
IC applications.
Design
Compiler/
Floorplan
Manager
(CWLM)
High-Quality, High-Volume Manufacturing
Toshiba’s ASIC manufacturing plants are among the
largest and most advanced in the world. They are all
certified to ISO9000. Rigorous quality control coupled
with a sophisticated batch tracking system allows
Toshiba to meet the needs of fast-ramping, highvolume markets.
Gate-Level
Netlist
Design Planning
Concurrent
Placement &
Optimization
GCF
Clock Tree
Synthesis
(CTGen)
Timing
Optimization
(ultra place)
Routing
AWLM = Area-based Wire Load Model
CWLM = Custom Wire Load Model
PDEF = Physical Design Exchange Format
TDF is a trademark of Toshiba Corporation. Cadence is a registered trademark of Cadence Design Systems, Inc. Synopsys is a registered
trademark and Design Compiler and Flooplan Manager are trademarks of Synopsys, Inc. All others are trademarks of their respective
manufacturer and may be registered in certain jurisdictions.
Simulation/
STA
TOSHIBA
TAEC Regional Sales Offices
NORTHWEST
San Jose, CA
TEL: (408) 526-2400
FAX: (408) 526-2410
SOUTHWEST
Irvine, CA
TEL: (949) 453-0224
FAX: (949) 453-0125
Portland, OR
TEL: (503) 629-0818
FAX: (503) 629-0827
Dallas, TX
TEL: (972) 480-0470
FAX: (972) 235-4114
CENTRAL
Chicago, IL
TEL: (847) 945-1500
FAX: (847) 945-1044
NORTHEAST
Boston, MA
TEL: (781) 224-0074
FAX: (781) 224-1096
SOUTHEAST
Atlanta, GA
TEL: (770) 931-3363
FAX: (770) 931-7602
Edison, NJ
TEL: (732) 248-8070
FAX: (732) 248-8030
The technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or reexport directly or indirectly, in contravention of the U.S. Export Administration regulations, is strictly prohibited.