Lecture 1
VLSI CAD Overview:
Design, Flows, Algorithms and Tools
048918
VLSI Backend CAD
Konstantin Moiseev – Intel Corp. & Technion
Shmuel Wimer – Bar Ilan Univ. & Technion
March 2013
Credits:
David Pan – Univ. of Texas Austin
Maciej Ciesielski - UMASS
Andrew Kahng – UCSD
Hai Zhou – Northwestern Univ.
Kia Bazargan – Univ. of Minnesota
Avinoam Kolodny - Technion
1
Administration
• Lecturers:
– Konstantin Moiseev konstantin.moiseev@intel.com
– Shmuel Wimer wimer@ee.technion.ac.il
• Schedule:
– Mayer 351, Thursdays 16:30 – 18:30
• Course grade:
– 20% participation in lectures
– 40% programming exercise
– 40% home examination
• Web page:
– http://moodle.technion.ac.il/course/view.php?id=3186
• guest access is enabled
Course outline
• VLSI design flow overview
• Introduction to algorithms and optimization
• Backend CAD optimization problems:
–
–
–
–
–
Design partitioning
Technology mapping
Floorplanning
Placement
Routing
• Introduction to layout
• Layout optimization and verification
– Layout analysis
– DRC and LVS checks
– Finding objects in the layout
We are here
Design Factors and Styles
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The Big Picture: IC Design Methods
Design
Methods
Cost /
Development
Time
Quality
# Companies
involved
Full Custom
Standard Cell
Library Design
ASIC – Standard
Cell Design
RTL-Level Design
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Optimization: Levels of Abstraction
• Algorithmic
– Reduce fan-out, capacitance
– Buffer insertion
• Layout / Physical-Design
– Move cells/gates around to shorten
wires on critical paths
– Abut rows to share power / ground
lines
– Spacing
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Level of detail
• Gate-level
Effectiveness
– Encoding data, computation
scheduling, balancing delays of
components, etc.
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Full Custom
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Full Custom
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Standard Cell (Semi Custom)
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Cell-Based Design (Standard Cells)
Rows of cells
Feedthrough cell
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Logic cell
Routing
channel
Functional
module
(RAM,
multiplier, …)
Routing channel
requirements are
reduced by presence
of more interconnect
layers
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FPGA: Lookup Table (LUT)
• Look-up Table
– Truth table implemented in hardware
– Can implement arbitrary function with fixed number of inputs (typically
4-5) by programming the storage bits (customizing the truth table)
Programming bit P
1
0
0
1
2-Input LUT
0/1
0/1
F
0/1
0/1
F = x1’x2’ + x1x2
x1 x2
F
0
0
1
1
1
0
0
1
0
1
0
1
x1 x2
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FPGA: Logic Element
• Logic Element: the basic programmable element of FPGA
– Contains LUT
• Programming is a domain of specialized technology
mapping onto device specific structure
Inputs
Clock
Look-Up
Table
(LUT)
Out
State
Enable
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FPGA: Architecture
Tracks
Logic Element
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
Each programmable logic element outputs one data bit
Interconnects are also programmable
A domain of physical synthesis (place and route)
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FPGA: Architecture
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Comparison of Design Styles
style
full-custom
standard cell
gate array
FPGA
cell size
variable
fixed height *
fixed
fixed
cell type
variable
variable
fixed
cell placement
variable
in row
fixed
fixed
interconnections
variable
variable
variable
programmable
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programmable
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Comparison of Design Styles
style
full-custom
standard cell
gate array
FPGA
moderate
large
moderate
low
routing
layers
none
compact
Area
compact
Performance
high
high
to moderate
Fabrication
layers
ALL
ALL
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to moderate
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Comparison of Design Styles
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Design Styles Tradeoffs
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The Inverted Pyramid (~2000)
Electronic Systems > $1 Trillion
Semiconductor > $220 B
CAD $3 B
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Moore’s law
• Moore’s law – exponential growth in complexity
1 billion
transistors
The infamous design productivity gap
Data explosion and productivity
Evolution of the EDA Industry
What’s next?
Results
(design productivity)
Synthesis – Cadence, Synopsys
Schematic entry – Daisy, Mentor, Valid
Transistor entry – Calma, Computervision, Magic
Effort (EDA tool effort)
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History of VLSI Layout Tools
Year
1950 - 1965
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Design Tools
Manual Design
1965 - 1975
Layout editors
Automatic routers( for PCB)
Efficient partitioning algorithm
1975 - 1985
Automatic placement tools
Well Defined phases of design of circuits
Significant theoretical development in all phases
1985 – 1995
Performance driven placement and routing tools
Parallel algorithms for physical design
Significant development in underlying graph theory
Combinatorial optimization problems for layout
1995 – 2002
Interconnect layout optimization, Interconnectcentric design, physical-logical codesign
2002 - present
Physical synthesis with more vertical integration
for design closure (timing, noise, power, P/G/clock,
manufacturability)
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Synthesis and Design Process (High Level)
• Application (graphics, DSP, general processor)
• Algorithm (Z-buffer, FFT)
• Architecture (pipeline, cash sharing, parallelism)
• High level synthesis
• Logic and physical synthesis
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Synthesis Flow at Logic Level
a multi-stage process
Specification
Logic Extraction
module example(clk, a, b, c, d, f, g, h)
Technology-Independent
Optimization
clk, a, b, c, d, e, f;
ainput
reg g, h;
Mapping
boutput g,a h;Technology-Dependent
h
g1
always
@(posedge
clk)
begin
e
0 Synthesis
Physical
G
g = a | b; g0
fbif (d) begin
g
if (c) h = a&~h;
G
h5
else h = b;
dc
if (f) g = c; else a^b;
h3
b end else
g
H
ed
if (c) h = 1; else h ^b;
h
H
a
f end
h1
endmodule
ce
c
clk
d
f
clk
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VLSI Design Flow
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design
Chip Planning
Circuit Design
Placement
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Clock Tree Synthesis
Signal Routing
Fabrication
Timing Closure
Packaging and Testing
Chip
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Physical Design Steps
•
•
•
•
•
•
Circuit partitioning
Floorplanning
Pin assignment
Placement
Routing
Convergence
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Partitioning
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design
Chip Planning
Circuit Design
Placement
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Clock Tree Synthesis
Signal Routing
Fabrication
Timing Closure
Packaging and Testing
Chip
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Partitioning
Circuit:
1
3
Cut cb
2
7
8
4
6
5
Cut ca
Block A
8
7
Block B
Block A
3
4
1
6
5
2
Cut ca: four external connections
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8
7
Block B
5
4
1
6
3
2
Cut cb: two external connections
Partitioning - optimization Goals
• In detail, what are the optimization goals?
–Number of connections between partitions is minimized
–Each partition meets all design constraints (size, number
of external connections..)
–Balance every partition as well as possible
• How can we meet these goals?
–Unfortunately, this problem is NP-hard
–Efficient heuristics are developed in the 1970s and 1980s.
They are high quality and in low-order polynomial time.
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Floorplanning
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design
Chip Planning
Circuit Design
Placement
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Clock Tree Synthesis
Signal Routing
Fabrication
Timing Closure
Packaging and Testing
Chip
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Floorplanning
I/O Pads
Floorplan
Module a
Module b
Block c
Block a
Module c
Chip
Planning
Module d
GND
Block Pins
Block
b
Block d
VDD
Block e
Supply Network
33
© 2011 Springer Verlag
Module e
Floorplanning
Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1
Task: Floorplan with minimum total area enclosed
C
B
A
B
A
A
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C
Floorplanning
Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1
Task: Floorplan with minimum total area enclosed
35
Floorplanning
Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1
Task: Floorplan with minimum total area enclosed
Solution:
Aspect ratios
Block A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3
This floorplan has a global bounding box with minimum possible area (9 square units).
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Pin Assignment
During pin assignment, all nets (signals) are assigned to unique pin locations
such that the overall design performance is optimized.
90 Pins
Pin
Assignment
90 Pins
90 Pins
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90 Pins
© 2011 Springer Verlag
90 Connections
Pin Assignment – Example
Determine the circles
Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards
Given: Two sets of pins
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Pin Assignment – Example
Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards
Best mapping (shortest Euclidean distance)
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Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards
Pin Assignment – Example
Best mapping
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Final pin assignment
Pin Assignment – Example
Given: Two sets of pins
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Final pin assignment
Placement
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design
Chip Planning
Circuit Design
Placement
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Clock Tree Synthesis
Signal Routing
Fabrication
Timing Closure
Packaging and Testing
Chip
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Placement
Linear Placement
c
b
g
d
e
g
f
d
c
2D Placement
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c
b
VDD
h
e
g
f
g
h
d
f
e
f
e
h
a
h
d
a
a
b
GND
c
b
Placement and Routing with Standard Cells
© 2011 Springer Verlag
a
Placement
Global
Placement
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Detailed
Placement
Placement Optimization Objectives
Number of
Cut Nets
Wire Congestion
Signal
Delay
© 2011 Springer Verlag
Total
Wirelength
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Routing
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design
Chip Planning
Circuit Design
Placement
Physical Design
DRC
LVS
ERC
Physical Verification
and Signoff
Clock Tree Synthesis
Signal Routing
Fabrication
Timing Closure
Packaging and Testing
Chip
46
Routing
Given a placement, a netlist and technology
information,
• determine the necessary wiring, e.g., net
topologies and specific routing segments, to
connect these cells
• while respecting constraints, e.g., design rules
and routing resource capacities, and
• optimizing routing objectives, e.g., minimizing
total wirelength and maximizing timing slack.
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Routing
Placement result
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
3
4
C
1
A
1
2
4
5
4
1
Technology Information
(Design Rules)
48
B
3
4
D
6
Routing
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
3
4
C
1
1
A
2
4
N1
1
Technology Information
(Design Rules)
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B
3
4
4
5
D
6
Routing
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5}
N4 = {B1, A1, C3}
3
4
C
1
1
A
2
4
N4
N2
1
Technology Information
(Design Rules)
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B
N3
N1
3
4
4
5
D
6
The Design Closure Problem
Iterative removal of timing violations (white lines)
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