Antimonide-Based III-V CMOS Technology

ANTIMONIDE-BASED III-V CMOS TECHNOLOGY A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTIRCAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Ze Yuan August 2013 © 2013 by Ze Yuan. All Rights Reserved. Re-distributed by Stanford University under license with the author. This work is licensed under a Creative Commons AttributionNoncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/ This dissertation is online at: http://purl.stanford.edu/yh428qq2909 ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Krishna Saraswat, Primary Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. James Harris I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. James Plummer Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost for Graduate Education This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives. iii ABSTRACT As scaling of silicon CMOS becomes increasingly difficult, use of alternate materials with high carrier mobilities is being explored extensively. Despite burgeoning interests in III-‐Vs for realizing high performance transistors at low power, III-‐V MOSFETs have been plagued by (a) Poor PMOS performance, which makes realizing CMOS in a single material system difficult; (b) Low density of states (DOS) for electrons; (c) Poor surface passivation resulting in high interface trap density; (d) Poor dopant activation in the source-‐drain (S/D); (e) High contact resistance; (f) Hetero-‐integration of III-‐V materials on silicon substrates. This work will present novel solutions to overcome these problems. The design is based on the 0.61-‐0.62nm lattice constant system with InGaSb as the channel material because of its advantages in terms of band engineering and high mobility/offsets for both electrons and holes. The goal is to achieve high electron/hole mobility in the same channel material for N-‐ and P-‐channel MOS devices through the optimization of surface passivation, stoichiometry, heterostructure design and novel contact/interface engineering. Hetero-‐integration on a silicon substrate is another key challenge in enabling III-‐V CMOS. The hetero-‐ integration scheme for III-‐V CMOS transistors on silicon using the rapid-‐melt-‐ growth (RMG) technique is demonstrated. ACKNOWLEDGMENTS This journey would not have been possible without the help, encouragement, and contribution of several individuals, to whom I am greatly indebted. First of all, I would like to express my sincere gratitude to my research advisor Prof. Krishna Saraswat for his rigorous support and guidance throughout the course of my graduate studies and research. He has been undoubtedly one of the most kind and helpful people I have ever interacted with at Stanford. He once told me that a professor’s job is to not to tell students what to do, but to be surprised by the students’ ideas and to find money for them. Over the years, he offered great degree of freedom and the perfect blend of encouragement and guidance. It has been his trust that made me work hard. His broad intelligence and unique insight to semiconductor technology have been a constant source of inspiration to me. All these energy and passion that I gained, at the end, even surprised myself, from which I realized the beauty of the way he trains students. I am deeply indebted to my co-‐advisor Prof. James Plummer, who has been an excellent role model and mentor. I have learned a lot from his vast knowledge, wide industry experience and strong technical expertise. More than knowledge, what Prof. Plummer has taught me is how to behave professionally. In spite of his extremely busy schedule, Prof. Plummer has always made time to give me very thoughtful and constructive criticism on my research. I am especially grateful to Prof. H. –S. Philip Wong, who has always been there no matter what kinds of help I needed. I am also thankful to Prof. James Harris, Prof. Boris Murmann for their valuable suggestions on the research and for their precious time and efforts as members of my reading and defense committee. I felt very fortunate to have worked with Dr. Aneesh Nainani, who has been a mentor or even “co-‐advisor” to me in a lot of ways. I really cherish the friendship we have built over the years and I am sure we will have opportunities to work together once again some time in the future. I would like to thank Dr. Brian Bennett, Brad Boos, and Dr. Mario Ancona from Naval Research Laboratory. The experimental work on heterostructure design would not have been possible without their support on MBE growth. They generously shared their expertise in antimonide-‐based compound semiconductors and provided valuable feedback and advice to my research. I would also like to thank Dr. Albert Wang, Dr. Man-‐Hoi Wong, Dr. Wei-‐E Wang from SEMATECH, and Prof. Ravi Droopad from the University of Texas at Dallas for the support on material growth for the project on rapid-‐melt-‐growth. During my graduate studies at Stanford, I have been fortunate to gain valuable experience from internships. I would like to thank Dr. Don D’Avanzo, Dr. Thomas Low, Dr. Barry Wu for my internship experience at Agilent Technologies, Inc., Dr. Robert Visser, Dr. Bhaskar Kumar for giving me the opportunity to work at Applied Materials Inc. and Dr. Jing Wang for hiring me at SuVolta, Inc. My experimental research work relied heavily on the use of the Stanford Nanofabrication Facility. I really appreciate the great effort of all the SNF staff on training lab users and maintaining equipment. I consider myself lucky to have worked with a lot of talented people in and out of Stanford, from whom I have learnt so much. I would like to acknowledge the Saraswat group, the Plummer group, the Wong group, the Harris group, the McIntyre group and the Nishi group for sharing their knowledge and insights with me. Specifically, I would like to thank Dr. Blanka Magyari-‐Kope, Dr. Peter Griffin, Dr. Tejas Krishnamohan, Dr. Ximeng Guan, Dr. Yuan Zhang, Hai Wei, Dr. Zihong Liu, Dr. Yijie Huo, Yi Wu, Dr. Jiale Liang, Dr. Jenny Hu, Chien-‐Yu Chen, Archana Kumar, Dave Sukhdeo, Shuang Li, Yangsen Kang, Liang Dong, Robert Chen, Dr. Hai Lin, Dr. Xiaoqing Xu, Rakesh Jeyasingh, Aryan Hazeghi, Dr. Jaesoo Ahn, Dr. Cynthia Ginestra, Dr. Sun Yun, Shimeng Yu, Liang Zhao and Henry Hony-‐Yu Chen, etc.; all the past and present group members, Dr. Shyam Raghunathan, Dr. Kyung Hoae Koo, Dr. Gunhan Ersosum, Dr. Donghyum Kim, Dr. Duygu Kuzum, Dr. Yeul Na, Dr. Arunanshu Roy, Dr. Crystal Kenney, Dr. Bin Yang, Woo-‐Shik Jung, Suyog Gupta, Donguk Nam, Ju Hyung Nam, Gautam Shine, Dr. Jason Lin, Ashish Pal, Shashank Gupta, Raisul Islam, Dr. Shu-‐ Lu Chen, Dr. Serene Koh, Xue Bai, etc. No words would ever do justice to express my deepest thanks and gratitude to my girlfriend, Christina Yu Zhao, my friends and my family. I will be eternally grateful to them for being with me at all times. Their continuous love, sacrifice, support and encouragement have allowed me to pursue my ambitions. I dedicate this work to them. TABLE OF CONTENTS List of tables .....................................................................................................................iii List of figures ................................................................................................................... iv Chapter 1: Introduction .................................................................................................. 2 1.1 Advantages of III-‐V Compound Semiconductors ................................................ 3 1.2 Critical issues in III-‐V CMOS Technology ............................................................. 6 1.3 Organization of Thesis ......................................................................................... 14 Chapter 2: Surface Passviation in Antimonide-‐Based Metal-‐Oxide-‐ Semiconductor Devices .......................................................................................... 22 2.1 Effects of oxidant dosing on GaSb (001) prior to atomic layer deposition of Al2O3 .................................................................................................................. 22 2.2 Amelioration of interface state response using band engineering in III-‐V quantum well metal-‐oxide-‐semiconductor field-‐effect transistors ................. 35 Chapter 3: InGaSb: Single-‐Channel Solution for III-‐V CMOS .................................. 51 3.1 Tight-‐binding Study of Γ-‐L Bandstructure Engineering for Ballistic InGaSb NMOSFETs ............................................................................................................ 51 3.2 Heterostructure Design for Single-‐Channel III-‐V CMOS ................................... 60 3.3 Surface-‐Channel InGaSb CMOS Transistors....................................................... 68 3.4 Buried-‐Channel InGaSb CMOS Transistors ........................................................ 76 Chapter 4: Source/Drain Technology in Antimonide-‐Based MOSFETs .............. 89 4.1 Antimonide-‐based P-‐channel MOSFETs with Self-‐aligned Ni-‐Alloy Metal Source/Drain ........................................................................................................ 90 4.2 Schottky barrier height reduction for metal/n-‐GaSb contact by inserting TiO2 interfacial layer with low tunneling resistance ........................................ 99 Chapter 5: Hetero-‐Integration of III-‐V Compound materials on Silicon using Rapid-‐Melt-‐Growth ................................................................................................ 114 5.1 Introduction to Rapid-‐Melt-‐Growth ................................................................. 114 5.2 Co-‐Integration of III-‐V CMOS Transistors using Rapid-‐Melt-‐Growth ............ 119 Chapter 6: Conclusion and Outlook ......................................................................... 140 6.1 Conlusions .......................................................................................................... 140 6.2 Future work ........................................................................................................ 142 ii LIST OF TABLES Number Page Table 1: Comparison of on-‐state current and mobility for different candidate of CMOS technology ........................................................................................... 82 Table 2: Comparison of Electrical Properties between Ni-antimonide alloys and ion implanted GaSb ............................................................................................... 95 Table 3: Comparison amongst promising process technologies for hetero-integration of III-Vs on silicon ........................................................................................ 118 Table 4: Melting temperature and lattice mismatch with respect to silicon of InAs and GaSb ....................................................................................................... 121 iii LIST OF FIGURES Number Page Figure 1.1 Electron and hole mobility versus lattice constant for different conventional semiconductors [14]. .................................................................... 4 Figure 1.2 Electron injection velocity in III-V HEMTs [14]. ............................................. 5 Figure 1.3 Possible material combinations for future CMOS technology with alternative channel materials. .......................................................................... 12 Figure 2.1 Angle resolved XPS spectra (tilted at 25°) comparing the concentration of (a) GaOx and (b) SbOx in samples with and without H2O pre-pulsing following TMA pre-pulsing. Increase in GaOx/Ga and SbOx/Sb ratios can be observed in sample with H2O pre-pulsing. ................................................. 25 Figure 2.2 The ratio of integrated peak area between GaOx and Ga, as well as SbOx and Sb in XPS spectra after annealing at different temperature for 1 min indicates GaOx and SbOx are thermally stable at temperature up to 400°C. ... 26 Figure 2.3 high-frequency (100 kHz) capacitance voltage characteristics of W/12nm Al2O3/n-GaSb gate stack before and after forming gas annealing at 350°C for 1min. .......................................................................................................... 27 Figure 2.4 Frequency dependence of peak accumulation capacitances shows the impact of border traps near the dielectric/semiconductor interface. Higher deposition temperature and post-metallization annealing lead to reduction in frequency dispersion.................................................................................... 28 Figure 2.5 Capacitance voltage characteristics of W/8nm Al2O3/GaSb gate stack as function of frequency on n-type substrate with and without H2O prepulsing. ............................................................................................................ 30 Figure 2.6 Capacitance voltage characteristics of W/8nm Al2O3/GaSb gate stack as function of frequency on p-‐type substrate with and without H2O pre-‐pulsing...................................................................................................... 31 iv Figure 2.7 Cross-sectional HR-TEM image of the gate stack consists of ~7.3nm Al2O3 and W as gate metal. No clear sign of interfacial layer confirm the scalability of the approach. .............................................................................. 31 Figure 2.8 Conduction plots (Gp/ωAq) of W/8nm Al2O3/GaSb gate stack with H2O pre-pulsing showing the trace of Fermi-level movements on a) n-type and b) p-type substrates. Measurement temperatures are indicated in the figure. . 33 Figure 2.9 Comparison of extracted interface trap density (Dit) between samples with and without H2O pre-pulsing. H2O pre-pulsing efficiently reduces Dit especially at energy levels towards the conduction band edge. ...................... 34 Figure 2.10 Band diagram and Fermi-level movement during MOSFET operation for a) high-k dielectric/bulk GaSb/InAlSb/InGaSb; GaSb; c) b) high-k high-k dielectric/thick dielectric/ultra-thin GaSb/InAlSb/InGaSb. In both (a) and (b), electrons (ρe) and holes (ρh) at the interface could interact with interface defects. Quantum confinement effect becomes more dominant as the thickness of interfacial GaSb layer scales down as in (c). A dramatic increase of subband energies results in fewer carriers near the interface. Therefore, the interaction between interface traps and carriers is suppressed. ....................................................... 37 Figure 2.11 Dependence of the effective bandgap (Egeff) of the GaSb/InAlSb heterostructure on the thickness of the interfacial GaSb layer (TGaSb) in terms of monolayers. When TGaSb is smaller than a few monolayers, the effective bandgap of GaSb/InAlSb approaches that of InAlSb alone. ............ 39 Figure 2.12 Capacitance measured on the heterostructure with both (a) p- and (b) ndoped channel. Marginal dispersions have been observed at 200K, indicating minimal impact of interface traps on the capacitance. (c) Ultrathin interfacial layer of GaSb can be clearly identified in HR-TEM image. ... 41 Figure 2.13 Measured conductance response for the heterostructure compared to bulk GaSb as the control sample. Biasing condition is set to give near flat-band conditions for both cases. Nearly one order-of-magnitude reduction in v conduction peaks is observed for the heterostructure compared to control sample. ............................................................................................................. 41 Figure 2.14 Transfer characteristics of both (a) p- and (b) n-channel MOSFETs built on the heterostructure in this work, showing sharp switching behavior. Subthreshold swings are 33mV/dec and 61mV/dec for n- and p-channel devices respectively, close to the thermal limit of ln10 kT/q V/dec. .............. 42 Figure 3.1 Structure of InGaSb double-gate MOSFET with (100) orientation. Atom arrangement under VCA.................................................................................. 52 Figure 3.2 (a) Band diagrams of GaSb, In0.5Ga0.5Sb and InSb; (b) summary of the bandstructure effects by varying In% in InGaSb and their relationships. ....... 53 Figure 3.3 Calculated bandstructure from TB for InGaSb at sheet charge density ~3×1012cm-2 with a body thickness of 4nm. .................................................... 54 Figure 3.4 Calculated bandgap and Γ-L energy separation vs. (a) In composition for 4nm body thickness and ~1011 and 1012 cm-2 sheet charge density; (b) body thickness at sheet charge density of 1012 cm-2; (c) sheet charge density for 4nm body thickness. ........................................................................................ 55 Figure 3.5 2D density of states for GaSb and InSb for body thickness of 4nm. ............... 56 Figure 3.6 Fraction f electron occupation in Γ-valley in InXGa1-XSb vs. (a) In composition for 4nm body thickness and ~1011 and 1012 cm-2 sheet charge density; (b) body thickness for 1012 cm-2 sheet charge density; (c) sheet charge density for 4nm body thickness. .......................................................... 57 Figure 3.7 (a) sheet charge density as a function of gate voltage. Gate voltage is adjusted to give 5×107cm-2 sheet charge at 0V; (b) subthreshold swing with varing In composition for body thickness of 4nm and 5nm. ................... 58 Figure 3.8 Injection velocity as a function of sheet charge density for different In composition, the drop in injection velocity at high sheet charge density is due to L-valley population............................................................................... 59 Figure 3.9 Saturation current as a function of gate voltage; Gate voltage is adjusted to give 15uA/um current density at 0V. .............................................................. 59 vi Figure 3.10 Schematic of the heterostructure studied in this work. .................................. 62 Figure 3.11 Cross-‐sectional TEM image of the heterostructure stack grown by Molecular Beam Epitaxy (MBE). The stack is grown on GaAs substrate. The lattice-‐mismatch is released by 1μm thick AlGaSb buffer layer. ........ 63 Figure 3.12 Band energies of the type-I heterostructure formed by InGaSb/AlGaSb, which offers sufficient CBO/VBO to confine both electrons and holes. ........ 64 Figure 3.13 (a) VBO is measured using UV-XPS by taking the difference between VB spectrum from the channel and the buffer layer. Bandgaps of (b) AlGaSb, (c) InGaSb and (d) GaAs are measured using photoluminescence (PL) at 80K. .............................................................................. 64 Figure 3.14 Results from tight-binding calculations show (a) heterostructure design can provide high NS at given gate voltage. Nearly eight orders-ofmagnitude switching of sheet charge densities can be obtained within 1V for both carriers; (b) most of the charge (above 80% and 90% of electrons and holes respectively) is confined in the high-mobility channel even at high sheet charge density up to 1013cm-2. ........................................................ 65 Figure 3.15 a) Electron and (b) hole mobility measured in InGaSb channel as a function of sheet charge density (NS) using gated Hall measurement. Electron and hole mobility of 4000cm2/Vs and 900cm2/Vs can be obtained at sheet density of 1012cm-2 respectively, and are 2.5X and 4X as compared with Si universal even at high NS. ................................................................... 66 Figure 3.16 X-ray diffraction of 004 rocking curve of the heterostructure stack that consists of 1um thick AlGaSb buffer layer, a 10nm InGaSb channel grown on top of GaAs SI substrate. ............................................................................ 67 Figure 3.17 Raman spectrum of CZ-‐grown bulk GaSb and GaSb after Be implantation and consequent annealing. ..................................................... 68 Figure 3.18 Metal S/D structure, in which a slight overlap of gate and S/D electrodes is introduced to lower the access resistance. Top surface layers are n-‐type or p-‐type doped for NMOS or PMOS respectively.......... 69 vii Figure 3.19 Well-‐behaved CGC vs VG characteristics are obtained on both a) p and b) n-‐type InGaSb surface channel devices. .................................................. 70 Figure 3.20 Transfer characteristics for a) PMOS and b) NMOS with metal S/D. NMOS ID-‐VG scales linearly with drain voltage due to the high contact resistance. ....................................................................................................... 71 Figure 3.21 Output characteristics for a) PMOS and b) NMOS with metal S/D. NMOS drain currents are largely limited by the high contact resistance. ....................................................................................................... 72 Figure 3.22 Structure of n-‐channel devices with TiO2 inserted in between the semiconductor and metal at S/D. 5X increase in on-‐state current for NMOS is achieved with the insertion of TiO2. .............................................. 73 Figure 3.23 I-‐V characteristics of (a) Al/GaSb (b) Ti/GaSb contacts on both n-‐ type and p-‐type substrate.............................................................................. 74 Figure 3.24 Temperature dependence of I-‐V characteristics of Al/GaSb Schottky diodes. ............................................................................................................. 74 Figure 3.25 Band diagrams of metal contacts to n-‐type and p-‐type GaSb. ................. 75 Figure 3.26 Temperature dependence of the transfer characteristics of p-‐channel devices shows the significant drop in leakage current at low temperature due to the deactivation of p-‐type defect states. .................... 75 Figure 3.27 Band diagrams and carrier concentration profile (blue: electrons, red: holes) of the surface channel device with 10nm InGaSb as the channel and AlGaSb as the buffer layer. The surface is terminated with 1nm GaSb and the Fermi-‐level is pinned at 0.1eV from the valence band edge of GaSb. Doping levels are changed from 1017cm-‐3, 1018cm-‐3 to 1019cm-‐3, indicated by the directions of the arrows. .............................. 76 Figure 3.28 Band diagrams (blue: conduction band, light green: heavy hole band, dark green: light hole band) and electron concentration (purple: L-‐ valley electrons, red: Γ-‐valley electrons) of the buried channel device viii with 10nm InAlSb top barrier layer, 10nm InGaSb as the channel and AlGaSb as the buffer layer. The surface is terminated with 1nm GaSb and the Fermi-‐level is pinned at 0.1eV from the valence band edge of GaSb. 2x1012cm-‐2 modulation-‐doping layers are included in both top and bottom barrier layers. ............................................................................ 77 Figure 3.29 Schematic of the structure of the buried channel devices. 3nm and 10nm AlInSb top barrier layer were used for PMOS and NMOS respectively..................................................................................................... 78 Figure 3.30 I-‐V characteristics of Au-‐ and Pd-‐based alloy contact with n-‐GaSb with different annealing conditions. Current density increases consistently with higher annealing temperature and duration. ................ 79 Figure 3.31 AES depth profile of Au/Ni/Ge/Au alloy contact on the heterostructure for buried-‐channel devices. ............................................... 80 Figure 3.32 Transfer characteristics of (a) PMOS and (b) NMOS. On/off ratio up to 104 and 3x102 can be obtained for PMOS and NMOS respectively. NMOS current scales non-‐linearly with VDS due to high contact resistance. ....................................................................................................... 81 Figure 3.33 Output characteristics of (a) PMOS and (b) NMOS. Characteristics can be further improved by reduction of contact and series resistance. .. 81 Figure 4.1 XRD analysis of 10nm Ni on GaSb with and without RTA at 300°C for 3mins. .............................................................................................................. 91 Figure 4.2 Cross-sectional TEM image of Pt/Ni-GaSb/GaSb, diffraction pattern indicates poly-crystallinity of Ni-GaSb. .......................................................... 92 Figure 4.3 I-V characteristics of Schottky diodes with different contact metals on nGaSb. ............................................................................................................... 93 Figure 4.4 Schematic of structure for TLM and TLM plots of Pt contact to low-sheetresistance Ni-antimonide alloys. ..................................................................... 94 ix Figure 4.5 Transfer characteristics of devices (LG~5μm) on bulk GaSb substrate and heterostructure stack. Higher on-current and lower off-current were achieved with the heterostructure design. ....................................................... 96 Figure 4.6 Transfer characteristics of the devices with heterostructure design and Nialloy as metal S/D. ........................................................................................... 97 Figure 4.7 Output characteristics of the devices with heterostructure design and Nialloy as metal S/D. ........................................................................................... 98 Figure 4.8 a) The gate to channel capacitance (CGC) measured at 100kHz. b) Extracted effective-field mobility using split-CV analysis and benchmark against silicon and strained GeSn. ............................................................................... 98 Figure 4.9 Band diagrams of depinning effects (a) by MIGS theory, (b) by interface dipole theory and (c) with low CBO dielectric. In the case of (a) and (b), dielectrics with high CBO introduce high tunneling resistance, while in (c) low Schottky barrier is achieved with low tunneling resistance due to low CBO. .............................................................................................................. 100 Figure 4.10 SRPES spectra for (a) TiO2 and GaSb valence bands, (b) Al2O3 and GaSb valence bands, and (c) Al 2p peak from Al2O3. (d) Summary of band offsets information for Al2O3 and TiO2 with GaSb. The TiO2/GaSb and Al2O3/GaSb valence band offsets were measured to be 2.6eV and 3.0eV, respectively. The energy loss spectrum of the Al 2p peak indicates the bandgap of 6.1eV for Al2O3. Photon energy used for valence band and Al 2p were 120eV and 160eV respectively.................. 103 Figure 4.11 J-V characteristics of Al/n-GaSb Schottky diode with interfacial layer of (a) TiO2 and (b) Al2O3. (a) The current density increases with increase in TiO2 thickness even up to 7.5nm. Contact characteristic changes from rectifying to quasi-ohmic. (b) With Al2O3, the current level increases slightly initially and drops significantly for thickness larger than 1nm. The left inset of (a) shows J-V characteristics of TiO2 devices for bias voltage from -1V to 1V, the rectifying behavior for Al/n-GaSb is clearly visible. x The right inset of (a) shows temperature-dependent J-V measurements for 2nm and 9.5nm TiO2 devices, which show effective electron barrier heights of 0.14eV and 0.07eV respectively. .................................................. 104 Figure 4.12 Normalized current density of Al/n-GaSb Schottky diode with interfacial layer of TiO2 and Al2O3 of different thicknesses biased at -0.1V. TiO2 diodes show a substantial increase in current from reduction in ΦBN. Increase in current density with thickness is maintained up to 9.5nm. For Al2O3, after the initial increase, tunneling resistance reduces current density. Current levels are sensitive to the thickness of Al2O3. ..................... 107 Figure 5.1 Top-view illustration of the structure for germanium/III-V RMG process (left). Cross-sectional view of the structure, which is typically used for TEM study of material properties of the stripe (right). ................................. 116 Figure 5.2 Schematics of defect analysis of aspect ratio trapping (ART) and rapid melt growth (RMG). The control of defect propagation along the length of the trench is difficult for ART, while RMG can efficiently terminate defect propagation by the necking mechanism. ....................................................... 119 Figure 5.3 InAs NMOS, GaSb PMOS offer advantages in favorable band line-up relative to ECNL and excellent electron and hole transport properties. ........... 121 Figure 5.4 TEM images of GaSb stripe after RMG show no visible defects, e.g. threading dislocation, stacking faults, etc...................................................... 124 Figure 5.5 TEM images of GaSb near the Si seed after RMG. Defects, e.g. twinnings, etc., only propagate over short range due to the efficient termination of defects near the neck region. ......................................................................... 125 Figure 5.6 High-resolution TEM images of GaSb and InAs ~1μm away from the seed windows. Diffraction-patterns indicate single-crystallinality. Crystal orientation of Si seed is preserved. ................................................................ 126 Figure 5.7 Diffraction patterns taken at different locations along the stripe of a) GaSb, b) InAs 1μm, 2μm, 3μm away from seed confirm the propagation of the xi growth as zone axis remains unchanged. The distance from the seed is indicated in the figure. ................................................................................... 126 Figure 5.8 Tilted-view SEM image showing rough surface and poor coverage around the neck region for InAs thin film grown on SiNx by MOCVD. ................... 127 Figure 5.9 Tilted-view and cross-sectional SEM images of GaSb thin film on dielectric on silicon, showing lack of step coverage around the neck region due to the poor nucleation during MBE growth of GaSb thin film. .............. 128 Figure 5.10 Top-view and cross-sectional SEM images of GaSb thin film on dielectric on silicon showing smooth surface on dielectric and step coverage. ........................................................................................................ 129 Figure 5.11 AFM measurement on as-deposited film and stripe after rapid-meltgrowth, showing the surface roughness is improved after RMG. ................. 130 Figure 5.12 Raman spectra of bulk and RMG GaSb show similar FWHM and peak position. ......................................................................................................... 131 Figure 5.13 SEM image of the TLM structure for GaSb stripe....................................... 131 Figure 5.14 TLM measurements on GaSb stripes give high sheet resistance, indicating low concentration of defects, which are electrically active; Ni-‐alloy shows low sheet resistance and ρc. .............................................. 132 Figure 5.15 InAs NMOS, GaSb PMOS with common device process flow with the same gate stack and self-aligned Ni-alloy S/D. ............................................. 133 Figure 5.16 Process flow for InAs-OI NMOS, GaSb-OI PMOS transistors with Nialloy SDs integrated on silicon using RMG. ................................................. 133 Figure 5.17 SEM image of GaSb PMOS on insulator on silicon integrated with RMG process. .......................................................................................................... 134 Figure 5.18 Transfer characteristics of GaSb-OI PMOS showing a on/off ratio higher 103. ................................................................................................................. 134 Figure 5.19 SEM image of sidewall profile of GaSb stripe after RMG shows that underlying dielectric can potentially be etched away to enable GAA structure. ........................................................................................................ 135 xii Figure 5.20 Output characteristics of InAs-OI NMOS, GaSb-OI PMOS transistors integrated on silicon using RMG. .................................................................. 135 xiii CHAPTER 1: INTRODUCTION For over 50 years, the increases in density and performance of complementary metal-‐oxide-‐semiconductor (CMOS) logic transistors have propelled the exponential rise of silicon electronics. However, traditional transistor scaling is now close to its physical limits. To prolong the life of the microelectronics revolution, attention has thus turned to non-‐silicon semiconductors, which have excellent carrier transport properties, including carbon-‐based semiconductors such as carbon nanotubes [1,2] and graphene [3,4], germanium [5,6] and III-‐V compound semiconductors [7,8]. Amongst the candidates for replacing silicon as the channel material, III-‐Vs offer advantages in terms of compatibility with traditional silicon CMOS processing and superior carrier transport properties, particularly electron transport. As a result, III-‐ Vs have received increased attention in the development of nanometer-‐scale logic transistors. Recently, the power dissipation of logic chips has reached a level of 100Wcm-‐2 [9], indicating that metal-‐oxide-‐semiconductor field effect transistor (MOSFET) scaling has entered the phase of “power-‐constrained” scaling. Power density cannot increase much further without incurring substantial packaging and cooling costs that make these chips impractical for most applications. Meeting the power constraint requires that transistors move towards a reduction in operating voltage [10], but doing so would compromise switching speed. For this reason, the operating voltage of silicon-‐based CMOS transistors has stayed flat at around 1V for a few generations in spite of their power consumption [11]. Fundamentally, the speed of CMOS circuit is determined by the intrinsic delay of a single transistor, which is CV/I, where C is the transistor capacitance, V is the operating voltage and I is the drive-‐current. In nanoscale transistors, the drive-‐ 3 current is determined by the product of sheet charge carrier density (nS) and injection velocity of the carriers (vinj) [12], at the “virtual source” position along the channel that presents the highest energy barrier in the conduction band. Therefore, to first order, the intrinsic delay is proportional to 1/vinj. This simple analysis indicates that enhancement of vinj is the key to improving the frequency performance of the circuits. To achieve this goal, one possible solution is to introduce a new channel material in which carriers travel at higher velocity compared to silicon. III-‐V compound semiconductors have the highest electron mobility amongst all the conventional semiconductors, making them an extremely attractive candidate for the channel materials. Due to their unique optical and electronic properties, the III–V compound semiconductors, such as GaAs, AlAs, InAs, InP and their ternary and quaternary alloys, are already widely used in high-‐speed, high-‐frequency electronics, lasers, light-‐emitting diodes and detectors for optical communications, instrumentation and sensing. For instance, high electron mobility transistors (HEMTs) based on GaAs, InAs and InGaAs, which exhibit outstanding electron transport properties, have been in large-‐scale manufacturing for more than a decade. Recently, III–V CMOS technology has gained momentum in the community of semiconductor research. The importance of their role has been recognized in the International Technology Roadmap for Semiconductors [13]. 1.1 ADVANTAGES OF III-‐V COMPOUND SEMICONDUCTORS What attracts attention to III–V CMOS technology has been the extraordinary electron mobility of certain III–V compounds as shown in Fig. 1.1 [14]. The room-‐ temperature mobility of electrons and holes in inversion layers and quantum wells is shown as a function of the actual semiconductor lattice constant. For relaxed layers, under no strain, the lattice constant is its natural one. For pseudomorphic 4 layers, which are strained on a substrate with a different lattice constant, the lattice constant is that of the substrate. Thus, points marked with the same label may appear in different locations in the figures. A >10x enhancement of electron mobility can be achieved in InAs, InGaAs system relative to silicon at comparable sheet charge densities. Current-‐gain (fT) and power-‐gain (fmax) cutoff frequencies of InGaAs-‐based high-‐electron-‐mobility transistors (HEMTs) exceeding 600GHz and 1THz respectively have been achieved [15]. Figure 1.1 Electron and hole mobility versus lattice constant for different conventional semiconductors [14]. The injection velocity, vinj, to first order, is proportional to 𝜇, in which 𝜇 corresponds to the low field carrier mobility [16]. The ballistic limit refers to the case where carriers travel from source to drain without being scattered and losing 5 their momentum. This can only be achieved at extremely short channel lengths. As the device scales down, it gradually approaches the ballistic limit, which leads to the increase of injection velocity until it saturates at extremely short channel lengths. Hence, a study of vinj of III-‐V materials in short-‐channel devices could be an excellent indicator for the performance of nanoscale MOS transistors made of III-‐Vs. Fortunately, III-‐V HEMTs technology is fairly mature and, in fact, already supports large-‐scale industrial manufacturing. Therefore, III-‐V HEMTs have been the main avenue for understanding the injection velocities and provide an important reference for future III-‐V CMOS transistors. Figure 1.2 Electron injection velocity in III-‐V HEMTs [14]. In the InGaAs system, the electron mobility can be enhanced by increasing the In composition in the compound. This leads to an increase in injection velocity as the In composition increases from In0.53Ga0.47As to InAs. It has been experimentally demonstrated by measurements in InGaAs and InAs HEMTs [17] that vinj 6 approaches 4 × 107cms–1 (InAs) at 0.5V as shown in Fig. 1.2. This corresponds to an enhancement factor of more than two compared to strained silicon. The drain voltage for III-‐Vs is also assumed to be at 0.5V, which is half of that of silicon. This proves that, even at a lower operating voltage, III-‐V MOS transistors have a strong potential for use in high-‐speed circuits. 1.2 CRITICAL ISSUES IN III-‐V CMOS TECHNOLOGY Despite burgeoning interest in III-‐Vs for realizing high-‐performance transistors at low power, several barriers have plagued III-‐V MOSFETs. Most probably, the technology will be introduced at the 10nm technology node [14], which means that devices will need highly scaled electrostatics, low parasitics, and good manufacturability, especially for hetero-‐integration. These present a diverse array of serious challenges for III-‐V devices to outperform their silicon counterparts at such gate lengths. The following are some examples of the critical issues that III-‐Vs must overcome to deliver enhanced performance while still being cost-‐effective in manufacturing. The gate stack From a gate stack point of view, the emergence of high-‐permittivity (high-‐k) dielectrics enabled alternative channel materials, since the gate stack is what differentiates a MOSFET from a conventional HEMT. A gate stack should have the following desirable characteristics: be free of trapped charge and defects; produce a smooth interface with few interfacial imperfections; and be highly stability. For silicon technology SiO2/Si meets all such requirements. The same does not apply to III-‐Vs. On the contrary, generally speaking, III-‐V native oxides are believed to pin the 7 Fermi level at the dielectric/semiconductor interface [18], which suppresses the modulation of the surface potential in a MOSFET. There are multiple potential origins of interface traps that pin the Fermi-‐level at the interface. For instance, in GaAs, Ga/As oxides and suboxides, elemental As, As-‐As dimers, Ga-‐Ga dimers, and dangling bonds could all contribute to interface trap states [19-‐21]. Much recent progress has been made on the growth of high quality gate stacks using ALD. One of the reasons that the use of ALD enables high-‐quality interfaces is the so-‐called “self-‐cleaning” effect [19], which happens during the initial stage of the ALD growth. This mechanism has been studied with simulations based on density functional theory (DFT) [20]. When correlated with experimental measurements, e.g. scanning tunneling microscopy (STM), DFT simulations provide a lot of insight into the impact of the detailed bonding of the surface atoms on the interfacial defect states [20,22]. It has been suggested that dimer formation is the main cause of the interfacial gap states [23]. There are several ways to deal with the problem, including a pre-‐deposition surface clean [24], the use of an interfacial layer [25], post-‐deposition treatment [26] and the use of a buried-‐channel structure [27]. Recently, it has been proposed that careful control over the initial stages of the ALD growth allows the modulation of the surface bonding, thus minimizing the interface trap density [20]. Another important topic is the accurate characterization of interface traps as well as border traps, which refer to the traps within the high-‐k oxide that are close to the semiconductor/oxide interface. It has been shown that blindly applying the conventional capacitance-‐voltage characterization techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under-‐ and over-‐ estimate the interface trap density by more than an order of magnitude [28]. The temperature dependent conductance method is recommended for the extraction of interface trap density (Dit). The role of border traps has also become more 8 recognized. It has been demonstrated that the charging of slow traps in the high-‐k dielectric could potentially harm the stability of the devices [29]. The correct characterization of the border traps has also been actively studied [30]. Self-‐aligned low-‐resistance source/drain As device scaling continues and reaches the 10nm technology node, parasitic resistance becomes a limiting factor for the on-‐state current [31]. Gate pitch scaling has been more aggressive compared to the physical length of the gate, leaving less area for source/drain contacts. At the 15nm node, the contact length can be estimated to be about 10nm. The performance gained from a high-‐mobility channel will be compromised if the parasitic resistance is not properly controlled. The importance of the two main components of parasitic resistance has been recognized: the voltage drop between the channel and the source/drain contact and the contact resistance. Future generations of transistors will require a source resistance below 50 Ωμm while the source resistance of state-‐of-‐art InGaAs HEMTs is about 150-‐250 Ωμm with a relatively large contact area. There are several approaches to close the gap between the existing and the desired source/drain resistance in III-‐V transistors: a self-‐aligned source/drain process that allows for the aggressive scaling of the separation between gate and source/drain contacts and a very low ohmic contact resistance. A self-‐aligned process can be realized in several different ways depending on the device structure. Similar to silicon technology, ion-‐implantation could be used to implant the source/drain region self-‐aligned to the gate pattern [7]. The problem with ion-‐implantation is the poor recovery of the crystalline structure in III-‐V materials. Due to the absence of solid phase epitaxy under normal conditions and poor dopant activation, achievement of high carrier concentrations from ion 9 implantation is thus challenging. A monolayer doping technique has been developed to achieve ultra-‐shallow junction with high carrier concentration without excessive damage to the lattice [32]. Another approach is by selective epitaxial regrowth of the highly doped source/drain regions. The selectivity of the epitaxial re-‐growth is enabled by the combination of a replacement-‐gate process and metal-‐organic chemical vapor deposition (MOCVD) [33]. A raised source/drain structure after the re-‐growth benefit the source/drain resistance as well. Another advantage of the approach is the ability to have a gate-‐last process in order to preserve a high-‐quality oxide/semiconductor interface. More recently, another option has emerged as a promising candidate for achieving low source/drain resistance: alloying III-‐Vs with Ni in the source/drain regions in a self-‐aligned fashion analogous to the present self-‐aligned silicide source/drain contacts used in silicon CMOS production. With a thermal budget as low as 350°C, a sheet resistance below 100Ω/sq and a specific contact resistivity of ~2x10-‐9Ωcm-‐2 can be achieved between the contact pad and the metallic S/D [34]. An important advantage of this approach is that the use of a metallic S/D could be a potential solution to the “source starvation” problem for III-‐V MOSFETs [35] due to the low density-‐of-‐states inside the source region of the MOSFETs. For low ohmic contact resistance, fundamentally speaking, III-‐Vs would not be at disadvantage compared with silicon when the Fermi-‐levels are pinned at a favorable position relative to the band edge. For instance, in the case of InAs, the Fermi-‐level at the interface between the contact metal and the InAs is pinned inside the conduction band of InAs, resulting in negative barrier for the injection of electrons from the semiconductor to the metal. However, if the Fermi-‐level is pinned at an unfavorable position, e.g. contact to n-‐GaSb, the higher pinning factor associated 10 with the lower bandgap of the semiconductors, could result in high Schottky barriers regardless of different contact metals. In 2011, Intel announced the use of trigate transistors for the 22-‐nm technology node. Similar devices based on III-‐V compounds have already been demonstrated with improved short-‐channel effects over devices with planar designs [7-‐8]. To compete with silicon counterparts, III-‐V devices need to achieve a similar level of electrostatic control with a 3D structure. Source/drain design for 3D structures would become more challenging with this additional constraint. Low density of states of electrons The product of sheet charge density and injection velocity determines the on-‐ state current. Ideally, materials with both a large density of states (DOS) and a high electron injection velocity are desired. The higher carrier mobilities and injection velocities of III-‐Vs come from the fact that the effective masses of electrons are much smaller compared to Si. However, they suffer from the low carrier DOS for the same reason, which leads to a low sheet charge density. In order to achieve excellent electrostatic control for III-‐V MOSFETs, the equivalent oxide thickness (EOT) and body thickness of the channel have to be aggressively scaled. Because of the quantum confinement effect in devices with a scaled channel thickness, the impact of the DOS increases. Eventually, this leads to diminishing benefits of III-‐Vs over silicon with an EOT below 0.6nm [35]. Unlike silicon, in which Δ-‐valleys of electrons comprise nearly all of the conduction in NMOS, there are two valleys participating in III-‐V electron conduction in III-‐Vs: Γ-‐ and L-‐valleys. Indium-‐rich compounds usually have a low energy band edge for the Γ-‐valley, together with an extremely small effective mass of electrons. 11 In Gallium-‐rich compounds, on the other hand, the L-‐valleys also contribute to the conduction due to the low energy separation between the Γ-‐ and L-‐valleys. In some cases, there is mixed conduction between the two valleys, e.g. GaSb, where the trade-‐off between the DOS and injection velocity becomes complicated. A study of the bandstructure in these materials cannot rely on the traditional effective mass approximation for several reasons. Most notably, the Γ-‐valley is highly non-‐parabolic, therefore making the effective mass approximation inaccurate. Quantum confinement effects lead to a distortion of the E-‐k dispersion relation, meaning that the bandstructure varies for different body thicknesses, bias conditions, etc. A true atomistic simulation has to be adopted to study such effects [36]. Balance between NMOS and PMOS Ideal CMOS circuits require well-‐matched performance from both NMOS and PMOS devices. Because of the lower carrier mobility of holes, PMOS transistors have traditionally lagged behind NMOS devices. Circuit designers have learned to work with silicon PMOS transistors that have about one-‐third of the current density of NMOS. As shown in Fig. 1.1, there is a large imbalance between electron and hole mobilities in each material system. Considering the difficulty and manufacturing cost of hetero-‐integration, it is favorable to have NMOS and PMOS based on the same material system with channel materials of similar lattice constants. However, amongst the common options, there is not a pair of materials with similar lattice constants that meets this requirement. Technologies featuring NMOS and PMOS transistors made of different lattice constants have therefore been proposed [8,37]. 12 S! NMOS PMOS Gate Gate S-Si SiO2 D! S! Ge CMOS Ge D! Ge SiO2 Si - Substrate Si - Substrate NMOS PMOS III-V Ge Ge III-V CMOS III-V Si - Substrate III-V Si - Substrate Figure 1.3 Possible material combinations for future CMOS technology with alternative channel materials. Ge has the highest bulk hole mobility amongst all conventional semiconductors, and is a relatively mature in terms of integration with silicon technology. Therefore, silicon p-‐channel transistors can be replaced by germanium to complement strained n-‐channel Si transistors for enhanced hole transport [38]. Though the technology is relatively well-‐developed, in some cases, already in production, the benefits are marginal for scaling beyond 10nm compared with other choices. Due to its high hole mobility and technology maturity, Ge CMOS is a very attractive option [39]. The problem with this approach is that Ge NMOS has not shown equivalent performance when compared to InGaAs-‐based III-‐V NMOS. Enhancement of the performance of Ge NMOS is still an active research topic within the community. The use of strain [40], alloying Ge with Sn [41], and a few other techniques have all been demonstrated recently. 13 The combination that offers the best performance is InGaAs-‐based III-‐V NMOS complemented by Ge PMOS, simply because InAs has shown extremely high electron mobility in HEMT devices and this complements the excellent performance of Ge PMOS. The problem lies in the manufacturing challenges implied by this approach. The co-‐integration of two completely different material systems is challenging [42]. Cross-‐contamination becomes an issue, as both group IV and III-‐V materials need to be integrated on a silicon platform. Selective epitaxial growth techniques will need to be adopted. Common gate stack solution and source/drain technology may require compromise on each type of device [43]. The last option is all III-‐V CMOS. As shown in Fig. 1.1, even though the InGaAs system has excellent electron mobilities, the hole mobility lags far behind and is even worse than that of silicon. The only material systems within III-‐Vs that can offer good hole transport are antimonide compounds, namely GaSb, InGaSb and InSb [44]. Through pseudomorphic buffer engineering, the hole mobility can be further increased by introducing compressive biaxial strain [45]. This demonstrates the important potential role antimonide compounds would play in an all-‐III-‐V CMOS scheme. Recently, it has also been found that the superposition of uniaxial strain and biaxial strain yields nonlinear mobility gains [46]. Hetero-‐integration of III-‐Vs on silicon The hetero-‐integration of III-‐Vs has been an active research topic for some time, in hopes of integrating optical devices and other III-‐V electronic devices with CMOS technology. Such integration has usually been achieved by direct hetero-‐epitaxial growth. Due to the large lattice mismatch between III-‐Vs and silicon, a pseudomorphic buffer layer is grown first to absorb all the lattice difference. The active layers are then grown on top of the buffer. Besides the desire for a low defect 14 density films, one additional requirement for the integration of III-‐V CMOS transistors is the thickness of the buffer layer. This is important for a variety of reasons, including the integration with silicon-‐based devices, the need for high throughput, and heat dissipation. State-‐of-‐art III-‐V MOSFETs on silicon have been fabricated on off-‐cut Si wafers with more than a 1μm-‐thick composite buffer layer grown by molecular beam epitaxy (MBE) [27], which is likely not a suitable approach for manufacturing. To avoid direct hetero-‐epitaxial growth of III-‐Vs, different types of layer transfer techniques have been developed, in which III-‐V device layers are grown first on native substrates and then transferred onto a silicon substrate [47,48]. The challenge for these layer transfer techniques is scaling up to large wafers. Using structural geometry to control the defect formation and propagation has been used to reduce the buffer layer thickness. One of such techniques is called “aspect-‐ratio trapping” (ART), which consists of selective growth of materials inside trenches with high aspect ratio and sub-‐micrometer dimensions. The trenches trap threading dislocations, yielding high-‐quality device layers [49] with low buffer thickness. 1.3 ORGANIZATION OF THESIS This thesis studies some novel solutions to the problems associated with III-‐V CMOS technology. From a manufacturing point of view, it is still favorable to realize CMOS in a single material system. Therefore, the target of this work is the realization of an all III-‐V CMOS approach. As previously mentioned, the role of the antimonides is unique in this scheme due to their superior hole transport. We base the design on the 0.61-‐0.62nm lattice constant system with InGaSb as the channel 15 material because of its advantages in terms of band engineering and high mobility/offsets for both electrons and holes. The goal is to achieve high electron/hole mobility in the same channel material for N-‐ and P-‐channel MOS devices through the optimization of surface passivation, stoichiometry, heterostructure design and novel contact/interface engineering. Hetero-‐integration on a silicon substrate is another key challenge in enabling III-‐V CMOS. The hetero-‐ integration scheme for III-‐V CMOS transistors on silicon using the rapid-‐melt-‐ growth (RMG) technique is also demonstrated. The thesis is organized in the following way. Chapter 2 describes the modulation of surface bonding with an in-‐situ pre-‐ALD surface treatment, as well as the use of quantum confinement effects in minimizing the impact of surface defect states. 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Gupta, et al., “Towards high mobility GeSn channel nMOSFETs: Improved surface passivation using novel ozone oxidation method,” in Proc. IEDM 2012, Dec. 2012. [42] M. Yokoyama, et al., “CMOS integration of InGaAs nMOSFETs and Ge pMOSFETs with self-‐align Ni-‐based metal S/D using direct wafer bonding,” in Proc. VLSIT 2011, Jun. 2011. [43] D. Lin, et al., “Enabling the high-‐performance InGaAs/Ge CMOS: a common gate stack solution,” in Proc. IEDM 2009, Dec. 2009. [44] B. R. Bennett, R. Magno, J. B. Boos, W. Kruppa, M. G. Ancona, “Antimonide-‐based compound semiconductors for electronic devices: A review,” Solid-‐State Electronics, vol. 49, pp. 1875-‐1895, 2005. [45] B. R. Bennett, M . G. Ancona, J. B. Boos, B. V. Shanabrook, “Mobility enhancement in strained p-‐InGaSb quantum wells,” Appl. Phys. Lett., vol. 91, p. 042104, 2007. 21 [46] L. Xia, et al., “Performance enhancement of p-‐channel InGaAs quantum-‐well FETs by superposition of process-‐induced uniaxial strain and epitaxially-‐grown biaxial strain,” in Proc. IEDM 2011, Dec. 2011. [47] M. Yokoyama, et al., “Extremely-‐thin-‐body InGaAs-‐on-‐insulator MOSFETs on Si fabricated by direct wafer bonding,” in Proc. IEDM 2010, Dec. 2010. [48] H. Ki, et al., “Ultrathin compound semiconductor on insulator layers for high-‐ performance nanoscale transistors,” Nature, vol. 468, pp. 286-‐289, 2010. [49] N. Waldron, et al., “Integration of InGaAs channel nMOS devices on 200mm Si wafers using the aspect-‐ratio-‐trapping technique,” ECS Trans., vol. 45, no. 4, pp. 115-‐ 128, 2012. CHAPTER 2: SURFACE PASSVIATION IN ANTIMONIDE-‐BASED METAL-‐OXIDE-‐SEMICONDUCTOR DEVICES High interface trap density (Dit) at high-‐k dielectric/III-‐V interface is considered one of the main challenges for antimonide-‐based III-‐V metal-‐oxide-‐semiconductor field-‐effect-‐transistors (MOSFETs). In this chapter, we have investigated the effects of oxidant dosing on GaSb (001) surface prior to atomic layer deposition (ALD). It is shown that in situ H2O pre-‐pulsing leads to the formation of GaOx and SbOx and increase in the oxygen content at the interface, identified by X-‐ray photoelectron spectroscopy (XPS) analysis. Such interfacial layer leads to a reduction in Dit, and a Dit of 5×1011cm-‐2 near the valence band edge of GaSb is achieved. In the second part, we have investigated the suppression of interface state response using band engineering in III-‐V quantum well MOSFETs and experimentally verified the concept in the antimonide materials system using a gate-‐stack consisting of Al2O3/GaSb/InAlSb. It is shown that if the thickness of the interfacial layer of GaSb is scaled down to a few monolayers, the effective bandgap of the interfacial layer increases dramatically due to quantum confinement, which leads to the suppression of interface-‐trap response. 2.1 EFFECTS OF OXIDANT DOSING ON GASB (001) PRIOR TO ATOMIC LAYER DEPOSITION OF AL2O3 Antimonide-‐based compound semiconductors have recently emerged as potential candidate for replacement of silicon in future high-‐performance, low-‐ power complementary metal-‐oxide-‐semiconductor (CMOS) technologies, due to its excellent electron and hole transport properties [1-‐6]. Both n-‐ and p-‐channel devices of high performance have been demonstrated [2-‐9]. However, the highly 23 reactive nature of the surface of anitmonide compound has led to main challenges in achieving good passivation with high-‐k dielectrics and minimizing the interface trap density, which are critical for maintaining high carrier mobility. Atomic layer deposition of high-‐k dielectrics has been widely used to passivate surfaces of antimonide compounds. Natively grown III-‐V oxides are of complex structure and composition, thus pin the Fermi-‐level at the interface. Wet chemical cleans [8-‐11] and in situ hydrogen plasma exposure [12] prior to atomic layer deposition (ALD) are adopted to clean such GaOx and SbOx layers of poor quality. On the other hand, silicon-‐silicon dioxide, germanium-‐germanium dioxide interfaces are proven to give high-‐quality dielectric/semiconductor interfaces [13, 14]. Theoretical calculation shows high interfacial oxygen content at high-‐k dielectric/GaSb interface can eliminate any gap states [15]. Experimentally, SbOx grown during atomic layer deposition is found to be important for the modulation of the Fermi-‐level at the interface [10], which is achieved by low processing thermal budget and plasma-‐enhanced atomic layer deposition (PEALD) of dielectrics. These suggest the formation of high oxygen content interfacial oxide layer in a controllable way is the key to good modulation of charge on GaSb. In this section, we report an in situ surface treatment process for GaSb surface prior to ALD deposition of Al2O3. Pre-‐ALD oxidant exposure at low temperature is used to form high-‐quality interfacial oxide layer. Change in chemical bonding due to pre-‐ALD oxidant exposure of the substrate surface is investigated by X-‐ray photoelectron spectroscopy (XPS). It is found that high oxygen content at the interface could be achieved by careful control over initial nucleation steps. The spectroscopy results are correlated with frequency dispersion of MOS capacitors, conductance measurement and extracted interface trap density (Dit). 24 After degreasing with solvent, both n-‐ (Te doped, 5×1017cm-‐3) and p-‐type (undoped, ~1×1017cm-‐3 due to point defects) GaSb bulk substrates were cleaned using 1:1 diluted HCl for 5 min to remove native GaOx and SbOx, blown dried with N2 gas, and then immediately transferred into ALD reactor. Subsequently, the wafers were heated up to 400°C to further remove residual oxide by thermal desorption [6]. Prior to ALD of Al2O3 using trimethyl-‐aluminum (TMA) and H2O vapor as precursors, the samples were subjected to different pre-‐ALD pulsing treatments. Poor quality of the high-‐k/GaSb interface has been partly attributed to the presence of Sb-‐Sb dimers that create gap states [10]. Initial dosing of TMA is expected to form dimethyl-‐aluminum (DMA) by dissociative chemisorption, which bonds to Sb surface atoms, similar to the case of arsenide compounds [16,17]. Full coverage of DMA is thus desired to minimize Sb-‐Sb metallic bonding states. This was achieved by pre-‐pulsing TMA for 10 cycles at 200°C. Such temperature was chosen as it has been shown that the optimal temperature for ALD of Al2O3 on GaSb is below 200°C [9,10]. Pre-‐pulsing of H2O for 10 cycles at 100°C, was performed to terminate the remaining dangling bonds with hydroxyl groups and lead to the formation of GaOx and SbOx. Low substrate temperature was chosen to facilitate such chemical reaction and prevent deep oxidation [17]. Border traps in Al2O3 near the dielectric/semiconductor interface could lead to tunneling of carriers into defect states, thus degrades the device performance [18,19]. Therefore, after this step, the temperature was raised back to 270°C for the subsequent deposition of Al2O3 in order to guarantee its good quality. 8 nm / 12 nm Al2O3 was grown by alternatively pulsing of TMA and H2O for 80 / 120 cycles. The thickness was measured by ellipsometer. 100 nm W was sputtered in a different chamber. W was chosen due to its good thermal stability, thus allowing post-‐ metallization annealing at high temperature. Post-‐metallization annealing was done 25 at 350°C in forming gas (5% H2/95% N2) to remove fixed charge in the Al2O3 and further improve its quality [8]. Circular MOS capacitor structures with diameter of 50 μm were patterned by standard lithographic techniques and W was etched by SF6-‐O2-‐based plasma dry-‐etch. Backside substrate contacts were made by e-‐beam evaporation of 100 nm Au. Control samples went through the same process except for H2O pre-‐pulsing. Figure 2.1 Angle resolved XPS spectra (tilted at 25°) comparing the concentration of (a) GaOx and (b) SbOx in samples with and without H2O pre-‐pulsing following TMA pre-‐pulsing. Increase in GaOx/Ga and SbOx/Sb ratios can be observed in sample with H2O pre-‐pulsing. 26 Capacitance-‐voltage (C-‐V) measurements were acquired at a variety of temperatures at frequencies ranging from 1kHz to 1MHz. For all the measurements, the gate voltage was swept across the range-‐of-‐interest while the back contact was grounded. The effects of H2O pre-‐pulsing on the chemical composition at the interface were investigated using X-‐ray photoelectron spectroscopy (XPS) measurements. Samples for XPS measurements were fabricated following identical ALD procedure, except with only 15 cycles of TMA and H2O pulsing so that only ~1.5nm Al2O3 were deposited. Figure 2.2 The ratio of integrated peak area between GaOx and Ga, as well as SbOx and Sb in XPS spectra after annealing at different temperature for 1 min indicates GaOx and SbOx are thermally stable at temperature up to 400°C. Figure 2.1 plots the angle-‐resolved XPS analysis of the Ga 3d and Sb 4d peaks comparing samples with and without H2O pre-‐pulsing treatment. For both Ga and Sb peaks, sample with H2O pre-‐pulsing shows much higher ratios between GaOx/Ga and SbOx/Sb peaks. This indicates higher Ga-‐oxide and Sb-‐oxide contents at the interface. Since the binding energy of elemental Sb is similar to that of Sb when bonded to GaSb, the higher ratio of SbOx/Sb could also indicate the suppression of 27 elemental Sb by H2O pre-‐pulsing. This suggests the effectiveness of H2O pre-‐pulsing in the formation of high oxygen-‐content GaOx and SbOx, which is important towards reducing gap states [15]. This also proves that H2O pre-‐pulsing at low temperature (100°C) is an efficient and reliable method to form SbOx, since SbOx desorption reaction takes place significantly at temperature above 200°C [20,21]. Figure 2.3 high-‐frequency (100 kHz) capacitance voltage characteristics of W/12nm Al2O3/n-‐GaSb gate stack before and after forming gas annealing at 350°C for 1min. It has been reported that SbOx has poor thermal stability. SbOx can react with the GaSb surface forming elemental Sb and GaOx [10,20,21]. On the other hand, forming gas anneal (FGA) at 350°C could remove the fixed charge effect in Al2O3 by passivating its defects [8,18]. It is critical to passivate defects in the Al2O3 layer by post-‐metallization anneal while preserving a high-‐oxygen content oxide/semiconductor interface. Figure 2.2 plots the ratio of integrated peak area between GaOx/Ga and SbOx/Sb in XPS spectra after annealing at different temperature for 1 min. It is found that annealing at temperature up to 400°C does 28 not lead to significant change of the ratio between GaOx and Ga, as well as SbOx and Sb, indicating GaOx and SbOx remain stable with such thermal budget. Figure 2.4 Frequency dependence of peak accumulation capacitances shows the impact of border traps near the dielectric/semiconductor interface. Higher deposition temperature and post-‐metallization annealing lead to reduction in frequency dispersion. The high-‐frequency (100 kHz) capacitance-‐voltage characteristics of W/12nm Al2O3/n-‐GaSb gate stack before and after FGA are plotted in Figure 2.3. It is shown that flat-‐band voltage is negatively shifted and the hysteresis has been reduced from ~0.3V to ~0.05V, indicating FGA efficiently remove the fixed charge in the bulk of the oxide and/or at the oxide semiconductor interface without de-‐composition of SbOx. Peak capacitance in accumulation region increases slightly because of the densification of Al2O3 or/and recovery from plasma damage during the sputtering of W gate metal. 29 Figure 2.4 plots the accumulation capacitances at different frequencies to show the impact of border traps, as it is known that uniform frequency dispersions in the accumulation region can be attributed to traps in oxide near the interface [19]. It is shown that such frequency dispersions are 4.7%/dec and 2.8%/dec on the capacitors with Al2O3 grown at 200°C and 270°C respectively, which justifies that higher growth temperature is important for achieving high-‐quality oxide near the dielectric/semiconductor interface. The frequency dispersion is further suppressed to 1.5%/dec by post-‐metallization annealing at 350°C. To see the effect of H2O pre-‐pulsing, capacitance-‐voltage characteristics are compared between samples with and without the surface treatment in Figure 2.5 and 2.6 for n-‐type and p-‐type substrate respectively. Less frequency dispersion and better gate modulation (e.g. higher Cmax/Cmin ratio) can be observed for samples with oxidant dosing for different measurement temperatures. At room temperature, frequency dispersions in depletion region have been reduced from 5.0%/dec to 4.1%/dec and 1.3%/dec to 1.0%/dec for n-‐ and p-‐type substrates respectively. 30 Figure 2.5 Capacitance voltage characteristics of W/8nm Al2O3/GaSb gate stack as function of frequency on n-‐type substrate with and without H2O pre-‐pulsing. 31 Figure 2.6 Capacitance voltage characteristics of W/8nm Al2O3/GaSb gate stack as function of frequency on p-‐type substrate with and without H2O pre-‐pulsing. Figure 2.7 Cross-‐sectional HR-‐TEM image of the gate stack consists of ~7.3nm Al2O3 and W as gate metal. No clear sign of interfacial layer confirm the scalability of the approach. 32 The thickness of the interfacial layer is confirmed with the cross-sectional HR-TEM image of the gate stack as in Figure 2.7, which shows no clear sign of GaOx/SbOx layer. This proves that the formation of such oxide layer is on sub-nm level, thus does not put much challenge on further scaling of EOT. G /A q (cm−2eV−1) 11 x 10 10 p 5.5 log10(Frequency (Hz) ) a) 5 170K 8 4.5 6 4 4 3.5 2 3 −1 0 1 2 0 12 x 10 log10(Frequency (Hz) ) 5.5 5 300K 2 1.5 4.5 1 4 3.5 3 −1 0.5 −0.5 0 0.5 V (V) G 1 1.5 2 33 −2 −1 Gp/A q (cm eV ) 6 11 x 10 14 log10(Frequency (Hz) ) b) 12 5.5 170K 10 5 8 4.5 6 4 4 3.5 3 −1 2 0 V (V) G 1 2 Figure 2.8 Conduction plots (Gp/ωAq) of W/8nm Al2O3/GaSb gate stack with H2O pre-‐pulsing showing the trace of Fermi-‐level movements on a) n-‐type and b) p-‐type substrates. Measurement temperatures are indicated in the figure. Figure 2.8 show the conductance contour (Gp/ωAq) map of n-‐ and p-‐type samples with H2O pre-‐pulsing as a function of gate voltage and small-‐signal frequency at different temperatures, respectively. The trajectory of the peak value of conduction corresponds to the modulation of the Fermi level at the interface within the bandgap of GaSb. Peaks of conductance in the accumulation and inversion regions can be attributed to series-‐resistance or/and border traps, and the generation of minority carriers, respectively. Interface trap density can thus be extracted in the depletion regions for different measurement temperature. Figure 2.9 compares the extracted Dit values for samples with and without H2O pre-‐pulsing. The Fermi stabilization energy is 0.1eV from the valence band (VB) of GaSb [10]. Therefore, an asymmetric distribution is expected with more Dit towards 34 the conduction band (CB) edge. Reduction of Dit (>30%) by H2O pre-‐pulsing can be observed across the bandgap of GaSb, especially for energy levels near the conduction band edge. Near the valence band edge, a Dit value of 5×1011cm-‐2 is obtained, which is favored for antimonide-‐based p-‐channel devices. Figure 2.9 Comparison of extracted interface trap density (Dit) between samples with and without H2O pre-‐pulsing. H2O pre-‐pulsing efficiently reduces Dit especially at energy levels towards the conduction band edge. In summary, we have studied the formation of high-‐oxygen-‐content GaOx and SbOx interfacial layer on GaSb (001) surface by oxidant dosing at low temperature prior to atomic layer deposition. The suppression of elemental Sb and formation of GaOx and SbOx lead to less dispersion in capacitance-‐voltage characteristics and better gate modulation. Reduction of Dit and a Dit value of 5×1011cm-‐2 near the valence band edge are achieved by the proposed method, which makes antimonide-‐ based compound material a good candidate for ultralow power p-‐channel devices. 35 2.2 AMELIORATION OF INTERFACE STATE RESPONSE USING BAND ENGINEERING IN III-‐V QUANTUM WELL METAL-‐OXIDE-‐SEMICONDUCTOR FIELD-‐EFFECT TRANSISTORS High mobility III-‐V semiconductors have attracted increasing interest for replacing silicon as the channel material in complementary metal-‐oxide-‐ semiconductor (CMOS) applications due to their excellent transport properties. Field-‐effect electron/hole mobilities exceeding 6,000cm2/Vs [22,23] and 1,000cm2/Vs [24-‐26] at sheet charge densities near 1012/cm2 have been experimentally demonstrated with InGaAs and InGaSb as the channel material respectively. However, a main challenge remains in achieving good passivation on III-‐V materials and minimizing the impact of interfacial states which degrade the subthreshold slope (SS) and mobility in MOSFETs fabricated using these materials. Common solutions have included chemical clean [27,28], insertion of Si/Ge interfacial layer [29,30], sulfide treatment [31,32] and in-‐situ passivation [33,34]. While great progress has been made in reducing the interface trap density (Dit) recently, the Dit numbers achieved using approaches hitherto are nowhere close to the values obtained on silicon/SiO2 system, potentially due to interfacial dangling bonds and dimer pairs [35,36]. In this work, we propose to ameliorate the effect of interface states on MOSFET performance through the use of band engineering with an ultrathin interfacial layer. We demonstrate the concept on the antimonide system with InGaSb/InAlSb as the channel/barrier material. Ultrathin GaSb, on which good passivation can be achieved [8] as described in the previous section, is inserted between the barrier layer (InAlSb) and high-‐k dielectric (Al2O3), forming a quantum well of Al2O3/GaSb/InAlSb. It is shown that the effective bandgap of the interfacial GaSb/InAlSb layers rises dramatically with scaled thickness of GaSb due to the quantum confinement effect. This strong confinement effect in the proposed gate 36 stack not only guarantees there is no parallel conduction path through the thin GaSb layer, but also results in fewer carriers available near the interface to interact with the trap states. The concept is verified by the suppression of the response to interface-‐traps measured using the conductance method, well-‐behaved capacitance characteristics and excellent subthreshold swing of fabricated MOSFETs. Heterostructure stacks making use of a wide-‐bandgap barrier layer on top of a narrow-‐bandgap high-‐mobility channel material have commonly been used in high electron mobility transistors (HEMTs) in III-‐V materials with Schottky-‐gates. For InGaAs and InGaSb, aluminum (Al)-‐containing InAlAs and InAlSb provide band offsets that can confine carriers in the narrow bandgap channel in a heterostructure design [22,25,26]. For InGaAs another option for the barrier layer has been InP which is lattice matched to In0.53Ga0.47As, even though it has lower offset for electrons as compared to InAlAs [22]. More recently, people have applied these technique to MOSFETs as well [22,23], however their options for the barrier layer have been limited to InP, due to the difficulty of achieving a quality interface between high-‐k and Al-‐containing III-‐V semiconductors. Passivation of Al-‐containing III-‐V alloys has proven difficult mainly due to interfacial AlOx, which was found hard to remove using chemical cleaning / thermal annealing [11,27]. Improved carrier mobility has been observed with the use of an InP barrier layer and has been attributed to the reduction in surface roughness scattering and reduction in interaction with dielectric traps as the carriers in the channel are kept way from the dielectric interface [22,23]. It has been proven by both experiments and modeling that the advantages due to the addition of such a barrier layer outweigh the penalty in equivalent oxide thickness due to addition of the barrier layer; good SS and short channel effects can still be maintained in scaled devices [37,38]. 37 Figure 2.10 Band diagram and Fermi-‐level movement during MOSFET operation for a) high-‐k dielectric/bulk GaSb; b) high-‐k dielectric/thick GaSb/InAlSb/InGaSb; c) high-‐k dielectric/ultra-‐thin GaSb/InAlSb/InGaSb. In both (a) and (b), electrons (ρe) and holes (ρh) at the interface could interact with interface defects. Quantum confinement effect becomes more dominant as the thickness of interfacial GaSb layer scales down as in (c). A dramatic increase of subband energies results in fewer carriers near the interface. Therefore, the interaction between interface traps and carriers is suppressed. Figure 2.10 describes the concept behind our approach; it shows the Dit distributions, band diagrams and Fermi-‐level movements during device operation for a) high-‐k dielectric/bulk GaSb; b) high-‐k dielectric/thick GaSb/InAlSb/InGaSb; c) high-‐k dielectric/ultra-‐thin GaSb/InAlSb/InGaSb. For these devices, to effectively switch the device, the Fermi-‐level has to move from valence band edge to mid-‐gap of the channel for p-‐channel devices, and from conduction band edge to mid-‐gap of the channel for n-‐channel. In either case, for device a) the inversion carriers (ρe, ρh) right at the interface will interact with (charge and discharge) the defect states, which results in both the loss of carriers density and mobility degradation. Adding an Al-‐containing wide bandgap cap layer shields the impact of the interfacial defects on the carriers’ mobility. To achieve a sharp and high-‐quality high-‐k interface, 38 termination of InAlSb with GaSb has been proposed as a solution [11,39]. For GaSb, good surface passivation has been achieved and a typical U-‐shaped Dit distribution is observed with higher Dit level expected towards the conduction band edge [38]. Since the physical interfaces between the high-‐k dielectric/semiconductor throughout the three cases are the same, we can assume they give similar Dit distribution within the energy gap. When such an interfacial layer of GaSb is inserted, a type-‐I heterostructure is formed between the high-‐k dielectric/GaSb/InAlSb. When the thickness of the interfacial GaSb layer is larger than a few nanometers, quantum confinement effects in such quantum wells are marginal. As the Fermi-‐level moves during the switching of the devices, it leads to accumulation of carriers (ρe, ρh) in the GaSb layer, thus causing a parallel conducting path and equivalent surface channel operation. As the thickness of the interfacial layer scales down to a few mono-‐layers, the quantum confinement effect becomes dominant enough so that both the lowest electron and hole subband energies are far away from the band edges. Therefore, the accumulation of carriers in the interfacial layer can be eliminated. Meanwhile, due to the absence of carriers right at the interface, the interaction between carriers and interface defects can be thus potentially suppressed. To simulate this quantum confinement effect, a tight-‐binding (TB) approach was used to model the electronic band structure of high-‐k dielectric/GaSb/InAlSb heterostructure [40]. Tight-‐binding parameters for ternary compound are calculated following virtual-‐crystal approximation (VCA) and fitted to bulk band parameters [41]. On-‐site parameters are shifted to incorporate band offset between semiconductors. The surface orientation was set as (001), and the semiconductor interface was considered as hydrogen passivated to eliminate all gap states. Therefore, an infinite potential barrier was assumed at the high-‐k/GaSb interface [42]. Hamiltonian is constructed based on the supercell approach by selecting one representative atom in each atom layer [43]. 39 Figure 2.11 Dependence of the effective bandgap (Egeff) of the GaSb/InAlSb heterostructure on the thickness of the interfacial GaSb layer (TGaSb) in terms of monolayers. When TGaSb is smaller than a few monolayers, the effective bandgap of GaSb/InAlSb approaches that of InAlSb alone. Figure 2.11 shows the dependence of the simulated effective bandgap (Egeff) of the heterostructure on the thickness of the interfacial GaSb layer (TGaSb). Egeff increases dramatically with decreasing number of the layers of Ga/Sb atoms. Subsequently, as the thickness decreases down to a few monolayers of atoms, the effective band gap almost approaches that of InAlSb alone. This indicates that as long as the thickness of the interfacial GaSb is kept below a few monolayers, the stack is partially equivalent to having just wide bandgap InAlSb alone in terms of band energies. The benefit is that the physical interface between the high-‐k dielectric and the semiconductor is now between the high-‐k and GaSb, thus problems involving AlOx are avoided. Experimentally, the proposed heterostructure was realized using molecular beam expitaxy (MBE). The specific stack consisted of two monolayers (0.6nm) of 40 GaSb/In0.2Al0.8Sb (3nm for p-‐channel, 10nm for n-‐channel)/In0.2Ga0.8Sb (7nm for p-‐ channel, 10nm for n-‐channel) with ~1um Al0.8Ga0.2Sb buffer layer/GaAs. The unintentionally doped stack was p-‐type due to the charged native defect states [4]. For n-‐channel samples, tellurium (Te) delta-‐doping was added in both top barrier and buffer layers during MBE growth [25]. To minimize the exposure with atmosphere, samples were capped with 50nm arsenic in the MBE system then transferred to the atomic-‐layer-‐deposition reactor. A clean (001) surface was prepared by heating up the samples up to 400°C under nitrogen purging, in order to decap the arsenic completely. This decapping process was carefully monitored by recording chamber pressure. Subsequently, an Al2O3 film was deposited at 300°C using trimethylaluminium and H2O as precursors. Smoothness on the atomic level of the interface between the high-‐k dielectric and the semiconductor heterostructure can also be achieved with in-‐situ techniques [33,34]. After the deposition of Al2O3, aluminum was deposited using electron-‐beam evaporation, then patterned to form a gate electrode. The top channel contact was formed by etching Al2O3. Then the ohmic contacts were formed by evaporation of Ti/Ni for p-‐channel devices and Au/Ni/Ge/Au for n-‐channel devices. Forming-‐gas anneal at 350°C was performed for 30 minutes to further improve the high-‐k film and interface quality. Control samples undergo the same process except the substrate is bulk GaSb with no heterostructure. Capacitance and conductance measurement were performed on both the heterostructure and the control samples. Both p-‐ and n-‐type capacitors built on the heterostructure show marginal frequency dispersion (<2.4%/dec for p-‐type, <2.6%/dec for n-‐type) at 200K as shown in Figure 2.12 (a) and (b) respectively. Since interface properties, and specifically high Dit level, are one of the major causes of frequency dispersion in C-‐V measurements, this absence of significant dispersion indicates the minimal impact of Dit. A few mono-‐layers of interfacial GaSb can be clearly identified in HR-‐TEM image in Figure 2.12 (c). 41 Figure 2.12 Capacitance measured on the heterostructure with both (a) p-‐ and (b) n-‐ doped channel. Marginal dispersions have been observed at 200K, indicating minimal impact of interface traps on the capacitance. (c) Ultra-‐thin interfacial layer of GaSb can be clearly identified in HR-‐TEM image. Figure 2.13 Measured conductance response for the heterostructure compared to bulk GaSb as the control sample. Biasing condition is set to give near flat-‐band conditions for both cases. Nearly one order-‐of-‐magnitude reduction in conduction peaks is observed for the heterostructure compared to control sample. 42 Figure 2.13 plots the conduction response, which is indicative of the interface state response [44]. We observe an order of magnitude reduction in the magnitude of conduction peaks from the sample with the heterostructure in this work compared to the control sample of bulk GaSb. The gate biasing is set to give near flat-‐band conditions for both cases. Since the physical interfaces in the two cases are the same, this demonstrates the suppression of interaction between carriers and the interface traps due to the effect of band engineering. The result is in qualitative agreement with the modeling analysis from tight binding, as the interface trap response is proportional to the number of carriers available at the interface, which in turn depends exponentially on the effective bandgap. Figure 2.14 Transfer characteristics of both (a) p-‐ and (b) n-‐channel MOSFETs built on the heterostructure in this work, showing sharp switching behavior. Subthreshold swings are 33mV/dec and 61mV/dec for n-‐ and p-‐channel devices respectively, close to the thermal limit of ln10 kT/q V/dec. 43 I-‐V measurement on the MOSFETs fabricated on the proposed heterostructure give sharp switching (low SS) for both p-‐ and n-‐channel devices as shown in Fig. 2.14 (a) and (b) respectively, close to the thermal limit of 30mV/dec at 150K and 24mV/dec at 120K. These measurements on C-‐V, conductance response and MOSFET characteristics indicate this technique is successful in ameliorating the response of interface states in III-‐V semiconductors and can be effectively applied in a MOSFET fabrication process flow. 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CHAPTER 3: INGASB: SINGLE-‐CHANNEL SOLUTION FOR III-‐V CMOS There has been an upsurge of interest in the possibility of a low-‐power, high-‐ performance CMOS based on III-‐V materials. For such a technology to be realized, comparable high performance from both n-‐ and p-‐channel devices is needed for complementary logic. The 6.1-‐6.2Å lattice constant system with InGaSb as the single channel has significant advantages in terms of high mobility, high sheet charge density, and large band offsets for both electrons and holes. We demonstrate, for the first time in antimonide systems, n-‐ and p-‐channel MOSFETs using a single channel material. Electron and hole mobilities greater than >4000 and 900cm2/V-‐sec have been achieved, respectively. The InGaSb NMOSFETs are the first of their kind, and when combined with PMOSFETS in the same material, form an attractive approach for next generation high speed, low power CMOS circuits. 3.1 TIGHT-‐BINDING STUDY OF Γ-‐L BANDSTRUCTURE ENGINEERING FOR BALLISTIC INGASB NMOSFETS nMOSFETs based on III-‐V materials have the highest mobility/injection velocity (νinj), the major concern, however, is the degradation of device performance due to low density-‐of-‐states (DOS) (low effective mass of carriers) and excessive spillover of the charge from Γ-‐ to L-‐valley at high sheet charge [1-‐2]. As we increase the In% in InGaAs / InGaSb channel nMOSFETs: νinj and separation between and the Γ-‐ to L-‐ valley (ΔΓ-‐L) increases while DOS decreases. In this section we study this tradeoff in InXGa1-‐XSb, which is a promising candidate for replacing silicon as the channel 52 material of future high-‐speed, low-‐power CMOS devices, showing high mobility for both electrons [3] and holes [4]. Figure 3.1 Structure of InGaSb double-‐gate MOSFET with (100) orientation. Atom arrangement under VCA. For performance evaluation of ultrathin-‐body (UTB) double-‐gate devices, the use of bulk effective masses may not be adequate [6]. The E-‐k relations for InXGa1-‐XSb UTB MOSFET (Fig. 3.1) is calculated using sp3d5s* atomistic tight-‐binding (TB) model coupled with Poisson’s equation. The effect of varying the In % on DOS, electron population /separation among Γ-‐, L-‐, and X-‐valleys is studied systematically. E-‐k band diagram for UTB MOSFET with GaSb and InSb channel is plotted in Fig. 3.2(a). Amongst different valleys of electrons, Γ-‐valley has lower effective mass, thus lower DOS and higher νinj. For GaSb (low In% InXGa1-‐XSb) ΔΓ-‐L may not be sufficient; L-‐valley can also be populated, which has higher DOS but lower νinj. Increasing In% in the compound brings up L-‐ and X-‐valleys, reduces the energy for Γ-‐valley, meanwhile reducing the effective mass of Γ-‐valley. However, high In% makes it difficult to achieve high electron sheet charge density (NS) from Γ-‐ 53 valley. From drive current perspective, high νinj and NS have to be achieved simultaneously, which requires engineering of DOS, νinj and electrons population in different valleys [3]. This trade-‐off between DOS and νinj is summarized in Fig. 3.2(b). Figure 3.2 (a) Band diagrams of GaSb, In0.5Ga0.5Sb and InSb; (b) summary of the bandstructure effects by varying In% in InGaSb and their relationships. TB parameters for ternary InXGa1-‐XSb are calculated following virtual-‐crystal approximation (VCA) incorporating compositional disorder effect and fitted to bulk band gap of ternary compound [7-‐9]. 1D Poisson’s equation perpendicular to channel direction is coupled with TB Hamiltonian by Hartree-‐Fock potential in the gate stack. Dangling bonds at interface are passivated by hydrogen termination of hybridized orbitals to eliminate all the states within band gap [10]. A ballistic 54 transport model is adopted to assess transport of electrons [11]. νinj is determined from full band structure with non-‐parabolic E-‐k relationship considered for all valleys. Figure 3.3 Calculated bandstructure from TB for InGaSb at sheet charge density ~3×1012cm-‐2 with a body thickness of 4nm. Band structures of InXGa1-‐XSb at NS of ~3×1012cm-‐2 for different In %’s are compared in Fig. 3.3 (TBODY=4nm). Each series of curves in the E-‐k plot represents each sub-‐band, black and blue for conduction bands and valence bands respectively. To achieve high νinj at relevant NS, it is important to confine sufficient amount of electrons in high-‐ νinj Γ-‐valley. The overall population among different valleys is determined by the energy separations as well as difference in DOS among Γ-‐, L-‐, and 55 X-‐ valleys. For low In % InXGa1-‐XSb, because of quantum confinement (QC) effects, the energy difference between Γ-‐ and L-‐valleys is marginal, especially under high VG and thin body thickness, resulting in Fermi level moving into L-‐valley. Band gap (Eg) and ΔΓ-‐L are shown in Fig. 3.4: with higher In%, ΔΓ-‐L is increased to confine more electrons in Γ-‐valley counteracting the effects of quantization (Fig. 3.4(a)), which is more dominant for thin TBODY (Fig. 3.4(b)). At higher NS (/VG), though Eg is lowered due to Quantum Confinement Stark Effect [12], ΔΓ-‐L stays low (Fig. 3.4(c)). This can be attributed to Γ-‐valley’s curvature getting blunt (effective mass becomes larger) at high NS, thus alleviated quantization effect. Figure 3.4 Calculated bandgap and Γ-‐L energy separation vs. (a) In composition for 4nm body thickness and ~1011 and 1012 cm-‐2 sheet charge density; (b) body thickness at sheet charge density of 1012 cm-‐2; (c) sheet charge density for 4nm body thickness. Fig. 3.5 plots the 2-‐D DOS, Γ-‐valley has much lower DOS compared with L-‐valley which is required to achieve high NS. In-‐rich compounds lead to decrease of DOS at 56 conduction band edge meaning further movement of Fermi level is necessary to achieve same NS. Figure 3.5 2D density of states for GaSb and InSb for body thickness of 4nm. % occupation of electrons in Γ-‐, L-‐valleys in InXGa1-‐XSb is plotted against In %, TBODY and NS in Fig. 3.6. From ΔΓ-‐L, adequate percentage of charge can be confined in Γ-‐valley even at high NS and thin TBODY. Fig. 3.7 illustrates (a) sheet charge density as a function of gate voltage and (b) sub-‐threshold swing comparison. The kink in charge density indicates the population of electrons into L-‐valley. For higher In composition, loss in DOS at the band edge costs more gate voltage to obtain sheet charge density of a reasonable level for device operation. The change in DOS as well as dielectric constant (from 14.4 GaSb to 16.8 InSb) reflects on the degradation of sub-‐threshold swing with increasing In %. For device geometry of interest, DOS determined quantum capacitance has an evident impact on the subthreshold behavior as subthreshold swing decreases with larger TBODY. 57 Figure 3.6 Fraction f electron occupation in Γ-‐valley in InXGa1-‐XSb vs. (a) In composition for 4nm body thickness and ~1011 and 1012 cm-‐2 sheet charge density; (b) body thickness for 1012 cm-‐2 sheet charge density; (c) sheet charge density for 4nm body thickness. νinj: ID-‐VG is evaluated by integrating NS with average velocity of electrons along transport direction at each k point. <100> is set as the transport direction. Under the ballistic transport model, when Fermi level is below conduction band edge, the injection velocity stays constant; it increases as Fermi level moves into conduction band. The average velocity at given gate bias can be calculated by taking the ratio between the overall current density and sheet charge density [11]. As shown in Fig. 3.8, since electron population is mostly in L-‐valley, the overall injection velocity of GaSb is low. Ga-‐rich InXGa1-‐XSb has low νinj as most of the electrons are in L-‐valley at high NS. In-‐rich compound gives high νinj, because of sharper curvature of Γ-‐valley in calculated E-‐k relation. The high injection velocity is maintained even at high NS as electrons are properly confined in Γ-‐valley. 58 Figure 3.7 (a) sheet charge density as a function of gate voltage. Gate voltage is adjusted to give 5×107cm-‐2 sheet charge at 0V; (b) subthreshold swing with varing In composition for body thickness of 4nm and 5nm. For the optimal overall driving capability, InXGa1-‐XSb can gain from injection velocity and DOS of L-‐valley simultaneously. In Fig. 3.7 (a), the filling of L-‐valley gives increase in NS. Without excessive filling of L-‐valley, average injection velocity maintains high as shown in Fig. 3.8. With these factors combined, Fig. 3.9 shows proper amount of In percentage (~25%) in InXGa1-‐XSb can give a overall improvement in drive-‐current. Further increase in In composition leads to significant loss in NS. The optimal current density is 80% higher than silicon, 50% higher than GaSb and 160% higher than InSb. Impact of quantum capacitance on subthreshold swing for In-‐rich compound is avoided for In percentage of ~25% as well. 59 Figure 3.8 Injection velocity as a function of sheet charge density for different In composition, the drop in injection velocity at high sheet charge density is due to L-‐ valley population. Figure 3.9 Saturation current as a function of gate voltage; Gate voltage is adjusted to give 15uA/um current density at 0V. 60 In conclusion, by using an sp3d5s* TB model, we explored the energy dispersion relations of InXGa1-‐XSb UTB device. Ballistic currents for nMOSFETs are calculated based on full band analysis. It is shown that band structure engineering of InXGa1-‐ XSb allows sufficient electron population in Γ-‐valley to maintain high injection velocity, meanwhile avoids the degradation of sheet charge density due to quantum confinement and loss in DOS. Optimal design of InXGa1-‐XSb channel can deliver ~80% improvements in drive current under ballistic limit for low supply voltage application compared with silicon. 3.2 HETEROSTRUCTURE DESIGN FOR SINGLE-‐CHANNEL III-‐V CMOS As Moore’s law is approaching the sub-‐20nm regime, III-‐V semiconductors are considered as promising candidates for potentially replacing silicon as the channel material in future technology nodes due to their high-‐performance and low-‐power advantages [12]. Most of the research in the community has been focused on the excellent electron transport in various III-‐V material systems demonstrated over the years [13,14]. However, the hole mobility achieved in III-‐V quantum wells has traditionally lagged behind in comparison to silicon. The requirements on circuit design for complementary logic suggests that a future III-‐V CMOS technology should strive for a PMOS that can deliver no worse than one-‐third of the current density of the NMOS transistor [15]. It has been proposed that the relatively high mobility for holes in germanium could make it a potential PMOS device to complement the III-‐V NMOS [16,17]. However, this can result in complications in CMOS circuit design and manufacturing, such as cross-‐contamination problems associated with co-‐ integration of group IV and III-‐V materials on a common Si platform and different 61 gate stack solutions for Ge and III-‐V. Thus it would be worthwhile to explore if a single material system can enable both good NMOS and PMOS transistors. To realize CMOS in a single material system, progress has been made on Ge NMOS and InGaAs PMOS in hopes of getting both high-‐performance CMOS transistors in either Ge [18] or InGaAs [19] systems. Meanwhile, antimony (Sb)-‐ based compound semiconductors have the highest electron and hole mobilities among all III-‐V materials. The electron saturation velocity in InSb is the highest among all the conventional semiconductor materials. Schottky-‐gate FETs with an InGaSb n-‐channel have achieved fT of 305GHz at 85nm gate length [20] and fT of 140GHz at 40nm gate length for p-‐channel [21]. Heterostructures with an InGaSb channel exhibiting a room temperature electron mobility of 25,000cm2/Vs (21,000cm2/Vs) with a sheet carrier density of 1.5×1012/cm2 (2.8×1012/cm2) have been achieved [22,23]. Room-‐temperature hole mobility as high as 1,500cm2/Vs in a strained InxGa1-‐xSb channel at a sheet charge density near 1012/cm2 has also been demonstrated [24]. In addition to good mobilities for the electrons and holes, InxGa1-‐xSb has high conduction and valence band offsets with AlxIn1-‐xSb and AlxGa1-‐xSb for flexible heterostructure design [25]. Despite the larger lattice constants, antimonides are also found to be potentially more suitable for heterointegration [26]. Thus, InxGa1-‐ xSb has the potential to enable a complementary technology with both high performance NMOS and PMOS in a single channel material, outperforming silicon [25-‐27]. In this section, we study the type-‐I heterostructure design of the AlxGa1-‐ xSb/InxGa1-‐xSb system. Carrier transport in the heterostructure is investigated by gated Hall measurements. High-‐mobility InGaSb n-‐ and p-‐channel MOSFETs using the same channel material are reported for the first time. 62 Figure 3.10 Schematic of the heterostructure studied in this work. Fig. 3.10 shows the schematic of the heterostructure design studied in this work. The stack grown by molecular beam epitaxy on semi-‐insulating GaAs substrate [26] consists of a 1um thick AlGaSb buffer layer, a 10nm InGaSb channel, which is capped with an InAlSb top barrier. For p-‐channel devices, the channel was unintentionally doped p-‐type due to the charged native defect states. For n-‐channel devices, both the top and bottom barrier layers of AlInSb and AlGaSb were delta-‐doped with Te to provide carriers to the acess region. InGaSb of low InSb mole fraction was chosen because of its potential to properly confine charge in Γ-‐valley and achieve optimal trade-‐off between the density-‐of-‐state and the injection velocity [27]. Cross-‐sectional TEM image of the heterostructure stack is shown in Fig. 3.11. 0.04um AlSb nucleation layer is grown first, which is proven to give better surface morphology. Misfit dislocations are generated at the interface between antimonide layers and GaAs substrate due to the lattice mismatch between the substrate and buffer. It can be observed that most of the dislocations/defects are contained in the buffer layer, thus it is possible to obtain good crystal quality near the channel layers. 63 Figure 3.11 Cross-‐sectional TEM image of the heterostructure stack grown by Molecular Beam Epitaxy (MBE). The stack is grown on GaAs substrate. The lattice-‐ mismatch is released by 1μm thick AlGaSb buffer layer. The type-‐I band alignment formed by AlGaSb/InGaSb heterostructure is shown in Fig. 3.12. The valence-‐band offset (VBO) of 0.30eV can be determined by comparing the valence band (VB) spectrum of InGaSb and AlGaSb using the Ga peak as a reference as in Fig. 3.13(a). Bandgaps of InGaSb (Fig. 3.13(b)), AlGaSb (Fig. 3.13(c)) and GaAs (Fig. 3.13(d)) are extracted from photoluminescence measurement at 80K to be 1.32eV, 0.70eV and 1.5eV respectively. The conduction-‐band offset (CBO) between AlGaSb and InGaSb can thus be calculated to be 0.32eV. The information of band-‐energies is summarized in Fig. 3.11. Therefore, such a heterostructure can provide both decent CBO and VBO, and thus has the potential to properly confine both electrons and holes. 64 Figure 3.12 Band energies of the type-‐I heterostructure formed by InGaSb/AlGaSb, which offers sufficient CBO/VBO to confine both electrons and holes. Figure 3.13 (a) VBO is measured using UV-‐XPS by taking the difference between VB spectrum from the channel and the buffer layer. Bandgaps of (b) AlGaSb, (c) InGaSb and (d) GaAs are measured using photo-‐luminescence (PL) at 80K. 65 The confinement of carriers is studied using a tight-‐binding simulation [7-‐9]. Fig. 3.14 (a) shows the accumulation of both electrons and holes in a double-‐gate structure with 2nm AlGaSb barrier layer, 8nm-‐thick InGaSb channel and 0.5nm equivalent-‐oxide-‐thickness (EOT). High sheet charge density and reasonable switching of devices can be obtained in the heterostructure even with such highly scaled electrostatics. The percentage of carriers that is confined in the high-‐mobility channel is plotted in Fig. 3.14 (b). At sheet charge densities (NS) relevant for MOSFET operation, 80/90% of the electron/hole can be properly confined. Figure 3.14 Results from tight-‐binding calculations show (a) heterostructure design can provide high NS at given gate voltage. Nearly eight orders-‐of-‐magnitude switching of sheet charge densities can be obtained within 1V for both carriers; (b) most of the charge (above 80% and 90% of electrons and holes respectively) is confined in the high-‐mobility channel even at high sheet charge density up to 1013cm-‐2. Device-‐quality surface passivation on the stack can be achieved by covering the surface with ultra-‐thin layer of GaSb, on which a high-‐k dielectric of Al2O3 was deposited by atomic-‐layer-‐deposition (ALD) [28]. To study the transport of carriers, structure for gated Hall measurement was fabricated on the samples. In Fig. 3.15, the heterostructure show 7X / 2.5X higher electron mobility (μe) and 7X / 4X higher 66 hole mobility (μh) at an NS of 1012cm-‐2\6x1012cm-‐2 for electrons and holes respectively, in comparison to silicon. Figure 3.15 a) Electron and (b) hole mobility measured in InGaSb channel as a function of sheet charge density (NS) using gated Hall measurement. Electron and hole mobility of 4000cm2/Vs and 900cm2/Vs can be obtained at sheet density of 1012cm-‐2 respectively, and are 2.5X and 4X as compared with Si universal even at high NS. The electron transport can potentially be further enhanced by increasing the In composition in the channel material, since InSb has the highest electron mobility amongst all the conventional semiconductors. However, this approach has its drawbacks. High In% InGaSb leads to low DOS of electrons, thus eventually result in 67 excessive loss in sheet charge density as described in the previous section. Another factor is the strain effect. Based on current buffer design, which consists of 1um thick AlGaSb, the channel layer of InGaSb grown on top is compressively strained. Figure 3.16 X-‐ray diffraction of 004 rocking curve of the heterostructure stack that consists of 1um thick AlGaSb buffer layer, a 10nm InGaSb channel grown on top of GaAs SI substrate. Fig. 3.16 shows the XRD [004] rocking curve of the heterostructure stack. Buffer layer of AlGaSb is fully relaxed on GaAs substrate. The channel layer grown on top has a larger lattice constant with respect to the buffer layer, thus is compressively strained. Using In0.2Ga0.8Sb as the channel material, the strain can be estimated to be 0.7%. Compressive strain is expected to split the heavy and light hole bands near the Γ-‐point. For holes, such splitting of bands results in more holes population in the light hole band of lower transport mass. Therefore, compressive strain is beneficial to hole transport. On the other hand, compressive strain raises up the band edge of 68 Γ-‐valley, meanwhile decrease its curvature. Thus the transport mass of Γ-‐valley increases, and mobility could be lowered. 3.3 SURFACE-‐CHANNEL INGASB CMOS TRANSISTORS Due to the poor recovery of crystalline quality after implantation associated with GaSb, it is favorable to adopt a device architecture that allows an implantation-‐free process for MOSFETs fabrication. Figure 3.17 Raman spectrum of CZ-‐grown bulk GaSb and GaSb after Be implantation and consequent annealing. Fig. 3.17 shows the Raman spectrum of CZ-‐grown bulk GaSb and GaSb after Be implantation (ion energy of 10keV, dose of 9x1014cm-‐2) and consequent annealing at 350°C for 30mins. The main peaks correspond to LO-‐phonon mode. After the 69 implantation, the peak is shifted to the left and broadened, which is an indication of poorer crystalline quality due to the incomplete recovery of crystal structure even after annealing. Therefore, it is desirable to develop an implant-‐free device structure and process flow for transistors. S/D designs with low extrinsic resistance are challenging for III-‐Vs, because of low solubility and poor activation of dopants. Use of metal S/D overcomes these problems, a slight overlap is introduced between the gate and S/D electrodes to reduce the access resistance as shown in Fig. 3.18. There is a 2μm overlay region between the S/D and the gate electrodes with Al2O3 inserted in between. Figure 3.18 Metal S/D structure, in which a slight overlap of gate and S/D electrodes is introduced to lower the access resistance. Top surface layers are n-‐type or p-‐type doped for NMOS or PMOS respectively. Both PMOS and NMOS are fabricated on the same heterostructure stack except with the top layer being intrinsically p or n-‐doped respectively. After MBE growth, the samples are capped with elemental arsenic to protect the surface from oxidation during the transfer. After solvent clean to degrease the samples, they are transfer 70 into atomic layer deposition machine. The base pressure of the main chamber is approximately 100mTorr. The samples were subject to heating up to 400°C for 10mins. This guarantees that all the arsenic is fully decapped inside the ALD chamber and fresh surface of antimonide, free from oxidation is prepared for ALD of Al2O3. After the growth of gate dielectrics, gate electrodes were deposited and patterned using lift-‐off process. Contacts to the channel were made after removal of Al2O3, followed by lift-‐off of the contact metals of Ti/Ni. Well-‐behaved CGC-‐V characteristics are obtained on both p-‐ and n-‐type samples. Figure 3.19 Well-‐behaved CGC vs VG characteristics are obtained on both a) p and b) n-‐type InGaSb surface channel devices. 71 For devices, initially 2nm Al2O3 was deposited after the decapping of arsenic. Source/drain electrodes were deposited and patterned using lift-‐off of 5nm Pt. Al2O3 is then removed by 2% HF dip, then immediately transferred into ALD chamber. 10nm / 25nm Al2O3 were deposited on p-‐ / n-‐channel devices respectively. Gate electrode is then deposited and an overlap of 2um is intentionally introduced between the gate and S/D electrodes. Finally, Al2O3 was etched at the S/D pads for probing. Transfer and output characteristics of the transistors are shown in Fig. 3.20 and Fig. 3.21, respectively. On/off ratios of 104 and 100 are achieved for PMOS and NMOS respectively. SS values are ~160mV/dec and ~500mV/dec correspondingly. The switching characteristics of the devices is limited by the leakage through the buffer layers. On-‐current of n-‐channel device is largely limited by the contact resistance due to the factor that Fermi-‐level is severely pinned near valence band edge of InGaSb. Figure 3.20 Transfer characteristics for a) PMOS and b) NMOS with metal S/D. NMOS ID-‐VG scales linearly with drain voltage due to the high contact resistance. 72 Figure 3.21 Output characteristics for a) PMOS and b) NMOS with metal S/D. NMOS drain currents are largely limited by the high contact resistance. Due to the severe Fermi level pinning and high contact resistance for n-‐type contacts, the overall resistance of n-‐channel devices is dominated by contact resistance. To improve the n-‐type contact, a TiO2 interfacial layer was inserted to lower the barrier height for electron injection. In contrast to other MIS schemes for Fermi-‐level unpinning, TiO2 lowers the barrier height without introducing tunneling resistance due to the low CBO of TiO2/GaSb. More than 5X improvement in ION is obtained for NMOS with introduction of TiO2, as shown in Fig. 3.22. The NMOS on-‐ state current remains limited by contact resistance due to the thinness of the surface channel and consequent depletion of electrons in the contact regions. This leaves room for further improvement in the device performance of NMOS with MIS S/D contacts. 73 Figure 3.22 Structure of n-‐channel devices with TiO2 inserted in between the semiconductor and metal at S/D. 5X increase in on-‐state current for NMOS is achieved with the insertion of TiO2. To investigate metal contact on antimonides, we built Schottky diodes on moderately doped n-‐ and p-‐type GaSb substrates of carrier concentration ~1017cm-‐ 3. Native oxides were removed by HCl clean. Metals were deposited by e-‐beam evaporation and patterned to make top electrode. Backside contact was formed using blanket evaporation of metal to measure diode I-‐V. Ideally, by Schottky-‐Mott relation, low workfunction metals such as Al and Ti would give higher Schottky barrier for holes than for electrons. Strong Fermi-‐level pinning is observed at metal/GaSb interface. Fig. 3.23 (a), (b) show the J-‐V characteristics of Al/n-‐, p-‐GaSb, and Ti/n-‐, p-‐GaSb respectively. Both Al and Ti show rectifying behaviors on n-‐GaSb and ohmic contact on p-‐GaSb. Lower (higher) Schottky barrier height for metal/p-‐ 74 (n-‐) GaSb is confirmed with temperature dependence measurement of Al/GaSb Schottky diode as shown in Fig. 3.24. Due to the intrinsic gap state distribution, the charge-‐neutral level (ECNL) is found to be near valence band edge as shown in Fig. 3.25. These confirm that antimonide (Sb binary and Sb rich ternary) compound exhibits Fermi-‐level pinning towards valence band. Figure 3.23 I-‐V characteristics of (a) Al/GaSb (b) Ti/GaSb contacts on both n-‐type and p-‐type substrate. Figure 3.24 Temperature dependence of I-‐V characteristics of Al/GaSb Schottky diodes. 75 Figure 3.25 Band diagrams of metal contacts to n-‐type and p-‐type GaSb. Leakage current of the devices is limited by the leakage through buffer layer beneath the channel. Point defects in antimonide can lead to shallow acceptor-‐type energy levels within the bandgap, and thus can be p-‐type activated. Because of this, undoped GaSb is p-‐type doped. For the same reason, point defects in the buffer layer can contribute to p-‐type conduction. Leakage current could be further reduced if the defect states in the buffer layer were deactivated. Fig. 3.26 shows the temperature dependence of the transfer characteristics of the p-‐channel devices. At low temperatures, the leakage current is greatly reduced. An on/off ratio of 107 is obtained at 77K. Therefore, in heterostructure device, it is critical to control the point defects in the buffer layer in order to achieve low leakage. Figure 3.26 Temperature dependence of the transfer characteristics of p-‐channel devices shows the significant drop in leakage current at low temperature due to the deactivation of p-‐type defect states. 76 3.4 BURIED-‐CHANNEL INGASB CMOS TRANSISTORS Because of the Fermi-‐level pinning near the valence band edge and thin channel thickness of the surface channel devices, population of electrons in the channel is difficult to achieve. Fig. 3.27 shows the simulation results of electron profile for different doping levels (1017cm-‐3, 1018cm-‐3, 1019cm-‐3) in the surface channel. 1.0 n p 1 10 1 -1 10 -4 10 0.5 -5 10 increasing ND -6 10 -7 10 -3 18 E - EF (eV) -3 10 n and p (10 cm ) -2 10 -8 10 -9 10 0.0 -10 0 5 10 15 10 20 z (nm) Figure 3.27 Band diagrams and carrier concentration profile (blue: electrons, red: holes) of the surface channel device with 10nm InGaSb as the channel and AlGaSb as the buffer layer. The surface is terminated with 1nm GaSb and the Fermi-‐level is pinned at 0.1eV from the valence band edge of GaSb. Doping levels are changed from 1017cm-‐3, 1018cm-‐3 to 1019cm-‐3, indicated by the directions of the arrows. Since Fermi-‐level is pinned at the valence band at the surface, there will be a depletion region for electrons. By a simple analysis, if the depletion width exceeds that of the channel thickness, all the electrons are depleted as a result. To get around this, one solution is to add another top buffer layer above the channel, so that it 77 confines the depletion region in the top buffer layer. In other words, the band bending in the top layer will allow the relative position of the Fermi-‐level with respect to the channel material to go further into the conduction band, thus helping the population of electrons. Fig. 3.28 shows the simulation results for the modified buried-‐channel device, where 10nm In0.2Al0.8Sb top buffer layer is added to shield away the surface pinning effect. 2x1012cm-‐2 modulation doping was added in both the top and bottom barrier layers. Activation energy of 0.1eV is set to the dopants to simulate the dopant activation of Te in antimonide. Figure 3.28 Band diagrams (blue: conduction band, light green: heavy hole band, dark green: light hole band) and electron concentration (purple: L-‐valley electrons, red: Γ-‐valley electrons) of the buried channel device with 10nm InAlSb top barrier layer, 10nm InGaSb as the channel and AlGaSb as the buffer layer. The surface is terminated with 1nm GaSb and the Fermi-‐level is pinned at 0.1eV from the valence band edge of GaSb. 2x1012cm-‐2 modulation-‐doping layers are included in both top and bottom barrier layers. 78 The problem with the buried-‐channel approach is now top buffer layer presents a barrier for carriers to tunnel through in order to reach to the channel, especially for electrons. Therefore, alloy contacts have to be used in the source/drain, where annealing causes the reaction of contact metal with antimonide to form metal alloy. As a result, the whole top barrier layer is consumed by the reaction and alloyed contact reach the channel. The schematic of the structure is shown in Fig. 3.29. Figure 3.29 Schematic of the structure of the buried channel devices. 3nm and 10nm AlInSb top barrier layer were used for PMOS and NMOS respectively. To optimize the electrical contact with alloyed metal scheme, we used n-‐type bulk GaSb of electron concentration of ~1017cm-‐3. The I-‐V characteristics are shown in Fig. 3.30. Au/Ge/Ni/Au scheme is chosen for n-‐type contact. The theory behind the alloy contact is complicated, especially with multiple metals involved, since it leads to complex phases of the metal alloys. Au and Ni form alloy with antimonide upon annealing. Ge diffuses into the semiconductor and typically serves as donors. It is found the current density of Au/Ni/Ge/Au contact with n-‐GaSb consistently increases with increase in annealing temperature and duration, while the surface morphology of the contact degrades accompanied with lateral diffusion of the metal alloy. Pd-‐based alloy contact, on the other hand, shows lower current than Au-‐based 79 contact, possibly because the absence of dopant species, even though Pd forms alloy with antimonide at a lower temperature. Figure 3.30 I-‐V characteristics of Au-‐ and Pd-‐based alloy contact with n-‐GaSb with different annealing conditions. Current density increases consistently with higher annealing temperature and duration. Auger Electron Spectroscopy (AES) is used to study the depth profile of the alloy contact to make sure the metal alloy diffuses through the top barrier layer as shown in Fig. 3.31. 40nm Au/ 12nm Ge/ 12nm Ni/ 700nm Au metal contact is deposited on the heterostructure stack for buried-‐channel devices and then annealed at 300°C for 5mins. It is found that there is a clear sign of the intermixing of antimonide with the metal. Antimony atoms have a tendency to diffuse toward the surface. Even though higher annealing temperature leads to further increase in current density, it also leads to excessive lateral diffusion of the contact. Therefore, final condition for annealing of Au-‐based alloy contact is set at 300°C for 5mins. Alloy scheme for p-‐ type contact is similar to n-‐type, except Pd-‐based alloy contact is used. 80 Intensity (a. u.) Ni Ge Au Sb 0 2 4 6 8 10 Sputtering time (mins) 12 14 Figure 3.31 AES depth profile of Au/Ni/Ge/Au alloy contact on the heterostructure for buried-‐channel devices. Finally, both p-‐ and n-‐channel MOSFETs were fabricated with the same heterostructure design except for the channel p-‐ or n-‐doped respectively. After the ALD deposition of Al2O3 as the high-‐k dielectric, aluminum was deposited using e-‐ beam evaporation and patterned to form gate electrode. The interface quality was further improved by forming-‐gas anneal at 350°C for 30mins. Pd/Pt/Au and Au/Ni/Ge/Au metal stacks were deposited and then alloyed to form an embedded direct contact to the p-‐ and n-‐channel quantum well (QW) respectively. Alloyed contact to p-‐type channel was established during the forming-‐gas anneal at 350°C. The annealing condition for n-‐type contact was optimized to be at 300°C in a nitrogen ambient. Transfer characteristics of the fabricated MOSFETs are shown in Fig. 3.32. Both PMOS and NMOS demonstrate decent switching behavior; on/off ratio up to 104 and 3x102 was observed for PMOS and NMOS respectively. Output characteristics (Fig. 3.33) show on-‐current of 5μA/μm, 3.8μA/μm at LG=50μm for PMOS and NMOS respectively. The NMOS performance is limited by contact and 81 series resistance, which leaves room for further improvement, and would be essential if LG were to be scaled down. Figure 3.32 Transfer characteristics of (a) PMOS and (b) NMOS. On/off ratio up to 104 and 3x102 can be obtained for PMOS and NMOS respectively. NMOS current scales non-‐linearly with VDS due to high contact resistance. Figure 3.33 Output characteristics of (a) PMOS and (b) NMOS. Characteristics can be further improved by reduction of contact and series resistance. 82 This is, to our best knowledge, the first demonstration of a high mobility NMOS and PMOS in the same channel material with comparable ION, (Table.1) which makes InGaSb an attractive prospect for realizing complementary logic in III-‐Vs. Table 1: Comparison of on-‐state current and mobility for different candidate of CMOS technology Ion (μA/μm) p n This work ~4 ~3.8 LG=50μm InGaSb InGaSb Ref. [16] ~2.4 ~8 LG=50μm Ge InGaAs Ref. [30] ~110 ~450 LG=1.5μm Ge InGaAs N/P μ at 1012cm-‐2 (cm2/V/s) p n Gated Hall 0.9 900 4000 3.3 260 1800 4.1 400 1300 Summary In Summary, in this section, we discussed the heterostructure design of 6.1-‐6.2Å lattice system to support InGaSb as the single-‐channel material for III-‐V CMOS. It is shown that AlGaSb/InGaSb provides favorable band alignment that give good confinement of both electrons and holes. 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Radosavljevic, T. Ashley, A. Andreev, S. D. Coomber, G. Dewey, M. T. Emeny, M. Fearn et al. "High-‐performance 40nm gate length InSb p-‐channel compressively strained quantum well field effect transistors for low-‐power (VCC= 0.5 V) logic applications." In Proc. IEDM 2008, Dec. 2008. [22] L. Desplanque, D. Vignaud, S. Godey, S. Plissard, X. Wallart, P. Liu and H. Sellier, "Electronic properties of the high electron mobility Al0.56In0.44Sb/Ga0.5In0.5Sb heterostructure," J. Appl. Phys., vol. 108, no. 4, 043704, Aug. 2010. [23] R. Loesch, R. Aldam, L. Kirste and A. Leuther, "Molecular beam epitaxial growth of metamorphic AlInSb/GaInSb high-‐electron-‐mobility-‐transistor structures on GaAs substrates for low power and high frequency applications," J. Appl. Phys., vol. 109, no. 3, 033706, Feb. 2011. [24] B. R. Bennett, M. G. Ancona, J. B. Boos and B. V. Shananbrook, "Mobility enhancement in strained p-‐InGaSb quantum wells," Appl. Phys. Lett., vol. 91, no. 4. 042104, Jul. 2007. [25] C. Merckling, X. Sun, A. Alian, G. Brammertz, V. V. Afanasev, T. Y. Hoffmann, M. Heyns, M. Caymax and J. Dekoster, "GaSb molecular beam epitaxial growth on p-‐ InP(001) and passivation with in situ deposited Al2O3 gate oxide," J. Appl. Phys., vol.109, no.7, 073719, Apr 2011. [26] B. R. Bennett, M. G. Ancona, J. G. Champlain, N. A. Papanicolaou, and J. B. Boos, "Demonstration of high-‐mobility electron and hole transport in a single InGaSb well for complementary circuits," J. Cryst. Growth, vol. 312, no. 1, pp. 37, 2009. 88 [27] Z. Yuan, A. Nainani, X. Guan, H.-‐S. P. Wong and K. C. Saraswat, "Tight-‐binding study of Γ-‐L bandstructure engineering for ballistic III–V nMOSFETs," in Proc. SISPAD 2011, pp.71-‐74, Sept. 2011. [28] A. Nainani, Y. Sun, T. Irisawa, Z. Yuan, M. Kobayashi, P. Pianetta, B. R. Bennett, J. B. Brad and K. C. Saraswat, "Device quality Sb-‐based compound semiconductor surface: A comparative study of chemical cleaning," Journal of Applied Physics, vol.109, no.11, p.114908, Jun 2011. [29] Z. Yuan, A. Nainani, J. Lin, B. R. Bennett, J. B. Boos, M. G. Ancona and K. C. Saraswat, "Fermi-‐level pinning at metal/antimonides interface and demonstration of antimonides-‐based metal S/D Schottky pMOSFETs," in Proc. DRC 2011, pp.143-‐ 144, June 2011. [30] D. Lin, et al., “Enabling the high-‐performance InGaAs/Ge CMOS: a common gate stack solution,” in Proc. IEDM 2009, pp. 327-‐330, Dec. 2009. CHAPTER 4: SOURCE/DRAIN TECHNOLOGY IN ANTIMONIDE-‐BASED MOSFETS As shown in previous chapter, the Fermi-‐level is pinned near the valence band edge of GaSb at metal/GaSb interface, which is favorable for achieving low resistance source/drain in p-‐channel devices, however, puts challenge on contact resistance in n-‐channel MOSFETs. In this chapter, the source/drain technology in anitmonide-‐based MOSFETs is discussed, particularly to address the approach for achieving low-‐resistance source/drain in pMOSFETs and low contact resistance in nMOSFETs. In the first part, we study the formation and electrical properties of Ni-‐GaSb alloys by direct reaction of Ni with GaSb. It is found that several properties of Ni-‐ antimonide alloys, including low thermal budget processing (300°C), the high electron Schottky barrier height (SBH) for Ni-‐GaSb/n-‐GaSb contact (0.58 eV), low sheet resistance of Ni-‐InGaSb (53 Ω/☐) and low specific contact resistivity (7.6×10-‐ 7 Ωcm2), make it a very attractive source/drain material in antimonide-‐based p-‐ channel metal source/drain metal-‐oxide-‐semiconductor field-‐effect transistors (MOSFETs). Devices with a self-‐aligned metal S/D process were demonstrated, in which heterostructure design is adopted to further improve the device performance, e.g. on/off ratio (>104), subthreshold swing (140 mV/dec). High effective-‐field hole mobility of ~510 cm2/Vs at sheet charge density of 2×1012 cm-‐2 has been extracted. Fermi level pinning near GaSb valence band edge leads to high Schottky barrier height for metal/ntype GaSb contacts. However, this effect can be alleviated by depinning of the Fermi level with the introduction of thin interfacial dielectric. The second part of the chapter shows that the use of TiO2 allows depinning of the Fermi level without introducing excessive tunneling resistance due to the low conduction 90 band offset, estimated by Synchrotron Radiation Photoemission Spectroscopy (SRPES). It is shown the insertion of TiO2 results in reduction of Schottky barrier height and greater than four orders of magnitude increase in current density for metal contacts on n-‐type GaSb. 4.1 ANTIMONIDE-‐BASED P-‐CHANNEL MOSFETS WITH SELF-‐ALIGNED NI-‐ALLOY METAL SOURCE/DRAIN Antimonide based compound semiconductors have attracted extensive interest for replacement of silicon in future high-‐performance, low-‐power complementary metal-‐oxide-‐semiconductor (CMOS) technologies, due to their superior electron and hole transport properties [1,2]. Although many works have focused on III-‐V n-‐ channel MOSFETs [3,4], performance of III-‐V p-‐MOSFETs traditionally lagged behind. Recently, high-‐performance p-‐channel devices have been demonstrated using antimonide-‐based channel materials [5-‐7]. Peak hole mobility above 900 cm2/Vs can be obtained with strained InGaSb p-‐channel MOSFETs [6,7]. This demonstrates the potential of antimonide compound semiconductors for III-‐V CMOS electronics. One of the main obstacles to achieving high-‐performance III-‐V MOSFETs is the high-‐resistance source and drain (S/D) contacts. Additionally, the poor thermal stability of oxide/GaSb interfaces and poor recovery of crystalline quality after ion implantation makes the S/D formation process with low thermal budget difficult [8]. Metal alloy with III-‐V compound semiconductors, which enables self-‐aligned metal S/D formation process, has been demonstrated recently [9,10]. Initial study on the formation of Ni-‐GaSb [11] suggests that the selective etching between the metal Ni and Ni-‐GaSb could potentially enable a self-‐aligned metal S/D process for antimonide-‐based p-‐MOSFETs. 91 We first study the formation and electrical properties of Ni-‐GaSb alloy by direct reaction of Ni with GaSb. A self-‐aligned, antimonide p-‐channel MOSFET process with Ni-‐alloy as source/drain is described. The fabricated device shows excellent characteristics. High hole mobility of 510 cm2/Vs at sheet charge density of 2×1012 cm-‐2 is achieved with a strained InGaSb channel. Figure 4.1 XRD analysis of 10nm Ni on GaSb with and without RTA at 300°C for 3mins. After degreasing in solvent and cleaning with diluted HCl (1:1), 10nm Ni was deposited on bulk CZ-‐grown GaSb by e-‐beam evaporation, followed by rapid thermal annealing (RTA) at 300°C for 3mins. X-‐ray diffraction (XRD) analysis was used to confirm the formation of Ni-‐GaSb alloys under such conditions. Fig. 4.1 shows the results of XRD analysis. The annealed sample shows several peaks, which could be attributed to a mixture of binary and ternary phases of Ni-‐GaSb alloys [11], while those peaks are absent in the case of the control sample. 92 Figure 4.2 Cross-‐sectional TEM image of Pt/Ni-‐GaSb/GaSb, diffraction pattern indicates poly-‐crystallinity of Ni-‐GaSb. To further confirm the existence of Ni-‐GaSb alloys and the selective etching of Ni, the sample was subject to HCl:H2O (1:5) wet etching to remove unreacted Ni. Pt was then deposited during the sample preparation for transmission electron microscopy (TEM) using a focused ion beam (FIB) system. Fig. 4.2 shows the cross-‐sectional TEM image of the Pt/Ni-‐GaSb/GaSb structure. Ni-‐GaSb alloy can be clearly identified; the layer thickness is approximately 6 nm. In order to achieve high ION and low IOFF at the same time in a metal S/D p-‐ channel MOSFET, a low Schottky barrier height (SBH) for holes and high SBH for electrons is desired. It is known that the charge neutrality level of GaSb aligns close to the valence band edge of GaSb [8], and exhibits severe Fermi-‐level pinning. Therefore, Schottky diodes with different contact metals were fabricated to study the SBH of Ni-‐GaSb on bulk n-‐GaSb with carrier concentration of ~5×1017 cm-‐3. Mesa structures were built by wet-‐etching of GaSb with HCl:H2O:H2O2 (50:150:1), and the 93 surfaces were passivated with Al2O3 deposited by atomic layer deposition (ALD). Different contact metals (Ti, Ni) were deposited by e-‐beam evaporation. To study the Schottky diode between Ni-‐GaSb/n-‐GaSb, RTA was performed on the sample with Ni at 300°C for 3 mins, so that the Ni-‐GaSb was formed at the metal/GaSb interface. Finally, Au was deposited on the back of the samples to serve as back contact. Figure 4.3 I-‐V characteristics of Schottky diodes with different contact metals on n-‐ GaSb. Metal/n-‐GaSb showed very similar Schottky behavior for all the cases in Fig. 4.3, indicating high SBH for electrons. The SBH, extracted from temperature-‐dependent I-‐V characteristics, was 0.58±0.06 eV, in agreement with previous report of SBH for different contact metals [11]. The SBH for holes can thus be estimated to be ~0.1 eV. Such band alignment makes it favorable for making high ION/IOFF in p-‐channel MOSFETs with Ni-‐GaSb alloy as S/D materials. 94 Achieving a contact with low sheet-‐resistance and low contact resistivity is essential in order to further scale the channel length of antimonide-‐based p-‐channel MOSFETs. N-‐type bulk GaSb samples were used to confine the conduction in the Ni-‐ GaSb layers. After the blanket formation of Ni-‐GaSb and selective etching of the un-‐ reacted Ni with diluted HCl, a transfer-‐length method (TLM) test structure was deposited using lift-‐off of Pt as the contact metals. The same structure was built on a heterostructure sample grown by molecular beam epitaxy [6], which consists of 7nm undoped In0.2Ga0.8Sb / 1μm Al0.8Ga0.2Sb wide-‐bandgap buffer layer on semi-‐ insulating GaAs substrate. The same sample was used for transistor fabrication. Figure 4.4 Schematic of structure for TLM and TLM plots of Pt contact to low-‐sheet-‐ resistance Ni-‐antimonide alloys. Fig. 4.4 shows the schematic of TLM structure and measurement results. Table 2 shows the summary of the sheet resistance (Rsheet) and specific contact resistivity (ρc), comparing Ni-‐antimonide alloys and S/D formed by ion implantation of Be [8]. It is shown that with even lower thermal budget (~300°C), Ni-‐GaSb shows more than 7 times reduction in Rsheet (87Ω/☐) and reduced ρc (3.3×10-‐6Ωcm2), as compared to results from ion-‐implantation. Further reduction in resistance was 95 observed in the heterostructure sample, which shows Rsheet of 53Ω/☐ and reduced ρc of 7.6×10-‐7 Ωcm2, respectively. Given that the conducting layer of InGaSb was undoped, the low Rsheet and ρc could be mainly attributed to the charge-‐neutrality level being close to the valence band edge. It proves the potential of such alloy materials as the S/D materials to give even lower resistance with doping. Table 2: Comparison of Electrical Properties between Ni-‐antimonide alloys and ion implanted GaSb P+ S/D by ion-‐ S/D materials implantation Ni-‐GaSb Ni-‐InGaSb Thermal budget 350°C 30mins 300°C 3mins 300°C 3mins Junction depth >200nm ~6nm ~7nm Rsheet (Ω/☐) 560 87 53 8.7×10-‐6 3.3×10-‐6 7.6×10-‐7 ρc (Ωcm2) P-‐channel MOSFETs with self-‐aligned Ni-‐alloy as S/D were fabricated on both a bulk n-‐GaSb substrate and a heterostructure stack with 7nm undoped In0.2Ga0.8Sb as the channel, following similar process as described in [10]. After surface clean, ~8 nm Al2O3 was deposited as the gate dielectric by ALD [8]. 30 nm of W was then sputtered, followed by a 350°C anneal for 1min in N2/H2 (95%/5%) ambient to improve the quality of the gate dielectric and recover the plasma damage. Gate electrodes were patterned using contact lithography, followed by e-‐beam evaporation of 7nm Ni. Source/drain metal pads were deposited by lift-‐off of 70nm of Pt. RTA was performed at 300°C for 3mins, followed by etching of unreacted Ni by HCl. 96 Figure 4.5 Transfer characteristics of devices (LG~5μm) on bulk GaSb substrate and heterostructure stack. Higher on-‐current and lower off-‐current were achieved with the heterostructure design. Fig. 4.5 shows the transfer characteristics of devices (LG~5μm) on both the bulk n-‐GaSb substrate and the heterostructure sample. On the bulk substrate, the ION/IOFF ratio (~50), as well as subthreshold swing (~250 mV/dec) of the devices, are largely limited by the ION/IOFF of the Ni-‐GaSb/GaSb Schottky diode. It is shown that the leakage current is greatly reduced by having a wide-‐bandgap buffer layer (Al0.8Ga0.2Sb) beneath the channel. A high ION/IOFF of >104 and subthreshold swing of 140mV/dec are achieved with the heterostructure design. The on-‐state current for the heterostructure design is also higher than that for bulk GaSb design due to the presence of ~0.7% biaxial compressive strain and confinement of carriers in the channel [6]. Drain current density scales with 1/LG with channel length ranging from 100μm to 5μm, indicating low external resistance for the set of devices. Extraction of external resistance is difficult, considering the channel lengths are comparatively 97 large, thus might result in relative large error in the calculated value using extrapolation. Figs. 4.6 and 4.7 show the transfer and output characteristics of the devices (LG~5μm) with heterostructure design, which shows a peak transconductance of 29 μS/μm at VDS=1V and a decent ION of 42 μA/μm. Further improvement would be possible with the scaling of the gate dielectric thickness. Fig. 4.8 plots the mobility extracted using split-‐CV analysis and benchmarks it against the mobility in unstrained silicon and strained GeSn p-‐channel MOSFETs with a metallic S/D [12]. In the unstrained case, bulk GaSb gives a mobility up to 2 times higher than that of silicon. Because of the 0.7% biaxial strain, the hole mobility is further improved by 2 times in the heterostructure devices. For antimonide devices, mobility enhancement drops at high sheet charge density due to the spill-‐over of charge into low-‐mobility buffer layer and surface roughness scattering [6]. Figure 4.6 Transfer characteristics of the devices with heterostructure design and Nialloy as metal S/D. 98 Figure 4.7 Output characteristics of the devices with heterostructure design and Ni-alloy as metal S/D. Figure 4.8 a) The gate to channel capacitance (CGC) measured at 100kHz. b) Extracted effective-‐field mobility using split-‐CV analysis and benchmark against silicon and strained GeSn. 99 Studies on the formation and electrical properties of Ni-‐antimonide formed by direct reaction of Ni with antimonide compound demonstrate the Ni-‐antimonide alloy is a suitable source/drain material in metal source/drain antimonide-‐based p-‐ MOSFETs. A self-‐aligned process for metal S/D MOSFETs using an epitaxial heterostructure with high hole mobility was developed and demonstrates the potential of such source/drain design in further channel length scaling of III-‐V p-‐ channel MOSFETs. 4.2 SCHOTTKY BARRIER HEIGHT REDUCTION FOR METAL/N-‐GASB CONTACT BY INSERTING TIO2 INTERFACIAL LAYER WITH LOW TUNNELING RESISTANCE Antimonide-‐based III-‐V compound materials have great potential for applications ranging from next generation complementary metal oxide semiconductor devices to optoelectronics [13-‐15]. Among the potential candidates for replacing silicon as channel materials, InSb has theoretically and experimentally demonstrated high electron mobility [13] and InGaSb shows promising hole mobility [14]. Band alignments of relevant ternaries and quaternaries are suitable for optoelectronic devices, e.g. infrared wavelength photo-‐detectors [15]. GaSb emerges as one of the crucial materials for 6.1Å lattice system based electronic devices, which has a bandgap of 0.7eV at room temperature, suitable for use in fiber optic communications systems. For high performance devices in these applications, Ohmic contact with low contact-‐resistivity is required. However, metal/GaSb interface exhibits Fermi level pinning near the valence band of GaSb [13,15] which makes low resistance Ohmic contact formation on n-‐type GaSb difficult. For example to get low resistance contacts to Sb-‐based HEMTs, alloyed contacts with large contact area and large source-‐drain separation to prevent shorting by metal diffusion are employed presently [16-‐18]. Furthermore, poor n-‐type dopant activation in GaSb limits the tunneling current through the Schottky barrier [15]. 100 Therefore, tuning of the electron Schottky barrier height (ΦBN) to make non-‐alloyed Ohmic contact on lightly doped n-‐type GaSb remains a challenge. Figure 4.9 Band diagrams of depinning effects (a) by MIGS theory, (b) by interface dipole theory and (c) with low CBO dielectric. In the case of (a) and (b), dielectrics with high CBO introduce high tunneling resistance, while in (c) low Schottky barrier is achieved with low tunneling resistance due to low CBO. Large ΦBN can be attributed to Fermi level pinning at metal/n-‐GaSb interface near the charge neutrality level (ECNL) of the semiconductor, which is found to be near the valence band for GaSb [19]. By inserting a dielectric between metal and semiconductor, Fermi level pinning at metal/semiconductor interface can be 101 alleviated [20]. This depinning effect has been explained by metal-‐induced gap states (MIGS) [21-‐22] (Fig. 4.9(a)) and interfacial dipole effect [23] (Fig. 4.9(b)). By the MIGS theory, inserting a thin insulator attenuates the metal electron wavefunction in the insulator prior to penetrating the semiconductor, resulting in fewer charges to drive the Fermi level towards ECNL. In accordance with interface dipole theory, by inserting thin dielectrics, electronic dielectric dipole is introduced between the insulator and semiconductor native oxide, which leads to a barrier shift. Connelly et al. demonstrated reduction in ΦBN to Si by inserting SiNX between metal and Si [20]. Other high-‐k dielectrics have also been adopted to tune the effective barrier height (ΦBNeff) of contacts to Si [24], InGaAs/GaAs [25], as well as to n-‐type germanium [26]. While the depinning effect is beneficial for reducing Schottky barrier height, the tunneling barrier introduced by the dielectric layer leads to additional tunneling resistance, thereby increasing the specific contact resistivity [20,24-‐26]. For dielectrics such as Al2O3, high tunneling resistance limits the current level with increase in the thickness of the dielectric (Fig. 4.9(a), (b)). The optimal thickness for contact resistivity is below 2nm [24-‐25]. Recently, modeling work suggested using dielectrics with very low conduction band offset (CBO), such as TiO2, to provide low contact resistivity to n-‐Ge [27], which has similar band lineup as GaSb and also shows Fermi level pinning at valence band edge. This allows depinning of the Fermi level without introduction of tunneling resistance (Fig. 4.9(c)). In this study, we demonstrate band engineering to tune ΦBN without adding tunneling resistance and achieve increase in current densities for metal/n-‐GaSb contact by insertion of TiO2. Al/TiO2/n-‐GaSb Schottky diodes with different thicknesses of TiO2 were fabricated to study the change in ΦBN. Obtained J-‐V characteristics are compared with control samples with Al2O3 interfacial layers, for which the current is limited by tunneling resistance. Aluminum (Al) is chosen 102 because of its low workfunction (4.06-‐4.26eV [28]) to better study the Fermi level movement towards the conduction band of GaSb (electron affinity: 4.06eV [15]). The band offsets of TiO2/GaSb and Al2O3/GaSb are determined using Synchrotron Radiation Photoemission Spectroscopy (SRPES). The Te-‐doped bulk n-‐GaSb substrates grown by the Czochralski (CZ) technique were chosen to be lightly doped with carrier concentration of ~1017cm-‐3 to put more emphasis on thermionic injection over thermionic field emission and field-‐emission current. First, samples were degreased in solvents. Surface cleaning was done by 15% HCl to remove native oxide, directly followed by atomic layer deposition (ALD) of TiO2 using tetrakis(dimethylamido)titanium (TDMAT) and H2O precursors at 200°C. Control samples of Al2O3 were deposited by ALD at 300°C using trimethylaluminum (TMA) and H2O as precursors. Al was deposited by e-‐beam evaporation and patterned as top contact. Backside contact was formed using blanket evaporation of Al. SRPES is used for the determination of band offsets of TiO2 and Al2O3 with GaSb [29-‐30]. The SRPES experiments were performed at beamline 8-‐1 of Stanford Synchrotron Radiation Lightsource, which provides a tunable range of monochromatic photons up to 160eV, yielding high surface sensitivity with a minimum electron escape depth around 5 Å. The Ga 3d, Al 2p, Ti 3p and the valence-‐band (VB) spectra can be studied with high accuracy in this low energy range. By studying the emission from valence electrons, the valence band offset (VBO) of TiO2 and Al2O3 relative to GaSb can be determined by comparing the VB spectra after surface cleaning and after deposition of thin TiO2/Al2O3, while using the Ga 3d peak from the substrate for alignment (Fig. 4.10(a), (b)). The VBO of TiO2 and Al2O3 on GaSb were measured to be 2.6eV and 3.0eV respectively. The ALD Al2O3 bandgap was found to be 6.1eV as determined from the energy loss spectrum of the Al 2p peak shown in Fig. 4.10(c). Due to the low bandgap value of TiO2, estimation of bandgap from energy loss of Ti 3p peak is difficult. The bandgap of TiO2 and GaSb are assumed to be within the range of 3.3-‐3.5eV [31] and 0.7eV [15] 103 respectively. CBO can then be calculated by subtracting the bandgap of GaSb and VBO from the bandgap for both TiO2 and Al2O3. The CBO was thus calculated to be 2.4eV for Al2O3 on GaSb and between 0-‐0.2eV for TiO2 on GaSb. Values of band offsets are summarized in Fig. 4.10(d). Figure 4.10 SRPES spectra for (a) TiO2 and GaSb valence bands, (b) Al2O3 and GaSb valence bands, and (c) Al 2p peak from Al2O3. (d) Summary of band offsets information for Al2O3 and TiO2 with GaSb. The TiO2/GaSb and Al2O3/GaSb valence band offsets were measured to be 2.6eV and 3.0eV, respectively. The energy loss spectrum of the Al 2p peak indicates the bandgap of 6.1eV for Al2O3. Photon energy used for valence band and Al 2p were 120eV and 160eV respectively. 104 Figure 4.11 J-‐V characteristics of Al/n-‐GaSb Schottky diode with interfacial layer of (a) TiO2 and (b) Al2O3. (a) The current density increases with increase in TiO2 thickness even up to 7.5nm. Contact characteristic changes from rectifying to quasi-‐ ohmic. (b) With Al2O3, the current level increases slightly initially and drops significantly for thickness larger than 1nm. The left inset of (a) shows J-‐V characteristics of TiO2 devices for bias voltage from -‐1V to 1V, the rectifying behavior for Al/n-‐GaSb is clearly visible. The right inset of (a) shows temperature-‐ dependent J-‐V measurements for 2nm and 9.5nm TiO2 devices, which show effective electron barrier heights of 0.14eV and 0.07eV respectively. 105 It has been shown, due to the Fermi-‐level pinning effect, Al/n-‐GaSb Schottky diodes without the interfacial dielectric layer exhibit rectifying behavior [32-‐33]. ΦBN for Al/n-‐GaSb is measured to be 0.56-‐0.57eV [32], meaning the Fermi level is pinned towards the GaSb valence band edge at Al/GaSb interface. Fig. 4.11(a), (b) show the room temperature J-‐V characteristics of the GaSb Schottky diodes for different thicknesses of the TiO2 and Al2O3 interfacial layer. Rectifying behavior for Al/n-‐GaSb is clearly visible on the scale plotted in Fig. 4.12(a):left inset. With increasing thicknesses of TiO2, increase in current density was observed for n-‐GaSb diodes. This trend of increase in current only saturates when the thickness of TiO2 reaches 7.5nm, indicating tunneling barrier is not a critical factor limiting electron transport. The J-‐V characteristics change from rectifying to quasi-‐Ohmic for n-‐type GaSb diodes, indicating a significant reduction in ΦBN. Meanwhile, the increase in current is only observed for ultra-‐thin Al2O3 layer below 1nm (Fig. 4.11(b)), since the tunneling resistance largely limits the current for thicker Al2O3. The current density for the metal/semiconductor contact structure consists of the current emission over the Schottky barrier (thermionic emission) and the current emission through the Schottky barrier (thermionic field emission and field emission current) [34]. Meanwhile for the metal/dielectric/semiconductor system it is limited by transport through the barrier of the dielectric layer [20,24-‐ 26]. The modeling of current characteristic through this system is a challenging exercise and there have been some recent papers using Tsu–Esaki model [27] and non-‐equilibrium green function [25] to model this system. In the absence of a model that can accurately captures these different components and tunneling currents, we adopt the thermionic emission model to estimate the reduction in ΦBN with TiO2 insertion through temperature dependent measurements from 77K to 300K [25-‐ 26]. The effective Schottky barrier height can be extracted by Richardson plot [25-‐ 106 26,35], in which the slope corresponds to -‐qΦBNeff /kB, where q and kB correspond to electronic charge and Boltzmann constant (Fig. 4.11(a):right inset). ΦBNeff extracted is not exact due to the presence of dielectric between the metal and semiconductor, but rather it is a representative of the electrical behavior. By insertion of TiO2 layer, the effective Schottky barrier height ΦBNeff decreases to 0.14eV and 0.07eV for 2nm and 9.5nm TiO2 respectively. Increase in dielectric thickness leads to lower extracted ΦBNeff. Modulation of diode current and the decreasing trend in extracted barrier height from thermionic emission model verify that the interfacial TiO2 layer reduces Schottky barrier height. Fig. 4.12 plots the current density levels at -‐0.1V for the TiO2 and Al2O3 diodes as a function of dielectric thickness. For Al2O3, the depinning effect leads to the initial increase in current density. However, high CBO with GaSb (2.4eV) limits the electron transport as the thickness of Al2O3 increases, adding substantial tunneling resistance to the contact. The optimal thickness for larger current density has to be kept ultra-‐thin (~1nm). Meanwhile, electron transport by tunneling through the dielectric has an exponential dependence on the thickness of the barrier; therefore the current density is sensitive to the dielectric thickness. This puts challenge to achieve uniform sub-‐nanometer deposition of the dielectrics on wafer scale in order to achieve high current density for contacts using high CBO dielectrics, such as Al2O3. For TiO2, due to the near zero CBO of TiO2 with GaSb (0-‐0.2eV), no excessive tunneling resistance is introduced by increasing TiO2thickness up to 7.5nm, while the depinning effect increases current density. As shown in Fig. 4.12, the current density increases consistently with increase in TiO2 thickness and remains fairly constant over a large range of dielectric thickness. This proves the use of thicker dielectric without excessive tunnel resistance such as TiO2 is advantageous. 107 Figure 4.12 Normalized current density of Al/n-‐GaSb Schottky diode with interfacial layer of TiO2 and Al2O3 of different thicknesses biased at -‐0.1V. TiO2 diodes show a substantial increase in current from reduction in ΦBN. Increase in current density with thickness is maintained up to 9.5nm. For Al2O3, after the initial increase, tunneling resistance reduces current density. Current levels are sensitive to the thickness of Al2O3. In conclusion, we have demonstrated band-‐engineering of Fermi level depinning for metal/n-‐GaSb contact with insertion TiO2 interfacial layer. The low CBO leads to reduction in Schottky barrier height without introduction of excessive tunneling resistance. The contact characteristics change from rectifying to quasi-‐Ohmic and more than four orders of magnitude improvement in current density is achieved. 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Monch, Electronic properties of semiconductor interfaces, Springer, New York, 2004 CHAPTER 5: HETERO-‐INTEGRATION OF III-‐V COMPOUND MATERIALS ON SILICON USING RAPID-‐MELT-‐GROWTH The integration of III-‐V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-‐mismatch between III-‐Vs and silicon [1]. Different requirements of n-‐ and p-‐channel devices pose a challenge to the co-‐integration of more than one type of material on a silicon platform. In this section, the co-‐ integration of InAs-‐OI NMOS and GaSb-‐OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-‐lineup. Such hetero-‐integration is demonstrated on silicon substrate using rapid-‐melt-‐growth technique. 5.1 INTRODUCTION TO RAPID-‐MELT-‐GROWTH As the research community demonstrates the huge potential of high-‐mobility alternative channel materials for future high-‐performance, low-‐power logic applications, one technological challenge remains, which is the monolithic integration of III-‐V compound semiconductors on a silicon substrate. There are two conventional methods for integrating high quality single crystal on top of a silicon substrate: wafer bonding and epitaxial growth. There are many techniques for wafer bonding. These approaches are usually material-‐specific, meaning that the process conditions such as the control of temperature and pressure might differ for different materials [1,2]. In recent years, patterned layer transfer technique has been developed for a variety of material systems [3,4]. However, the approach cannot be easily scaled to be compatible with state-‐of-‐art 300mm manufacturing. Compared 115 with wafer bonding which requires two separate wafers, epitaxial growth usually refers to growing a high quality single crystal layer on a single wafer. Generally, a relatively thick layer is required to relax the lattice mismatch, followed by several medium to high temperature annealing cycles to further reduce the density of defects in the epitaxial layer. The growth of more-‐than 1μm-‐thick buffer layer makes this approach less favorable for production [5]. Optimization of the buffer layer is the key to epitaxial growth and the process is usually material-‐specific, making the integration of more than one type of material difficult. Besides direct, large-‐area epitaxial growth, there are other approaches to reduce the buffer layer thickness required to relax the lattice mismatch. For instance, attempts have been made to develop universal buffer layer to support the growth of the active device layer on top [6]. Another promising method is called aspect ratio trapping. This technique uses high aspect ratio sub-‐micron trenches to trap threading dislocations and reduce the dislocation density of the lattice-‐mismatched material grown on silicon [7]. The problem with this approach is the incapability of the control over defect propagation along the trench direction [8]. Rapid-‐Melt-‐Growth (RMG) was first developed and introduced in 2004 [9,10] for growing single crystal germanium thin films on an amorphous dielectric layer. On a silicon bulk substrate, amorphous dielectric layer, e.g. SiOx, SiNx, is first deposited as an isolation layer. Small seeding windows are patterned to expose the underlying single crystal silicon substrate to serve as the crystalline template. Amorphous or polycrystalline germanium is deposited uniformly across the wafer and patterned into stripes with only one end touching silicon in the seed region. The whole structure is then covered with an oxide layer acting as a micro-‐crucible to hold the germanium stripe during melting. Typical dielectric materials have melt temperature higher than that of silicon and can maintain the structural integrity. Finally, the whole structure is heated up above the melting point of germanium by 116 rapid thermal annealing (RTA) for a short period of time, and then cooled down. Since the stripe is thermally isolated, heat can only be dissipated through the silicon seed. As a result, during the cooling process, liquid germanium solidifies from the seed region; hetero-‐epitaxial growth starts from the crystalline silicon seed, and then propagates to the other end of the stripe. The same principle has been applied to III-‐V materials. A typical structure is shown in Fig. 5.1. One of the advantages of this approach is the use of the necking mechanism to control the propagation of the defects generated due to the lattice mismatch between Ge/III-‐Vs and silicon seed, thereby, confining the defects to the neck region. Ge / Ge / Figure 5.1 Top-‐view illustration of the structure for germanium/III-‐V RMG process (left). Cross-‐sectional view of the structure, which is typically used for TEM study of material properties of the stripe (right). Despite a variety of experiments showing the robustness of the approach, an accurate estimation of the defect density of the stripe after RMG is still problematic. However, large area growth of single crystalline material is difficult with this 117 method. Therefore, some conventional methods, e.g. XRD, plan-‐view TEM, cannot be easily adopted to characterize the film quality after RMG. An attempt has been made to quantify the defect density by aggregating the data from cross-‐sectional TEM of a number of stripes. The defect density after RMG can be estimated to be ~ 106cm-‐2 [10], which meets the requirement of high-‐performance logic and memory devices. This demonstrates the potential of achieving low point defect density with RMG approach. The high crystalline quality of the recrystallized stripes was also confirmed by electrical measurements. High-‐performance gate all around (GAA) germanium PMOS transistors were fabricated showing steep subthreshold slope ~ 71 mV/dec and 40% higher hole mobility than silicon as in [11]. In 2010, Chen, et al., adopted the same method for III-‐V compound materials for their hetero-‐integration on silicon [12]. The transformation of amorphous to single crystal for both GaAs and GaSb on bulk Si substrates was demonstrated. Similar to the case of germanium, high-‐resolution TEM image and selective area diffraction patterns were used to study the single-‐crystal films seeded from the Si substrate and propagated along the patterned stripe on top of the insulator. Besides the confirmation of the crystallinity of the film, energy-‐dispersive X-‐ray spectroscopy was applied to investigate the stoichiometry of the compound material after re-‐ solidification. The results show a direct relationship between crystal quality and atomic composition, which suggests a congruent growth for the III-‐V material during the solidification process despite the possibility of out gassing. This proves thatat least for binary III-‐Vs, RMG has this type of “self-‐correction” effect for the stoichiometry of the recrystallized films. In comparison to direct wafer bonding [13] and aspect ratio trapping [14], which are promising techniques for hetero-‐integration of III-‐V on Si, rapid melt growth (RMG) stands out in overall capabilities across different criteria as shown in Table 3. 118 Table 3: Comparison amongst promising process technologies for hetero-‐ integration of III-‐Vs on silicon Direct Wafer Aspect Ratio Rapid Bonding Trapping Melt Growth Defect control ++ -‐ + Multiple materials + Buffer + 300mm compatible -‐ + + Through-‐put -‐ + + GAA + -‐ + redesign Compared with aspect ratio trapping, where defect-‐propagation cannot be trapped along the length of the trench, RMG efficiently terminates twining, anti-‐ phase defects, etc. by the necking mechanism, an analogous process to the defect necking from the seed crystal that occurs in Czochralski growth as shown in Fig. 5.2. 119 Figure 5.2 Schematics of defect analysis of aspect ratio trapping (ART) and rapid melt growth (RMG). The control of defect propagation along the length of the trench is difficult for ART, while RMG can efficiently terminate defect propagation by the necking mechanism. 5.2 CO-‐INTEGRATION OF III-‐V CMOS TRANSISTORS USING RAPID-‐MELT-‐GROWTH In future transport-‐enhanced CMOS devices, it is favorable to adopt different channel materials for n-‐ and p-‐channel devices for optimal performance of each device. In the previous chapter, we argue that the use of different materials for n-‐ and p-‐channel devices brings challenges to process technology. For instance, common gate stack solution [15] and source/drain technology [14] are difficult to achieve. Amongst the different candidates, a combination of InGaAs-‐based NMOS 120 and Ge-‐based PMOS stands out from different perspectives. First of all, the electron and hole mobility in InGaAs and Ge respectively are the highest amongst all conventional semiconductors. From source/drain and gate passivation point of view, the band lineup of In-‐rich InGaAs and Ge is also very favorable. The charge-‐ neutrality level (ECNL) lies in the conduction band of InAs, and is close to the valence band of Ge [16]. However, the co-‐integration of InGaAs and Ge on silicon substrate is very challenging. Besides the involvement of multiple epitaxial growths, the cross contamination issue is critical and inherent with this approach, as both group IV and III-‐V materials are co-‐integrated on silicon substrate. To work around this problem, we proposed the use of all III-‐V CMOS transistors. Because of the superior and unique hole transport properties, antimonides are identified as promising candidates for p-‐channel material. Electron transport is found to be excellent in the same material system as well. At the same time, due to charge-‐neutrality-‐level (ECNL) being close to the valence band, it is very difficult to achieve low interface defect density towards the conduction band, and low contact resistivity. Within III-‐Vs, ECNL for InAs and GaSb is located near the conduction/valence band respectively [16], as shown in Fig. 5.3. Bulk electron/hole mobility in InAs/GaSb is measured to be ~10,000 / ~1,000 cm2/Vs [17]. However, the challengeis then to co-‐integrate both arsenide and antimonide on silicon with a common gate-‐stack and source/drain solution. In this section, we demonstrate the co-‐integration of both InAs NMOS and GaSb PMOS on silicon using rapid-‐melt-‐ growth. Material characterization of the recrystallized film shows the feasibility of this approach for both InAs and GaSb and good material quality. InAs-‐OI, GaSb-‐OI process is further demonstrated. 121 Figure 5.3 InAs NMOS, GaSb PMOS offer advantages in favorable band line-‐up relative to ECNL and excellent electron and hole transport properties. The band-‐lineup with respect to ECNL leads to low Dit level near valence-‐band edge of GaSb and low Schottky barrier height for holes indicated by I-‐V dependence on temperature, both favored for PMOS operation, as shown in previous chapters. Similar argument also holds for InAs NMOS. Table 4: Melting temperature and lattice mismatch with respect to silicon of InAs and GaSb Si InAs GaSb Melting T (°C) 1412 942 712 Mismatch % 0 11.7 12.5 Since the deterministic parameter in RMG is the melting temperature, the technique can be easily applied to more than one III-‐V material regardless of their degrees of lattice mismatch relative to silicon. The lattice constant of InAs and GaSb are 6.0583Å and 6.0959Å at 300K. This means more than 11% lattice mismatch with 122 silicon. The principle of rapid melt growth guarantees the control over the propagation of misfit dislocations. Therefore, InAs NMOS and GaSb PMOS can be co-‐ integrated on silicon using RMG. Table 4 shows the melting temperature and the lattice mismatch against silicon of InAs and GaSb, respectively. The melting temperature of InAs is 942°C, which is more than 400°C below that of silicon. The phase diagram of In-‐Si shows that alloying with In will lower the melting temperature of the alloy [18]. The melting temperature drops sharply with In ratio higher than 90%. In fact, the same principle has been applied to achieve melt-‐induced-‐crystallization (MIC) [19], in which the lowering of melting temperature is used to induce regrowth during annealing to form crystalline structure. During rapid melt growth, at the interface of III-‐V materials and Si, such phenomenon is expected to cause the melting of the silicon seed even though the annealing temperature is well below the melting temperature of silicon. Once the material is in liquid phase, the diffusivity of silicon and III-‐V elements could be order-‐of-‐magnitude higher than those when the material is in solid phase. Even during the short period of time of growth, which is estimated to be on μs level based on a growth rate of more than 1m/s, the intermixing between silicon and III-‐Vs could be a critical issue, especially when the annealing time is constrained to a couple of seconds in RTA system. Therefore, the lower melting temperature of InAs and GaSb, compared to GaAs (1238°C), InP (1062°C), etc., is favorable for the suppression of such intermixing effect. Another effect associated with melting temperature is the high vapor pressure caused by the evaporation of group V atoms. It is difficult to measure the exact vapor pressure at high temperature close to the melting temperature of the III-‐V materials. It can be estimated close to 1000°C, arsenic vapor pressure can be larger than 1 atm. The strength of the micro crucible material may not be strong enough to hold the molten material. Thus, for the integrity of the structure, lower melting 123 temperature of the III-‐V materials is also desired. In summary, the combination of InAs and GaSb stands out in terms of low melting temperature. Due to lattice mismatch, there are a number of point defects or planar defects that can be generated, including stacking faults, twins, and domain boundaries. Different types of defects have different impact on the electrical properties of the film. Planar defects lead to leakage conduction path. Point defects, on the other hand, could be electrically active and of charged states, thus act similar to dopant-‐ like inter-‐band energy levels. RMG process for III-‐Vs is very similar to that for germanium. The III-‐V material is deposited on top of a dielectric on silicon wafer by MBE or sputtering, patterned and then encapsulated with LPCVD SiO2. Stripes are heated beyond the melting temperature using RTA. During the cooling process, epitaxial growth starts from Si seed and propagates through the III-‐V stripe. Transmission Electron Microscopy (TEM) is a common approach to study the defect formation during epitaxial growth. Planar defects can usually be clearly identified by cross-‐sectional TEM, while a more sophisticated approach has to be used to study point defects, e.g. plan view TEM. However, constrained by the geometry of the stripe, which is at most 2-‐5μm in width, a plan view TEM is hard to achieve due to the difficulty in sample preparation. Other approaches like X-‐ray diffraction is also difficult for the structure as well. As the stripes are isolated, the density of the materials may not be high enough to give the signal strength in XRD. Therefore, TEM is used to study the material quality of the III-‐V materials after rapid melt growth. For hetero-‐epitaxy, lattice misfit can be accommodated by inclined stacking fault defects. A stacking fault occurs with an extra plane of atoms inserted into or the removal of one plane in the stacking sequence. The typical width of stacking fault in 124 GaSb can be estimated to be ~15nm, which could be clearly identified in TEM [20]. As shown in Fig. 5.4, TEM images of GaSb after RMG show no such defects in the lateral part of the stripe on large-‐scale. This indicates that the lattice misfit is released near the interface between GaSb and silicon and not affecting in the lateral part of the GaSb, where the devices are to be built. Figure 5.4 TEM images of GaSb stripe after RMG show no visible defects, e.g. threading dislocation, stacking faults, etc. Twin is one type of planar defect resulting from a change in the stacking sequence during crystal growth. During crystal growth and there is not a gradual change in crystallographic orientation, as the twin boundary moves across a region, the crystal lattice flips, and a discrete increment of deformation is attained, indicated by twinning features. 125 Figure 5.5 TEM images of GaSb near the Si seed after RMG. Defects, e.g. twinnings, etc., only propagate over short range due to the efficient termination of defects near the neck region. At the beginning of the growth, the original growth plane is (001), the surface of the twinned crystal is the (221) plane, which bring the surface to various (221) planes or back to (001). As shown in Fig. 5.5, TEM images of GaSb stripe near the silicon seed window indicate that twinning only appears over a relatively small range away from the interface between GaSb and Si. This demonstrates the efficient termination of defect propagation near the neck region. HR-‐TEM of GaSb/InAs stripes 1μm away from the seed window, as in Fig. 5.6, shows high-‐quality crystalline structure. The seed silicon wafer has a crystal orientation of (001). As indicated by the diffraction pattern, the crystal orientation of GaSb/InAs is preserved from the silicon seed. From the reciprocal distance between the dots of different crystal planes, it confirms the lattice constants of GaSb/InAs are close to those of relaxed bulk materials. 126 Figure 5.6 High-‐resolution TEM images of GaSb and InAs ~1μm away from the seed windows. Diffraction-‐patterns indicate single-‐crystallinality. Crystal orientation of Si seed is preserved. Figure 5.7 Diffraction patterns taken at different locations along the stripe of a) GaSb, b) InAs 1μm, 2μm, 3μm away from seed confirm the propagation of the growth as zone axis remains unchanged. The distance from the seed is indicated in the figure. 127 As shown in Fig. 5.7, the diffraction patterns taken along the stripes confirm the propagation of the growth as the zone axis remains unchanged up to 3μm away from the silicon seed window. This also indicates that there is no twisting in the crystal orientation during the growth. 2μm Figure 5.8 Tilted-‐view SEM image showing rough surface and poor coverage around the neck region for InAs thin film grown on SiNx by MOCVD. Smooth surface morphology is critical in achieving good carrier transport in MOSFETs devices. Without the involvement of additional process step, e.g. chemical mechanical planarization (CMP), the surface roughness of the melted materials is largely determined by the as-‐deposited films. Physical vapor deposition (PVD) of the initial III-‐V thin films offers advantages over chemical vapor deposition (CVD) from this perspective. The nucleation process involved in CVD process is hard to initiate on the amorphous dielectrics, resulting in multiple domains or grains and rough surface as shown in Fig. 5.8. Another consideration is step coverage at the edge of the seed window. If the film thickness is to be scaled down, large surface roughness may result in partial coverage of the step of the dielectric material as shown in the SEM images in Fig. 5.9. During the melt-‐regrowth, due to the surface tension of the 128 liquid, the material can break at the neck region, which stops the propagation of the epitaxial growth. Depending on the deposition approach for the initial thin film, even though the crystalline quality of the as-‐deposited thin film is not important, optimization is still necessary to achieve good step coverage and low surface roughness. 500nm 500nm Figure 5.9 Tilted-‐view and cross-‐sectional SEM images of GaSb thin film on dielectric on silicon, showing lack of step coverage around the neck region due to the poor nucleation during MBE growth of GaSb thin film. 129 2μm 200nm Figure 5.10 Top-‐view and cross-‐sectional SEM images of GaSb thin film on dielectric on silicon showing smooth surface on dielectric and step coverage. A low-‐temperature MBE growth is developed to achieve uniform nucleation of the III-‐V layer on dielectric as shown in Fig. 5.10. For GaSb, growth temperature as low as 300°C is used to prevent the nucleation issue on dielectric. The lower limit for growth temperature is set by the stoichiometry of the film. MBE is usually grown with high ratio between group V / III flows to prevent the desorption of the III-‐V materials. At a low temperature, this may result in accumulation of group V atoms. Even though rapid-‐melt-‐growth has the self-‐correction effect [12] to expel the excessive element toward the end of the stripe, it is still favorable to have the film stoichiometry correct to begin with. XPS analysis on low-‐temperature MBE grown 130 GaSb shows that even at 300°C, the ratio between group V and III atoms can be preserved reasonably well to 1:1, while achieving a smooth surface. Figure 5.11 AFM measurement on as-‐deposited film and stripe after rapid-‐melt-‐ growth, showing the surface roughness is improved after RMG. Fig. 5.11 shows the atomic-‐force microscopy measurement on the as-‐deposited GaSb thin film and the stripe after rapid-‐melt-‐growth process. The surface roughness after RMG is improved over the as-‐deposited film. The improvement potentially comes from the wet etching process involved. In principle, the morphology of the thin film should be preserved during the melting by the micro-‐ crucible, thus there will not be a degradation of surface roughness due to the melting process. 131 Figure 5.12 Raman spectra of bulk and RMG GaSb show similar FWHM and peak position. Micro-‐Raman spectroscopy is another available approach to study the materials quality of the thin film after rapid-‐melt-‐growth. For comparison, CZ-‐grown bulk GaSb is used as control sample. As shown in Fig. 5.12, Raman spectroscopy shows similar position and FWHM of LO-‐mode peak compared to bulk sample, indicating good crystalline quality. Figure 5.13 SEM image of the TLM structure for GaSb stripe. 132 To study the electrical properties of the thin film, structure for transfer length method is built on stripes after RMG as shown in Fig. 5.13. The melted thin film of GaSb shows sheet resistance of 9300Ω/sq, for a film thickness of 120nm. Considering point defects are electrically active in GaSb, high resistivity number could be a suggestion of good crystalline quality. Good contacts with ρC of 7.9×10-‐ 6Ωcm2 were obtained by alloying with Ni, together with more than 10 times reduction in sheet resistance. Figure 5.14 TLM measurements on GaSb stripes give high sheet resistance, indicating low concentration of defects, which are electrically active; Ni-‐alloy shows low sheet resistance and ρc. A common gate stack and source/drain technology was developed as shown in Fig. 5.15. The RMG process was very similar for both InAs and GaSb except for the annealing temperature. After obtaining the single-‐crystalline stripes of the III-‐V materials, gate dielectric of Al2O3 was deposited by ALD. W was deposited by 133 sputtering for better sidewall coverage, and then patterned as gate electrode. Thin Ni was deposited and annealed to form Ni-‐III-‐V alloys, followed by the etching of unreacted Ni. Finally, source/drain contact pads were formed by lift-‐off of Ti/Pt. The process flow is summarized in Fig. 5.16. SEM image of the fabricated device is shown in Fig. 5.17. Figure 5.15 InAs NMOS, GaSb PMOS with common device process flow with the same gate stack and self-‐aligned Ni-‐alloy S/D. Figure 5.16 Process flow for InAs-‐OI NMOS, GaSb-‐OI PMOS transistors with Ni-‐alloy SDs integrated on silicon using RMG. 134 Transfer characteristic of fabricated transistor shows that an on/off ratio of 103 can be achieved as in Fig. 5.18. The on/off ratio is currently limited by the film thickness. Due to the low band gap of GaSb (~0.7eV), a thinner film is required to achieve lower off-‐state current. On the other hand, the lower limit of the film thickness is constraint by the step coverage issue. On-‐current of the device can also be further improved with smoother surface. Figure 5.17 SEM image of GaSb PMOS on insulator on silicon integrated with RMG process. Figure 5.18 Transfer characteristics of GaSb-‐OI PMOS showing a on/off ratio higher 103. 135 Back-‐surface between III-‐Vs and the underlying dielectric may not be well passivated, causing back-‐side leakage. Besides the scaling of film thickness, another solution to the problem is through the use of gate-‐all-‐around (GAA) structure, in which the underlying dielectric could be etched away. Fig. 5.19 shows the side-‐view SEM image of the stripe after RMG. Undercut of the dielectric beneath was obtained by wet-‐etch. Figure 5.19 SEM image of sidewall profile of GaSb stripe after RMG shows that underlying dielectric can potentially be etched away to enable GAA structure. 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Kong; B. Cheng; G. Han; Y.-‐C. Yeo, "Towards high performance Ge1−xSnx and In0.7Ga0.3As CMOS: A novel 139 common gate stack featuring sub-‐400 °C Si2H6 passivation, single TaN metal gate, and sub-‐1.3 nm EOT," in Proc. VLSIT 2012, pp.99-‐100, June 2012. [16] J. Robertson and B. Falabretti, “Band offsets of high K gate oxides on III-‐V semiconductors,” J. Appl. Phys., vol. 100, p. 014111, 2006. [17] M.P. Mikhailova, Handbook Series on Semiconductor Parameters, vol.1, M. Levinshtein, S. Rumyantsev and M. Shur, ed., World Scientific, London, 1996, pp. 147-‐168. [18] R. W. Olesinski, N. Kanani, G. J. Abbaschian, “The In-‐Si (indium-‐Silicon) system,” Bulletin of Alloy Phase Diagrams, vol. 6, no. 2, pp. 128-‐130, Apr. 1985. [19] S.-‐W. Lee, S.-‐K. Joo, “Low temperature poly-‐Si thin-‐film transistor fabrication by metal-‐induced lateral crystallization,” IEEE Electron Device Letters, vol. 17, no. 4, pp. 160-‐162, Apr. 1996. [20] D. B. Holt, B. G. Yacobi, Extended Defects in Semiconductors: Electronic Properties, Device Effects and Structures, 2007. CHAPTER 6: CONCLUSION AND OUTLOOK 6.1 CONLUSION In this work, we explored several challenges associated with III-‐V CMOS technology for future digital logic circuit applications. To be as concrete and quantitative as possible, we focused on the 6.1-‐6.2Å material system with InGaSb as the channel material. Surface passivation and MOS structure are the essence of a MOSFET device. We first studied the control of interface traps in Chapter 2. The formation of high-‐ oxygen-‐content GaOx and SbOx interfacial layers on GaSb (001) surfaces by oxidant dosing at low temperature prior to atomic layer deposition was achieved. The suppression of elemental Sb and formation of GaOx and SbOx lead to less dispersion in capacitance-‐voltage characteristics and better gate modulation. A Dit value of 5×1011cm-‐2 near the valence band edge was obtained by the proposed method. Furthermore, to minimize the impact of interface traps on device performance, we proposed a heterostructure that consists of an Al-‐containing barrier layer and an ultra-‐thin Al-‐free interfacial layer. We experimentally demonstrated that the heterostructure enables good quality of the high-‐k dielectric/semiconductor interface and suppresses the impact of interface traps by band engineering. After studies on surface passivation, we reported different considerations in the heterostructure design for single-‐channel III-‐V CMOS with InGaSb as the channel material. Full band and self-‐consistent analysis reveals that low In composition in the compound is favored for the optimal trade-‐off between carrier density of states and injection velocity. It is shown experimentally that AlGaSb/InGaSb provides favorable band alignment that gives good confinement of both electrons and holes. Excellent transport properties of InGaSb were measured by gated Hall experiments, with mobilities up to 4000cm2/Vs and 900cm2/Vs for electrons and holes respectively. Long-‐channel NMOS and PMOS delivered comparable on-‐state currents, which indicates the potential to support both n-‐ and p-‐channel devices with a small gap in performance for realizing complementary logic in III-‐Vs. Source/drain contacts have been identified as the most critical issue. To provide a potential path for the scaling of antimonide-‐based p-‐channel MOSFETs, the use of Ni-‐antimonide alloy was proposed. Studies on the formation and electrical properties of Ni-‐antimonide formed by direct reaction of Ni with antimonide compound demonstrate that the Ni-‐antimonide alloy is a good potential source/drain material in metal source/drain antimonide-‐based p-‐MOSFETs. A self-‐ aligned process for metal S/D MOSFETs using an epitaxial heterostructure with high hole mobility was developed and demonstrates the potential of such source/drain design in further channel length scaling of III-‐V p-‐channel MOSFETs. While Fermi-‐ level pinning near the valence band edge of GaSb is favorable for p-‐type contact, it makes n-‐type contact very difficult. We have demonstrated band engineering of Fermi level depinning for metal/n-‐GaSb contact with the insertion of a TiO2 interfacial layer. The low CBO leads to a reduction in Schottky barrier height without the introduction of excessive tunneling resistance. Lastly, we showed the first demonstration of hetero-‐integration of dual channel III-‐V CMOS transistors on silicon using rapid-‐melt-‐growth technique. Long stripes of InAs and GaSb with high crystalline quality suitable for making SOI-‐FinFET transistors were fabricated on silicon substrates. III-‐V-‐O-‐I transistors with ION/IOFF > 103 were demonstrated. RMG enables a path for transistors with strong electrostatic control and III-‐V CMOS using multiple materials on silicon substrates. 141 6.2 FUTURE WORK The research field of alternative channel materials has progressed rapidly in recent years. The technology has advanced at a fast pace and industry adoption is now close to reality. The development of the process technology for a single device has evolved to a relatively mature stage. The role of academic research has gradually shifted as well. There are several areas where further contribution from academic research is much needed. Firstly, the demonstration of short-‐channel state-‐of-‐the-‐art devices to prove concept, process and device design is important. Nanowire gate-‐all-‐around InGaAs NMOS [1] and core-‐shell structure nanowire MOSFETs [2] are examples of such research. While long-‐channel PMOS has been studied, with the self-‐aligned metallic source/drain process, it is possible to further scale the channel length of p-‐channel antimonide MOSFETs. Secondly, as the research on single MOSFET device has become more mature, the importance of integration on large-‐scale wafers has further elevated. To prove the potential of rapid-‐melt-‐growth, it is important to have a better understanding of the growth mechanism and defect control. Study of the melt recrystallization of ternary compound, defect generation and propagation, as well as accurate evaluation of defect density could contribute to the understanding of RMG in different ways. Since silicon substrates will continue to be the mainstay of the microelectronics industry, silicon-‐based devices will most likely co-‐exist with III-‐V-‐based electronics. For different purposes, one type of technology may be favored compared to the other. For instance, silicon CMOS may have advantages in terms of device density, variability, etc., for the use in SRAM arrays. Assessment of the hybrid technology on the system level with intense circuit and device interaction is necessary. 142 References [1] J. J. Gu, et al., “III-‐V Gate-‐all-‐around Nanowire MOSFET Process Technology: From 3D to 4D,” in Proc. IEDM 2012, pp. 529-‐532, Dec. 2012. [2] K. Tomioka, M. Toshimura, T. Fukui, “A III-‐V nanowire channel on silicon for high-‐performance vertical transistors,” Nature, vo. 488, pp. 189-‐192, 2012. 143

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