Virtual Memory: Paging
Virtual address space partitioned into fixed-size pages of size 2p bytes each
Virtual address space consists of 2n (virtual) pages of size 2p bytes each
Physical memory partitioned into fixed-size page frames of size 2p bytes each
Physical address space consists of 2m page frames of size 2p bytes each
The entire program image stored on paging device (usually disk)
At runtime a subset of the 2n (virtual) pages reside in main memory
Mapping of virtual page numbers to page frames maintained in a Page Table
Each virtual page has a descriptor in the Page Table
Descriptor holds administrative bits and the physical frame number if page is in memory
PDU xxx
Virtual Address (VA)
Page Offset (displacement)
VPN
PFN
Index into
Page Table
Descriptor
PFN
Physical Address (VA)
PFN
Page Table
Page Offset (displacement)
Virtual Memory: Issues
1. Performance Impact
•
Page Fault: Requires disk read (millions of cycles: ms vs ns)
•
Reduce the number of page faults by exploiting locality
• Fully Associative placement of virtual pages in frames
• Replacement (eviction) rule:
•
•
Optimal off-line is Belady scheme (requires future knowledge)
LRU is preferred on-line heuristic
• Too expensive to implement (update LRU stack every access)
• Approximate using the U (Use) bit
•
U bit of all pages cleared periodically by the OS
•
Set when a page is accessed
•
Minimize writes to disk:
• Write-back (copy-back) policy
• Write a Dirty page (D bit set) to disk when evicted from memory
•
Use large page size to amortize disk access overheads (commensurate
with locality in the accesses)
Virtual Memory: Issues
OS page fault overhead : 5ms
Disk Seek and Rotation Latency: 8ms
Transfer rate: 25 MB/sec
Page Fault Service Time
(a) 4KB pages (size of page):
5ms + 8ms + (4KB/25MB) x 1000 ms = 13.16 ms
(b) 4MB pages:
5ms + 8ms + (4MB/25MB) x 1000 ms = 173 ms
High Spatial Locality:
Use large block size
Sequential read of a large table (array): 64MB
(a) No. of page faults: 64MB/4KB = 16,000; Time: 13.16 x 16,000 ms = 210 seconds!
(b) No of page faults: 64MB/4MB = 16; Time: 173 x 16 ms = 2.7s
Virtual Memory: Issues
Performance Impact (contd …)
Page Hit: Requires two memory accesses for each memory reference
First access is for page descriptor in Page Table
Second access is for actual memory word
How do we reduce the penalty associated with Page Table Lookup?
Virtual Memory: Issues
2. Page Tables occupy significant amounts of memory
Page Table for each task (process)
Page Table has one entry for each possible virtual page
Example: For each process:
40-bit virtual address with 4KB pages.
P = 4KB = 212 bytes, hence p = 12.
Number of bits in virtual address (n+p) = 40
Number of bits for VPN (n) = 28
Number of virtual pages (N) = Number of Page Table entries = 228
Assuming 8 bytes per Page Table entry:
Page Table size = 231 bytes = 2GB!
Virtual Memory: Issues
Page Tables size: Smaller with large page sizes
Example: For each process:
40-bit virtual address with 4MB pages.
P = 4MB = 222 bytes, hence p = 22.
Number of bits in virtual address (n+p) = 40
Number of bits for VPN (n) = 18
Number of virtual pages (N) = Number of Page Table entries = 218
Assuming 8 bytes per Page Table entry:
Page Table size = 221 bytes = 2MB
Virtual Memory: Issues
3. Interaction between processor cache and Virtual Memory
Physical Cache
Processor
VA
MMU
PA
L1 Cache
Cache
Miss
Cache Hit
Processor
Virtual Cache
VA
L1 Cache
PA
MMU
Translation Lookaside Buffer
Translation Lookaside Buffer (TLB):
High-speed cache for page descriptors
Subset of page descriptors in the Page Table stored in TLB
TLB checked first for the Page Descriptor
if found, page map available without accessing Page Table
if page descriptor not cached in the TLB: read Page Table entry
TLB (classically) fully associative (less so as as size increases):
Any page descriptor can be stored in any TLB entry
Page descriptor identified by storing VPN in the TAG field
DATA field of TLB entry contains the descriptor
Fully Associative TLB Example
V
1
TAG (VPN)
010
1
111
1xx--
DATA
00
0xx--
10
TLB
VPN
0
VPN
PDU--
PFN
1
0
2
B
1
3
Z
3
4
A
4
0xx-0xx-1xx-0xx-1xx-0xx-1xx-1xx--
Ad
Ad
0
Zd
1
Ad
3
22
2
5
5
6
C
7
D
6
7
Page Table
Descriptors for pages B and
D are cached in the TLB at
present
PFN
B
0
A
1
D
C
2
3
Address Translation: Software TLB handling
CPU: generates (n+p)-bit virtual address Av
MMU:
1. Search the TLB associatively for match of the VPN with the TAG
field of some (valid) TLB entry
2. if TLB does not have an entry for the page /* no TAG matches VPN */
Handle TLB Miss
else
/* Page descriptor found in the TLB */
if P-bit of the page descriptor is OFF /* page not in main memory*/
Handle Page Fault
else /* Descriptor in TLB and page is in main memory */
Handle TLB Hit /* Common Case */
Address Translation: Software TLB handling
CPU: generates (n+p)-bit virtual address Av
MMU:
1 Handle TLB Hit /* Descriptor in TLB and page is in main memory */
Get the m-bit PFN stored in the page descriptor
Update if needed descriptor fields U and W in Page Table
and update corresponding TLB entry (*alternatives possible)
Concatenate PFN with the offset field of Av
Access main memory with the (m+p)-bit physical address
Return accessed word to CPU
* Invalidate TLB entry (on first write) fetch updated values from Page Table on miss
Address Translation: TLB Miss
May be software or hardware controlled
MMU: TLB Miss /*Get descriptor for the referenced page into TLB */
1. Choose an entry in the TLB to evict
Random choice (usually) employed
Write the (possibly updated) descriptor to PageTable[TAG] (* alternatives)
2. Access PageTable[VPN]
Load descriptor into TLB DATA field
Update TLB TAG field to VPN
Address Trace: Page B, C, Z (VPN: 2, 6, 3)
B: TLB Hit C: TLB Miss -- assume TLB entry 0 is evicted
V
1
TAG
110
1xx--
DATA
11
1
111
1xx--
10
TLB (after TLB Miss handling
for C)
Address Translation: Type-1 TLB Miss
Address Trace: Page B, C, Z (VPN: 2, 6, 3)
B: TLB Hit C: TLB Miss -- assume TLB entry 0 is evicted
Z: Type-1 TLB Miss: Fetch descriptor from page table and install in TLB
Assume TLB entry 1 is replaced
Retry access for Z: Page Fault
V
1
TAG
110
1xx--
DATA
11
1
011
0xx--
Zd
TLB (after TLB Miss handling
for Z)
Address Translation: Page Fault
Page Fault /*Handle Page Fault, Invalidate TLB entry*/
OS invoked. Process is swapped out so operations are not synchronous as they appear
1. Make space in memory by evicting a page to disk
a) Select LRU victim page to evict from main memory
(b) Write victim page to disk if it is dirty (D is true)
(c) Update descriptor for evicted page in Page Table
(d) Invalidate TLB entry corresponding to evicted page if it exists
(Should be rare. Pages not represented in TLB would be better LRU candidates)
Z: Page Fault: Suppose victim page is C (evict from page frame 3). Invalidate TLB entry
V
0
TAG
110
1xx--
DATA
11
1
011
1xx--
11
TLB (after Page Fault eviction)
Address Translation: Page Fault
2.
Read faulting page into page frame freed by the eviction
(a) Read faulting page from disk into freed page frame
(b) Update descriptor of faulting page in Page Table and
update descriptor in TLB (* alternative possible)
V
0
TAG
110
1xx--
DATA
11
1
011
1xx--
11
TLB (after Page Fault handling)