ELEC6027 VLSI Design Project
Task:
Design and Implement a Novel 16-bit Microprocessor in
0.35µm CMOS (C035U)
•
Complete IC Design Flow
•
Complex System
– Importance of Systematic Approach
– Modular Design & Test
– Manage Complexity through Hierarchy
•
Team Exercise
1
ELEC6027 VLSI Design Project
1.
Research Document
Milestones
WED week 4
(19th February 2014)
WED week 5
(26th Feb 2014)
WED week 6
(5th March 2014)
WED week 7
(12th March 2014)
• Report on Preliminary Research
2.
Initial Design
• Instruction Set, Datapath Diagram
3.
Behavioural Model
• SystemVerilog
4.
Cross Simulation
• SystemVerilog Control Unit, Magic Datapath
5.
Final Design
FRI week 10
(2nd May 2014)
Tue week 12
(13th May 2014)
• Full Magic Design, Programmer’s Guide
6.
Project Report
• Report on Design and Implementation
2
ELEC6027 VLSI Design Project
Initial Design
Instruction Set
Datapath Diagram
ADD
Syntax
ADD Ry, Rz, Rx
Semantics
Rx <- Ry + Rz
Coding
1011011 x y z
PC
IR
3
R0 (=0)
R1
R2
R3
ELEC6027 VLSI Design Project
Behavioural Model
Test Program
CPU
Control
module control()
Multiply
Datapath
module datapath()
ALU
module alu()
endmodule
endmodule
endmodule
4
Assembly Language
ADD R1,R2,R1
CMP R2,R1
BNE .start
Machine Code (hex)
F3A0
A002
240A
ELEC6027 VLSI Design Project
Cross Simulation
CPU
Topslice_0
Datapath
Bitslice_15
Control
module control()
endmodule
(magic)
Bitslice_14
Bitslice_13
Bitslice_12
Bitslice_11
Bitslice_10
Bitslice_9
Bitslice_8
Bitslice_7
Bitslice_6
Bitslice_5
Bitslice_4
Bitslice_3
Bitslice_2
Bitslice_1
Bitslice_0
Bottomslice_0
Test Program
Multiply
Assembly Language
ADD R1,R2,R1
CMP R2,R1
BNE .start
Machine Code (hex)
F3A0
A002
240A
The submitted SystemVerilog control module may well be a newer version than that submitted
with the behavioural model, in which case a newer SystemVerilog datapath module must also be
submitted.
5
ELEC6027 VLSI Design Project
Final Design
CPU
Cpu_core
Test Programs
Control
Programmer’s Guide
Multiply
Datapath
Assembly Language
ADD R1,R2,R1
CMP Random
R2,R1
BNE .start
Assembly Language
Machine Code
SRL (hex)
R1,R1
F3A0 XOR Factorial
R1,1,R2
A002 ST R3,[8204]
Assembly Language
240A
Machine Code
LD [8004],R3
(hex)
1F1F JSR .fact
4442 SBC R2,1,R2
0330
Machine Code (hex)
E220
0010
8004
Programmer’s Model
Instruction Set
Programming Tips
Example Code
An updated SystemVerilog behavioural model of the processor must be submitted with the final
design.
6
week MON TUE
1
2
3
4
WED
Research
Report
Initial
Design
5
6
THU mini milestones
LAB Confirm Teams
LAB Declaration of
Specialisms
LAB t.b.a.
LAB Draft Design
LAB
Behavioural LAB
Model
7
Cross
Simulation
LAB
8
9
LAB
LAB
10
11
12
LAB
—
Project
Report
Initial Behavioural
Model (executes at least
4 instructions)
Simulation of Basic
Datapath (including
ALU and Data Registers)
Simulation of Placed
and Routed Control Unit
t.b.a.
Simulation of First Cut
Chip in Pad Ring
t.b.a.
FRI
Behavioural
Model with
Interrupts
Final Design
ELEC6027 VLSI Design Project
Thursday Lectures
Week Time Topic
1 10:00 Introduction
This lecture
2 10:00 Basic Processor Design
Including RISCish and CISCish examples
3 10:00 Processor Datapath Design
Including RISCish and CISCish example
4 10:00 Behavioural Modelling
This seminar is intended for SystemVerilog specialists only
5 10:00 Advanced Bitslice Design
This seminar is intended for Datapath specialists only
8