ROCKET
SUPPORTED PLATFORMS
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License .
© Copyright 2015, Intel Corporation, Wind River Systems, Inc.
The kernel used in Wind River Rocket is called Zephyr. These terms, Rocket and Zephyr,
can be used interchangeably throughout this document
Supported Platforms
The kernel supports the platform configurations listed in the table below. An
application can use a platform configuration as is, or it can customize a platform
configuration by changing its default kernel configuration settings.
note
Developers can create new platform configurations that allow an application to run on other target systems.
Platform Configuration
Instruction Set
Architecture
fsl_frdm_k64f
ARM v7E-M
galileo
X86
basic_minuteia
X86
Supported Target Systems
Freescale Freedom
Development Platform
Galileo
Galileo (Gen 2)
QEMU 2.1
The following sections provide details on the respective platforms:
• Platform Configuration: fsl_frdm_k64f
• Platform Configuration: galileo
• Platform Configuration: basic_minuteia
1
Platform Configuration: fsl_frdm_k64f
Overview
The fsl_frdm_k64f platform configuration is used by Zephyr applications that run
on the Freescale Freedom Development Platform (FRDM-K64F). It provides support
for an ARM Cortex-M4 CPU and the following devices:
• Nested Vectored Interrupt Controller (NVIC)
• System Tick System Clock (SYSTICK)
• Serial Port over USB (K20)
note
This platform configuration may work with similar boards, but they are
not officially supported.
Supported Boards
The fsl_frdm_k64f platform configuration has been tested to run on the Freescale
Freedom Development Platform. The physical characteristics of this board (including
pin names, jumper settings, memory mappings, . . . ) can be found below. No claims
are made about its suitability for use with any other hardware system.
Pin Names
LED (RGB)
•
•
•
•
LED_RED = PTB22
LED_GREEN = PTE26
LED_BLUE = PTB21
mbed Original LED Naming
–
–
–
–
LED1
LED2
LED3
LED4
=
=
=
=
LED_RED
LED_GREEN
LED_BLUE
LED_RED
Push buttons
• SW2 = PTC6
• SW3 = PTA4
USB Pins
2
• USBTX = PTB17
• USBRX = PTB16
Arduino Headers
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D0 = PTC16
D1 = PTC17
D2 = PTB9
D3 = PTA1
D4 = PTB23
D5 = PTA2
D6 = PTC2
D7 = PTC3
D8 = PTA0
D9 = PTC4
D10 = PTD0
D11 = PTD2
D12 = PTD3
D13 = PTD1
D14 = PTE25
D15 = PTE24
A0 = PTB2
A1 = PTB3
A2 = PTB10
A3 = PTB11
A4 = PTC10
A5 = PTC11
I2C pins
• I2C_SCL = D15
• I2C_SDA = D14
• DAC0_OUT = 0xFEFE /* DAC does not have a Pin Name in RM */
Jumpers & Switches
The Zephyr kernel uses the FRDM-K64F default switch and jumper settings.
The default switch settings for the Freescale FRDM-K64F are:
Switch Number
Switch
ON Switch OFF
J14
J21
J25
x
SDA+SW1
3
x
MCU
Memory Mappings
The fsl_frdm_k64f platform configuration uses the following default hardware
memory map addresses and sizes:
Physical Address
Size
Access To
0xFFFFFFFF - 0xE0100000
0xE0100000 - 0xE0040000
-
0xE0100000 - 0xE00FF000
0xE00FF000 - 0xE0042000
0xE0042000 - 0xE0041000
0xE0041000 - 0xE0040000
0xE0040000 - 0xE0000000
-
0xE0040000 - 0xE000F000
0xE000F000 - 0xE000E000
0xE000E000 - 0xE0003000
0xE0003000 - 0xE0002000
0xE0002000 - 0xE0001000
0xE0001000 - 0xE0000000
0xE0000000 - 0xA0000000
0xA0000000 - 0x60000000
0x60000000 - 0x40000000
0x44000000 - 0x42000000
0x42000000 - 0x40100000
0x40100000 - 0x40000000
0x40000000 - 0x20000000
0x24000000 - 0x22000000
0x22000000 - 0x20100000
0x20100000 - 0x20000000
0x20000000 - 0x00000000
1GB
1GB
.5GB
32MB
31MB
1MB
.5GB
32MB
31MB
1MB
.5GB
System
External Private
Peripheral Bus
ROM Table
External PPB
ETM
TIPU
Internal Private
Peripheral Bus
Reserved
SCS
Reserved
FPB
DWT
ITM
External device
External RAM
Peripheral
Bit band alias
unnamed
Bit band region
SRAM
Bitband alias
unnamed
Bitband region
Code
For a diagram, see Cortex-M3 Revision r2p1 Technical Reference Manual page 3-11.
Component Layout
Refer to page 2 of the FRDM-K64F Freedom Module User’s Guide, Rev. 0,
04/2014 (Freescale FRDMK64FUG) for a component layout block diagram. See
http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_
m3_dgug.pdf
4
Supported Features
The fsl_frdm_k64f platform configuration supports the following hardware features:
Interface
Controller
Driver/Component
NVIC
on-chip
SYSTICK
UART 1
(OpenSDA v2)
on-chip
on-chip
nested vectored
interrupt controller
system clock
serial port
Other hardware features are not currently supported by the Zephyr kernel. See
vendor documentation for a complete list of Freescale FRDM-K64F board hardware
features.
Interrupt Controller
There are 15 fixed exceptions including exceptions 12 (debug monitor) and 15
(SYSTICK) that behave more as interrupts than exceptions. In addition, there can
be a variable number of IRQs. Exceptions 7-10 and 13 are reserved. They don’t
need handlers.
A Cortex-M3/4-based board uses vectored exceptions. This means each exception
calls a handler directly from the vector table.
Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here identifies
the handlers used for each exception.
Exc#
Name
1
2
3
4
5
6
Reset
NMI
Hard fault
MemManage
Bus
Usage fault
11
12
SVC
Debug
monitor
PendSV
SYSTICK
14
15
Remarks
Used by Zephyr Kernel
MPU fault
undefined
instruction, or
switch attempt
to ARM mode
system
system
system
system
system
system
initialization
fatal error
fatal error
fatal error
fatal error
fatal error
context switch
system fatal error
context switch
system clock
5
note
After a reset, all exceptions have a priority of 0. Interrupts cannot run
at priority 0 for the interrupt locking mechanism and exception handling
to function properly.
Interrupts
Interrupt numbers are virtual and numbered from 0 through N, regardless of how the
interrupt controllers are set up. However, with the Cortex-M3 which has only one
NVIC, interrupts map directly to physical interrupts 0 through N, and to exceptions
16 through (N + 16).
The Cortex-M4 has an 8-bit priority register. However, some of the lowest-significant
bits are often not implemented. When citing priorities, a priority of 1 means the
first priority lower than 0, not necessarily the priority whose numerical value is 1.
For example, when only the top three bits are implemented, priority 1 has a priority
numerical value of 0x20h.
When specifying an interrupt priority either to connect an ISR or to set the priority
of an interrupt, use low numbers. For example, if 3 bits are implemented, use 1, 2,
and 3, not 0x20h, 0x40h, and 0x60h.
Interrupt priority is set using the prio parameter of :cirq_connect().
The range of available priorities is different if using Zero Latency Interrupts (ZLI) or
not.
When not using ZLI:
• 2 to 2n -2, where n is the number of implemented bits (e.g. 2 to 14 for 4
implemented bits)
• Interrupt locking is done by setting BASEPRI to 2, setting exceptions 4, 5, 6,
and 11 to priority 1, and setting all other exceptions, including interrupts, to a
lower priority (2+).
When using ZLI:
• 3 to 2n -2, where n is the number of implemented bits (e.g. 3 to 6 for 3
implemented bits)
• Interrupt locking is done by setting BASEPRI to 3, setting exceptions 4, 5, 6,
and 11 to priority 1, setting ZLI interupts to priority 2 and setting all other
exceptions, including interrupts, to a lower priority (3+).
note
The hard fault exception is always kept at priority 0 so that it is allowed
to occur while handling another exception.
6
note
The PendSV exception is always installed at the lowest priority available,
and that priority level is thus not avaialble to other exceptions and
interrupts.
Interrupt Tables
There are a number of ways of setting up the interrupt table depending on the range
of flexibility and performance needed. The two following kconfig options drive the
interrupt table options:
SW_ISR_TABLE and SW_ISR_TABLE_DYNAMIC
Depending on whether static tables are provided by the platform configuration or by
the application, two other kconfig options are available:
SW_ISR_TABLE_STATIC_CUSTOM and IRQ_VECTOR_TABLE_CUSTOM
The following interrupt table scenarios exist:
SW_ISR_TABLE=y, SW_ISR_TABLE_DYNAMIC=y For maximum ease of
use, maximum flexibility, a larger footprint, and weaker performance.
This is the default setup. The vector table is static and uses the same handler
for all entries. The handler finds out at runtime what interrupt is running and
invokes the correct ISR. An argument is passed to the ISR when the ISR is
connected.
The table, in the data section and therefore in SRAM, has one entry per
interrupt request (IRQ) in the vector table. An entry in that table consists of
two words, one for the ISR and one for the argument. The table size, calculated
by multiplying the number of interrupts by 8 bytes, can add significant overhead.
In this scenario, some demuxing must take place which causes a delay before
the ISR runs. On the plus side, the vector table can be automatically generated
by the Zephyr kernel. Also, an argument can be passed to the ISR, allowing
multiple devices of the same type to share the same ISR. Sharing an ISR
can potentially save as much, or even more, memory than a software table
implementation might save.
Another plus is that the vector table is able to take care of the exception
handling epilogue because the handler is installed directly in the vector table.
SW_ISR_TABLE=y, SW_ISR_TABLE_DYNAMIC=n For advanced use,
medium flexibility, a medium footprint, and medium performance.
In this setup, the software table exists, but it is static and pre-populated. ISRs
can have arguments with an automatic exception handling epilogue. Table
pre-population provides better boot performance because there is no call to
:cirq_connect during boot up; however, the user must provide a file to override
the platform’s default ISR table defined in sw_isr_table.S. This file must
7
contain the _sw_isr_table[] variable initialized with each interrupt’s ISR. The
variable is an array of type struct _IsrTableEntry. When a user provides their
own sw_isr_table.c, the type can be found by including sw_isr_table.h.
SW_ISR_TABLE=n For advanced use, no flexibility, the best footprint, and the
best performance.
In this setup, there is no software table. ISRs are installed directly in the vector
table using the _irq_vector_table symbol in the .irq_vector_table section.
The symbol resolves to an array of words containing the addresses of ISRs.
The linker script puts that section directly after the section containing the
first 16 exception vectors (.exc_vector_table) to form the full vector table in
ROM. An example of this can be found in the platform’s irq_vector_table.c.
Because ISRs hook directly into the vector table, this setup gives the best
possible performance regarding latency when handling interrupts.
When the ISR is hooked directly to the vector, the ISR must manually invoke
the :c_IntExit() function as its very last action.
note
This configuration prevents the use of tickless idle.
SW_ISR_TABLE=y, SW_ISR_TABLE_STATIC_CUSTOM=y For overriding the static ISR tables defined by the platform:
In this setup, the platform provides the _irq_vector_table symbol and data
in sw_isr_table.s.
SW_ISR_TABLE=n, IRQ_VECTOR_TABLE_CUSTOM=y In this setup,
the platform provides the _irq_vector_table symbol and data in
irq_vector_table.c.
Configuration Options
LDREX_STREX_AVAILABLE Set to ‘n’ when the ldrex/strex instructions are
not available.
DATA_ENDIANNESS_LITTLE Set to ‘n’ when the data sections are big endian.
STACK_ALIGN_DOUBLE_WORD Set to ‘n’ only when there is a good reason
to do it.
NUM_IRQ_PRIO_BITS The platform configuration sets this to the correct value
for the board (“4” for FRDM board, IIRC).
RUNTIME_NMI The kernel provides a simple NMI handler that simply hangs in
a tight loop if triggered. This fills the requirement that there must be an NMI
handler installed when the CPU boots.If a custom handler is needed, enable
this option and attach it via _NmiHandlerSet().
8
NUM_IRQS The platform configuration sets this value to the correct number of
interrupts available on the board. The default is ‘34’.
SW_ISR_TABLE Set to ‘n’ when the platform configuration does not provide
one.
SW_ISR_TABLE_DYNAMIC Set to ‘n’ to override the default.
System Clock
FRDM-K64F uses an external oscillator/resonator. It can have a frequency range of
32.768 KHz to 50 MHz.
Serial Port
The FRDM_K64F board has a single out-of-the-box available serial communication
channel that uses the CPU’s UART0. It is connected via a “USB Virtual Serial Port”
over the OpenSDA USB connection.
Bibliography
1. The Definitive Guide to the ARM Cortex-M3, Second Edition by Joseph Yiu
(ISBN?978-0-12-382090-7)
2. ARMv7-M Architecture Technical Reference Manual (ARM DDI 0403D
ID021310)
3. Procedure Call Standard for the ARM Architecture (ARM IHI 0042E, current
through ABI release 2.09, 2012/11/30)
4. Cortex-M3 Revision r2p1 Technical Reference Manual (ARM DDI 0337I
ID072410)
5. Cortex-M4 Revision r0p1 Technical Reference Manual (ARM DDI 0439D
ID061113)
6. Cortex-M3 Devices Generic User Guide (ARM DUI 0052A ID121610)
7. K64 Sub-Family Reference Manual, Rev. 2, January 2014 (Freescale
K64P144M120SF5RM)
8. FRDM-K64F Freedom Module User’s Guide, Rev. 0, 04/2014 (Freescale
FRDMK64FUG)
9
Platform Configuration: galileo
Overview
The galileo platform configuration is used by Zephyr applications that run on Galileo
(Gen 1 or Gen 2) Development Boards.
It provides support for a Quark CPU and the following devices:
• High Precision Event Timer (HPET)
• Peripheral Component Interconnect (PCI) bus query
• Serial Ports in Polling and Interrupt Driven Modes
note
This platform configuration may work with similar boards, but they are
not officially supported.
Supported Boards
This section either provides links to, or describes the physical characteristics of the
boards that are supported by the galileo platform configuration. Subsections provide
information on pin names, jumper settings, memory mappings and board component
layout.
Pin Names
Refer to page 46 of the Document Number: 329676-001US Intel®Quark SoC X1000
Datasheet for a component layout diagram. Click the link to open the Intel®Galileo
Datasheet.
Also, refer to page 9 of the Intel®Galileo Board User Guide.
Jumpers & Switches
The Zephyr kernel uses the Galileo default jumper settings except for the IOREF
jumper which must be set to match the external operating voltage of either 3.3 V
or 5 V.
The default switch settings for the Galileo are:
Jumper
Setting
IOREF
VIN
3.3V or 5V
5V Jumpered
10
For more information, refer to page 14 of the Intel®Galileo Board User Guide.
Memory Mappings
The galileo platform configuration uses default hardware memory map addresses and
sizes.
For a list of memory mapped registers, see page 868 of the Intel®Quark SoC X1000
Datasheet.
Component Layout
Refer to page 3 of the Intel®Galileo Datasheet for a component layout diagram.
Click the link to open the Intel®Galileo Datasheet.
For a block diagram refer to page 38 of the Intel®Quark SoC X1000 Datasheet.
Supported Features
The galileo platform configuration supports the following hardware features:
•
•
•
•
HPET
PCI bus
Advanced Programmed Interrupt Controller (APIC)
Serial Ports in Polling and Interrupt Driven Modes
Interface
Controller
Driver/Component
HPET
PCI
APIC
UART
on-chip
on-chip
on-chip
on-chip
system clock
PCI library
interrupt controller
serial port-polling; serial
port-interrupt
Other hardware features are not currently supported by the Zephyr kernel. See the
Intel®Quark Core Hardware Reference Manual for a complete list of Galileo board
hardware features, and the Intel®Quark Software Developer Manual for Linux
PCI
The PCI driver initiates a PCI library scan of the PCI bus for any attached devices.
If devices are detected, they are initialized.
11
note
The PCI library does not support 64 bit devices. Memory address and
size storage only require 32 bit integers.
Serial Port Polling Mode Support
The polling mode serial port allows debug output to be printed.
For more information, see Intel®Quark SoC X1000 Datasheet, section 18.3.3 FIFO
Polled-Mode Operation
Serial Port Interrupt Mode Support
The interrupt mode serial port is used to provide general serial communication and
external communication.
For more information, see Intel®Quark SoC X1000 Datasheet, section 21.12.1.4.5
Poll Mode
Interrupt Controller
The galileo platform configuration uses the Zephyr kernel static Interrupt Descriptor
Table (IDT) to program the Advanced Programmable Interrupt Controller (APIC)
interrupt redirection table.
Interrupts
IRQ
Name
Remarks
Used by Zephyr Kernel
17
INTB
UART
20
timer
HPET
serial port, when used in
interrupt mode
timer driver
note
The galileo platform configuration does not support interrupt sharing,
for example, two PCI devices can not use same IRQ.
Configuration Options
CONFIG_PCI_DEBUG Set to “y” to enable PCI debugging functions for PCI
bus scanning. Allows a list of all the PCI devices found to be printed.
12
HPET System Clock Support
Galileo uses HPET timing with legacy-free timer support. The galileo platform
configuration uses HPET as a system clock timer.
Known Problems and Limitations
There is no support for the following:
•
•
•
•
•
•
•
Isolated Memory Regions
Serial port in Direct Memory Access (DMA) mode
Serial Peripheral Interface (SPI) flash
General-Purpose Input/Output (GPIO)
Inter-Integrated Circuit (I2C)
Ethernet
Supervisor Mode Execution Protection (SMEP)
Bibliography
1.
2.
3.
4.
5.
Intel®Galileo Datasheet.
Intel®Galileo Board User Guide.
Intel®Quark SoC X1000 Datasheet.
Intel®Quark Core Hardware Reference Manual.
Intel®Quark Software Developer Manual for Linux.
13
Platform Configuration: basic_minuteia
Overview
The |codename| uses the basic_minuteia platform configuration to emulate the
galileo platform (or something similar) running on QEMU. It provides support for an
x86 Minute IA CPU and the following devices:
• HPET
• Advanced Programmable Interrupt Controller (APIC)
• NS16550 UART
note
This platform configuration makes no claims about its suitability for use
with actual galileo hardware, or any other hardware.
Supported Boards
The basic_minuteia platform configuration has been tested on QEMU 2.1.
Supported Features
The basic_minuteia platform configuration supports the following hardware features:
Interface
Controller
Driver/Component
HPET
APIC
NS16550
UART
on-chip
on-chip
on-chip
system clock
interrupt controller
serial port
The kernel currently does not support other hardware features on this platform.
Interrupt Controller
Refer to the galileo.
note
The basic_minuteia platform configuration does not support PCI.
14
HPET System Clock Support
The basic_minuteia platform configuration uses an HPET clock frequency of 25
MHz.
Serial Port
The basic_minuteia platform configuration uses a single serial communication channel
that uses the NS16550 serial driver operating in polling mode. To override, enable
the UART_INTERRUPT_DRIVEN Kconfig option, which allows the system to be
interrupt-driven.
Known Problems or Limitations
The following platform features are unsupported:
•
•
•
•
•
•
•
•
Isolated Memory Regions
Serial port in Direct Memory Access (DMA) mode
Serial Peripheral Interface (SPI) flash
General-Purpose Input/Output (GPIO)
Inter-Integrated Circuit (I2C)
Ethernet
Supervisor Mode Execution Protection (SMEP)
PCI
15