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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Overview and Status of Metal S/D Schottky-Barrier
MOSFET Technology
John M. Larson, Member, IEEE, and John P. Snyder, Member, IEEE
Abstract—In this paper, the metal source/drain (S/D) Schottkybarrier (SB) MOSFET technology is reviewed. The technology
offers several benefits that enable scaling to sub-30-nm gate
lengths including extremely low parasitic S/D resistance (1% of
the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths,
superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic
bipolar action. These and other benefits accrue using a lowthermal-budget CMOS manufacturing process requiring two
fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials
such as high-k gate insulators and strained silicon substrates. SB
MOSFET technology state of the art is also reviewed, and shown
to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region.
SB-PMOS devices tend to have superior performance compared to
NMOS, but NMOS performance has recently improved by using
ytterbium silicide or by using hybrid structures that incorporate
interfacial layers to lower the SB height.
Index Terms—CMOSFETs, erbium silicide, metal source/drain
(S/D), platinum silicide, Schottky barriers (SBs), short-channel
MOSFET, transistors.
I. INTRODUCTION
T
HE INTERNATIONAL Technology Roadmap for Semiconductors (ITRS) states that the semiconductor industry has “entered the era of material-limited device
scaling” [1]. The building-block materials of the conventional
MOSFET device—silicon, silicon dioxide, doped silicon, and
polysilicon—have been extended to their performance limitations [1]. New materials, such as high-k gate insulators (to
replace SiO2 gate insulators), strained-silicon substrates (to
replace Si substrates), metal gates (to replace polysilicon gates),
and metal source/drains (S/Ds) (to replace doped silicon S/Ds),
are therefore under development. This review provides a technology overview and status summary for metal S/D Schottkybarrier (SB) MOSFET technology.
Metal S/D SB MOSFET devices replace S/D impurity doping with metal, typically silicide. There are numerous motivations for replacing doping with metal in the S/D regions,
including low parasitic S/D resistance, low-temperature processing for S/D formation, elimination of parasitic bipolar action, and inherent physical scalability to sub-10-nm gate-length
Manuscript received June 30, 2005; revised November 21, 2005. The review
of this paper was arranged by Editor J. Welser.
The authors are with Spinnaker Semiconductor, Bloomington, MN 55425
USA (e-mail: john.larson@spinnakersemi.com).
Digital Object Identifier 10.1109/TED.2006.871842
dimensions, which is due to the low resistance of metal and
the atomically abrupt junctions formed at the silicide–silicon
interface. An SB junction forms at the interface of the metal S/D
and the semiconductor substrate. For this reason, a metal S/D
MOSFET device is commonly referred to as an SB MOSFET
(SB-MOS, SB-PMOS, SB-NMOS, or SB-CMOS).
Nishi first proposed the idea of completely replacing doped
S/Ds with metal in 1966 when he submitted a Japanese patent
on the idea, which was later issued in 1970 [2]. In 1968,
Lepselter and Sze published the first paper on the topic, focusing on a PMOS bulk device employing PtSi for the S/D
regions [3]. The PMOS device fabricated by Lepselter and Sze
was plagued by poor performance with room-temperature drive
current ten times lower than that of a conventional MOSFET.
The next publication appeared in 1981, when Koeneke showed
how the lateral gap between the edge of the S/D electrodes
and the gate electrodes strongly affects the drive current of
the device, with a smaller gap resulting in significantly higher
performance [4], [5].
Later in the 1980s, a variety of SB-MOS device structures were studied, including the first SB-NMOS device by
Mochizuki and Wise [6], devices employing interfacial doping layers between the metal S/D and the channel [5], [7],
[8] and asymmetric devices in which the source is metal
and the drain is doped silicon [9], [10]. Sugino et al. and
Swirhun et al. realized that SB-MOS can essentially eliminate
parasitic bipolar action, and demonstrated a CMOS structure
having an SB-PMOS device and conventional NMOS device,
which was immune to latchup [7], [11], [12]. The pre-1994
SB-MOS literature established proof of concept but at the same
time suffered from low performance due to device architecture
and process-technology issues.
Since 1994, when Tucker et al. [13], [14] and Snyder
[15] realized the advantages for device scaling of SB-MOS
technology, state-of-the-art SB-CMOS process technology has
significantly advanced. This review will provide a technology overview of the device physical architecture, fabrication
process, the basic principles of operation and the current state
of the art.
II. SB-MOS: DEVICE ARCHITECTURE
A cross section TEM of a short-channel SB-PMOS device
is shown in Fig. 1(a), while a schematic representation of an
SB-MOS device is shown in Fig. 1(b). The principal innovation
of SB-CMOS technology is in the engineering of the source
and drain electrodes. In its simplest form, the SB-MOS device
0018-9383/$20.00 © 2006 IEEE
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY
Fig. 1. (a) High-resolution cross-section TEM of a 22-nm SB-PMOS device
[21]. The S/D electrodes are formed completely of platinum silicide, while
a conventional MOS gate stack is used on a silicon semiconductor substrate.
(b) Schematic of an SB-MOS device illustrating several key parameters.
architecture entirely replaces conventional impurity-doped S/D
electrodes with metal, the metal typically being a metal silicide.
For the purposes of introduction, the embodiment of the device
illustrated by Fig. 1 will be considered.
A. SB-MOS: Metal S/D Features
Fig. 1(a) shows that the atomically abrupt metal silicide
source and drain electrodes extend laterally proximal to the
gate electrode, and may be overlapped with the gate. As shown
in Fig. 1(b), a few important physical parameters define the
device. As with a doped S/D MOSFET device, the parameters
include the gate length (Lg ), effective channel length (Lch ),
and the S/D junction depth (tSD ). The sidewall thickness (tSW )
and the S/D overlap parameter (LSD,OL ) are especially critical
in the design of an SB-MOS device. The location of the
peak concentration of a laterally uniform vertically nonuniform
retrograde channel implant (Dpd ) is also very important.
For an SB-MOS device, the S/D-to-substrate junction is
fundamentally different than that of a conventional MOSFET
device. At the S/D junction, doped S/D conventional MOSFET
devices form a p-n diode junction, whereas metal S/D SBMOS devices form an atomically abrupt SB junction having an
SB height φb . An SB junction leads to fundamentally different
mechanisms for controlling current, which will be summarized
later in this review.
SB-CMOS circuits require complementary-performing SBNMOS and SB-PMOS devices. This is accomplished by either
using a mid-gap silicide or using complementary silicides. Midgap silicides have an SB height of approximately half the silicon
bandgap, while complementary silicides provide two different
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complementary barrier heights. SB-MOS devices fabricated
using mid-gap silicides provide extremely poor saturation drive
current [16] and high subthreshold leakage current due to high
gate-induced drain leakage and junction leakage.
An optimized complementary silicide structure requires a
silicide for NMOS having a low barrier to electrons on
N-type silicon (φb,e ) and for PMOS, a low barrier to holes
on P-type silicon (φb,h ). Silicides such as platinum silicide
(PtSi) for SB-PMOS and a rare-earth silicide for SB-NMOS
such as erbium silicide (ErSix ) or ytterbium silicide (YbSix )
provide the lowest known barrier heights to P- and N-type
silicon, respectively, with φb,h for PtSi of ∼ 0.15-0.27eV [17],
[18] and φb,e for the rare-earth silicides ErSix and YbSix of
∼ 0.27-0.36eV [19], [20]. One area of significant interest is
φb engineering, which has been achieved by using a hybrid
structure that has an interfacial layer placed between the metal
and the semiconductor channel resulting in a reduced effective
barrier height. These hybrid devices, denoted as “Schottkylike” devices, will be reviewed in more detail below.
One of the “difficult challenges” cited by the ITRS [1] is
parasitic S/D resistance. The ITRS predicts that starting in
2008, there is no known solution for the parasitic S/D resistance
challenge [1]. The metal silicide S/D architecture provides an
elegant solution to this problem, since metal-to-metal contacts
provide very low contact resistivity and the metal silicide
provides low sheet resistance. For example, we have measured
the contact resistivity of aluminum metallization on PtSi to be
1.6 × 10−9 Ω · cm2 , and a 60-nm-thick PtSi sheet resistance to
be 6 Ω/sq.
B. SB-MOS: Other Elements
Any semiconductor substrate can be used for SB-CMOS,
such as silicon, strained silicon, or silicon germanium. A conventional MOS gate stack is used, including a gate insulator
with an effective oxide thickness (EOT), and a gate electrode
having a gate length Lg . The device is fully compatible with
any gate insulator technology such as SiO2 , nitrided oxides,
or high-k dielectrics and with standard polysilicon gates or
metal gates.
To control subthreshold leakage current, channel doping
concentration is reduced due to the built-in SB, which provides
a potential barrier that acts as a quasi-pocket or halo implant. In
addition to having a lower doping concentration in the channel,
a simpler doping profile can be used, such as a retrograde
implant that comprises a laterally uniform and vertically
nonuniform doping profile [21]. Halo or pocket implants are
eliminated from the structure and manufacturing process. Depending on the channel length, the retrograde channel implant may have a peak dopant concentration of approximately
1018 −1019 cm−3 located at a depth Dpd of approximately
25–100 nm below the gate insulator [21]. In the region 0–10 nm
below the gate insulator, where a majority of the mobile charge
flows from source to drain, the SB-MOS dopant concentration is 1016 −1017 cm−3 , or approximately 90%–99% lower
compared to a doped S/D device. Reduced channel doping
provides improved effective carrier mobility. Alternatively,
silicon-on-insulator (SOI) substrates or multigate structures
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
may be used to assist in controlling subthreshold leakage
[22], [23].
A thin sidewall spacer helps minimize S/D-to-gate underlap
so that the SB junctions to the channel region are in close
proximity to the gate electrode. The thickness of the sidewall
spacer (tSW ) should be less than about 10 nm. The S/D overlap
parameter LSD,OL is the lateral distance from the S/D edge
to the edge of the gate electrode. When a lateral gap exists
between the S/D edge and the gate edge, the S/D are said to
have gate underlap (LSD,OL < 0). If no lateral gap is formed
and the S/D-to-channel junction is located beneath the gate
electrode, the S/D are said to have gate overlap (LSD,OL > 0).
The optimum value for LSD,OL is determined by minimizing
the capacitance due to junction proximity to the gate [24],
minimizing the parasitic junction resistance induced by underlap, and minimizing the gate-induced drain-leakage current
(IGIDL ). Although the above description of SB-MOS device
architecture focuses on a bulk substrate version, many other
SB-MOS architectures have been demonstrated, including SOI
[16], [17], [22], [25]–[33], FinFET [23], and Schottky-like
devices with interfacial layers [23], [30], [31], and [34]–[36].
III. SB-MOS: PROCESS FLOW
The manufacturing process for SB-CMOS is simpler than
conventional bulk CMOS, requiring fewer process and photolithography steps. The process is fully compatible with existing silicon CMOS factories and does not require novel
process equipment. The manufacturing process begins with a
standard isolation process such as STI or LOCOS. Standard
well implants and channel implants are provided next. Then,
a dual-doped polysilicon or metal-gate process is provided.
Standard lithography and etch technologies are used to form
the gate fine lines. A thin (< 10 nm) sidewall spacer is formed
on the gate and an anisotropic sidewall spacer etch exposes
the active regions. Pocket or halo implants are not needed
to control short-channel effects. The built-in SB at the metal
source and drain channel interface, which is augmented by
laterally uniform channel implants, effectively controls shortchannel effects. S/D extension and deep contact implants are
also eliminated.
When complementary silicides are used, a dual-silicide
exclusion-mask process is used to form the S/D regions of
the NMOS and PMOS devices. The silicide exclusion mask is
typically composed of an oxide hard mask. For example, after
deposition of an oxide layer, the oxide hard mask is patterned
and etched so that the S/D regions of the PMOS devices are
exposed and a self-aligned PtSi process used to form PtSi S/Ds
of the PMOS devices. Then, the S/D regions of the NMOS
devices are similarly exposed and a self-aligned ErSi process
used to form the ErSi S/D regions of the NMOS devices. The
platinum and erbium are provided by standard physical vapor
deposition (PVD) process equipment. The junction depth and
lateral silicide growth is determined by the amount of material
deposited. Because the effective gate length Leff is determined
by the extent of lateral silicide growth, it is important that the
uniformity of deposited material be at least 5% across the wafer,
which is achievable in modern PVD production tools. For these
particular silicides, the maximum anneal temperature required
for the silicide reaction is less than 600 ◦ C. Finally, back-end
metallization is provided using conventional techniques.
There are many variations of this basic flow and device architecture, most of which engineer the S/D structure differently
by introducing an interfacial layer of doping or a thin insulator
between the metal S/D and the channel region to lower the
effective SB height. Examples of process steps used to provide
these interfacial layers include the implant-to-silicide process
[37], dopant segregation [35], [36], and thin interfacial insulator
layers [38]. These and other techniques will be discussed in
more detail when the state of the art is reviewed below. If
the SB height is sufficiently lowered, then halo implants, SOI
substrates, or FinFET structures will be needed to control shortchannel effects.
The dual-silicide exclusion-mask process requires some adjustment from a conventional bulk CMOS flow. In one version
of this process, a silicide exclusion mask is provided and
patterned such that the PMOS active regions are exposed.
After cleaning, an HF clean removes the native oxide, and
the wafers are immediately loaded for platinum deposition.
A standard sputter-deposition tool can be used for platinum
deposition to thicknesses of ∼ 10–50 nm. A 500-◦ C 1-h furnace
anneal forms the PtSi. Then, the unreacted Platinum not in
contact with silicon is removed by an aqua regia wet strip.
The process is then repeated for the ErSi self-aligned silicide
module. Following the formation of a second silicide exclusionmask layer and Erbium deposition, ErSix is formed by either
a furnace anneal at approximately 400 ◦ C for about 1 h or a
higher temperature (500 ◦ C) shorter anneal time (5–10 min)
RTA process. Sulfuric peroxide is used to remove the unreacted
erbium and then the second oxide hard mask is removed. This
dual-silicide exclusion-mask process requires only two masks
compared to four for a typical doped S/D CMOS process.
There are significant process advantages with SB-CMOS
technology. For example, following the formation of the gate
stack, the maximum process temperature is less than 600 ◦ C.
S/D extension and deep ion-implantation steps are eliminated
as are the high-temperature 1000-◦ C spike or flash anneals
required to activate the S/D dopants. These steps are replaced
with the dual-silicide exclusion-mask process described above,
which has a maximum temperature less than 600 ◦ C. This is
a very important advantage as it enables integration of other
new critical material systems into CMOS process flows, such
as high-k gate insulators, metal gates, and strained silicon.
The properties of these new materials tend to degrade upon
high-temperature annealing typical of doped S/D technology,
but are more stable when using a thermal budget less than
600 ◦ C [34]. Furthermore, because ion-implantation steps for
S/D formation are eliminated, strained substrates are not damaged by high-dose or high-energy implants, thereby minimizing
substrate damage and degradation of charge carrier-mobility
improvement in the strained channel region. The process equipment required for ion implantation of the S/D and spike/flash
annealing is also eliminated and replaced with relatively simple
sputter-deposition and anneal tools. Finally, statistical variation
endemic to doped S/D architectures is virtually eliminated by
the use of well-controlled metal silicides. Random statistical
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY
Fig. 2.
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Qualitative surface (S) and subsurface (SS) band diagrams. (a) SB-PMOS device. (b) Conventional impurity-doped S/D PMOS device.
variations in the positioning of the S/D contacts to the channel
region due to dopant diffusion effects are eliminated.
IV. SB-MOS: PRINCIPLES OF OPERATION
Although metal S/D SB-CMOS technology is similar to
doped S/D conventional CMOS technology in many respects,
there are differences in the fundamental principles of operation.
These differences are traceable to the different nature of the
junction between the S/D regions and the semiconductor substrate, which is an SB diode contact for SB-MOS technology.
The basic operating principles of an SB-PMOS device with
a finite SB for hole emission to the valence band are illustrated
in Fig. 2 and are compared to a conventional PMOS device.
Surface and subsurface band diagrams are shown in the OFF
state and a surface band diagram is shown in the ON state.
Fig. 2(a) shows that the SB-PMOS device Fermi levels for the
source and drain silicide are attached to the silicon band gap
close to the valence band in the “OFF” and “ON” states in the
top and bottom band diagrams, respectively. The resulting SB is
∼ 0.23 eV to holes and ∼ 0.87 eV to electrons if PtSi is used
for the metal region. If barrier-height engineering is used to
lower the effective barrier height, the band structure will be
modified due to the presence of high P+ dopant concentration
near the source or thin interfacial layers between the source and
the channel regions. Fig. 2(b) shows that the band diagrams for
SB-PMOS and conventional PMOS devices are quite similar
except at the source and drain regions, where the metal silicide
Fermi level is replaced by the silicon bands in conventional
PMOS and the SB-PMOS bands have a built-in Schottky potential barrier φb at the S/D junction to the channel. The band
diagrams for an SB-NMOS device are the mirror image of those
shown in Fig. 2.
For the SB-PMOS device, the emitted current density at the
source (Js ) is the sum of the current emission over the barrier
(the thermal emission Jth ) and current emission through the
barrier (thermionic field emission and field-emission current).
For the sake of this review, thermionic field emission and fieldemission current will be lumped into one component of current,
denoted as the field-emission current Jfe . The thermal-emission
current can be determined by classical thermal-emission
theory [39]:
−φb
Jth = A∗ T 2 e −kT
qV
e kT − 1
(1)
where A∗ is the Richardson constant, T is temperature, and
V is the applied bias. The tunneling field-emission current is
a much more complicated calculation and will be discussed
further below.
When a low electric field (E-field) is present at the source
electrode, there is virtually no field-emission current and the
total current Js equals Jth . However, as the E-field increases
at the source, Jfe increases rapidly, while Jth remains approximately constant. When the gate is biased in the ON state,
and a large E-field is present at the source tip below the
gate electrode (e.g., 300 MV/cm), Js is dominated by fieldemission current. For this reason, an SB-MOS transistor is often
referred to as a field-emission device in the ON state. With this
background, both the ON- and OFF-state operational regimes
will be discussed in greater detail.
A. Subthreshold Leakage Current (IOFF )
As with any MOSFET technology, SB-MOS subthreshold leakage current is typically dominated by three components (not including gate insulator leakage): 1) gate-induced
drain-leakage current (IGIDL ); 2) junction leakage (Ij ); and
3) S/D thermal-emission leakage current (Ith ):
IOFF = IGIDL + Ij + Ith .
(2)
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 2(a) illustrates the band diagram in the OFF state for
an SB-PMOS device, with the drain biased at Vds = Vdd and
Vgs = 0. For PMOS, IGIDL is caused by the tunneling of
electrons through the relatively large but thin barrier at the drain
side in the OFF state, which is a result of the close proximity of
the drain to the gate. For SB-PMOS, the SB to electrons (φb,e )
is the difference between the silicon band gap (Eg ) and the
barrier height to holes (φb,h )
φb,e ≈ Eg − φb,h .
(3)
The amount of electron (PMOS) or hole (NMOS) tunneling
current causing IGIDL is strongly sensitive to the barrier height
φb,e or φb,h , respectively. Semiconductor substrates with lower
band gaps Eg such as germanium will suffer from significantly
increased IGIDL [40]. IGIDL is also highly sensitive to the
barrier width, which is controlled by the E-field (ED ) and
potential profile at the drain. Parameters such as LSD,OL , EOT,
and Vd determine ED and the potential profile, which in turn
determines the barrier thickness, the tunneling current through
the barrier, and IGIDL .
Previously fabricated SB-PMOS devices [21] of various gate
lengths were used to investigate IGIDL . Briefly, a blanket As
implant was provided to the active area to reduce subthreshold
leakage current. The gate stack consisted of 100-nm-thick
in situ phosphorus-doped amorphous silicon on an 18-Å gate
oxide. The use of an n-type gate material produces a 1.1-V
threshold voltage shift, which is accounted for by applying
an additional −1.1 V to the gate. The gate oxide is relatively
thick for the gate lengths produced, which means an added
gate voltage must be applied in order to achieve a reasonable
electric field in the oxide (Eox ). The additional gate voltage
was determined by using a detailed MOS capacitor-simulation
software that accounted for the n-type polysilicon gate, the
relatively thick gate oxide of 18 Å, polysilicon depletion and
inversion-layer quantization effects, and which resulted in an
Eox appropriate for the device gate length such as 6–7 MV/cm.
Gate lithography was performed using a 248-nm stepper with a
double-exposure phase-shift mask approach [41]. A sub-10-nm
sidewall spacer was provided by a thermally grown oxide.
Finally, PtSi S/D electrodes were formed using an evaporation
process to deposit the platinum and a furnace anneal of 550 ◦ C
for 60 min. Fig. 3 illustrates measured subthreshold data for
various bias conditions, gate lengths, and channel doping. The
IGIDL is ∼ 0.01−300 pA/µm, depending on the doping and
bias conditions, and is relatively independent of gate length.
Junction leakage current (Ij ) for an SB-MOS device is
caused by the reverse-biased Schottky diode at the drain electrode. For example, for a PMOS device with PtSi drain contacts
on an N-type well, at Vd = −1.0 V, the PtSi/N-type well
contact is a reverse-biased SB diode. Fig. 4 shows the Schottky
diode curves for PtSi and ErSix on lightly doped (1015 cm−3 )
N- and P-type substrates, respectively. The PtSi and ErSix
SB diodes provide Ij of 2.6 and 38.6 fA/µm2 , respectively.
For a typical layout of a 65-nm node transistor, the length
of the drain is approximately 195 nm, which results in an Ij
of 0.4 and 6 fA/µm at |Vd = 1.0 V|, for PtSi and ErSix ,
respectively.
Fig. 3. Examples of SB-PMOS IGIDL leakage current for various gate-length
devices (25 nm, 60 nm, 80 nm, and 1 µm) for a drain bias of −1.0 V. Vg∗ is Vg
minus 1.1 V. IGIDL is estimated by extrapolating the slope of the Id −Vg curve
from the subthreshold data. The portion of the Id −Vg curve that is nearly flat
is due to the junction leakage current. The inset shows the effect of the channel
implant and Vd on IGIDL (indicated range covers all four gate lengths).
Fig. 4. Diode curves for ErSix and PtSi diodes formed on a P- and N-type
substrates, respectively.
However, when the substrate is more heavily doped, the
reverse leakage current of PtSi and ErSix diodes increases. For
a modestly doped device, with a peak doping concentration
of 1018 cm−3 at a depth of 50 nm, and 50-nm-deep S/D
junctions, the SB diode reverse leakage increased to 500 and
2 pA/µm2 at |Vd | = 1.0 V, resulting in an Ij of 100 and
0.4 pA/µm for PtSi and ErSix , respectively. The PtSi junction
leakage could be significantly reduced by optimizing the dopant
profile and PtSi depth, or by using an SOI structure.
The most significant contribution to subthreshold leakage
current for SB-CMOS technology is source-to-drain thermalemission leakage current (Ith ). This is clearly shown by Fig. 3
for the 25-, 60-, and 80-nm SB-PMOS devices. Due to the
presence of φb , SB-MOS devices have an intrinsic advantage
in controlling Ith because φb plays the roll of a pocket or halo
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY
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B. ON-State Drive Current (ION )
Fig. 5. Id −Vg transistor curves of a 25-nm SB-PMOS transistor having no
channel implant. The applied gate voltage Vg is the indicated gate voltage Vg∗
minus 1.1 V.
implant, without having to add any dopants to the channel
region. Unimplanted 25-nm-gate-length SB-PMOS devices illustrate the effectiveness of the SB control of thermal-emission
leakage current. Devices were fabricated using the same
process as those shown in Fig. 3, but no channel implant
was provided. Fig. 5 provides Id −Vg curves for this unimplanted 25-nm-gate-length device, which shows that ION is
629 µA/µm, IOFF is 6140 nA/µm, and the ON–OFF current
ratio is 102. An ON–OFF ratio of 100 is remarkable considering
the device gate length and the fact that the channel is only
lightly doped (1015 cm−3 ).
For practical applications of SB-MOS technology, much
lower subthreshold leakage current is required. This is achieved
by augmenting the SB with a modest channel implant having a vertically nonuniform but laterally uniform doping profile, such as that used for the devices shown in Fig. 3. The
25-nm device in Fig. 3, which is identical to the device in
Fig. 5 except for the modest channel implant, has an ION of
460 µA/µm and IOFF of 168 nA/µm, for an ON–OFF current
ratio of 2700. Compared to the undoped device, IOFF decreased
by 97% while ION only decreased by 27%. This illustrates the
good control of thermal-emission leakage current provided by
a relatively low-concentration simple channel doping profile
and process.
The surface doping concentration near the gate insulator was
estimated to be 2 × 1016 cm−3 from simulation of the implant
process. It is important to note that no high-dose halo or pocket
implant was used for these devices. As a result, we estimate that
the doping concentration within 10 nm of the gate insulator is
90%–99% lower for SB-MOS devices having φb of ∼ 0.25 eV,
compared to conventional doped S/D devices having a halo
channel implant. Lower channel doping provides a number
of benefits, including significantly reduced junction and gate
capacitance, thereby enhancing the frequency response of
the device, which improves device performance [21]. Fully
depleted SOI technology provides another means to improve
the source-to-drain thermal-emission leakage current [22].
When a strong electric field is present at the source electrode, virtually all of the source-emitted current is due to field
emission of carriers that tunnel through the SB. As the channel
charge increases, the E-field at the source tip reduces due
to charge screening effects, which reduces the field-emitted
current, until equilibrium is achieved. The physics and models required to understand the ON-state drive current of an
SB-MOS device are fundamentally different than those used
in a doped S/D conventional MOSFET device. Furthermore,
at this time, simple analytical expressions describing the
current–voltage relationships of an SB-MOS device over a
broad range of bias conditions and device physical parameters
are not available. In order to predict the ON-state performance
of an SB-MOS device, one must model the field-emission
current from the source by computational means.
At least four approaches have been reported for estimating
the field-emission tunneling current Jfe through the sourceside sharp triangular Schottky potential barrier, which is shown
in the ON-state band diagram in Fig. 2(a). These approaches
include: 1) analytical expressions for Jfe combined with fitting parameters; 2) numerical integration techniques using the
Wenzel–Kramers–Brillouin (WKB) approximation for modeling tunneling probabilities; 3) numerical integration techniques
using the exact Airy function for modeling tunneling probabilities, assuming a sharp triangular potential barrier; and
4) numerical integration techniques using the exact Airy function for modeling tunneling probabilities, assuming an arbitrary
barrier shape. The simplest of these analytical expressions
was used by Hattori and co-workers [42], [43] and Padovani
and Stratton [44]. However, Jfe calculated by more accurate
techniques can be several orders of magnitude different then the
analytical expressions, especially at high electric fields [15].
More accurate calculations of Jfe , such as those listed in
cases 2)–4), involve detailed analysis of the carrier velocity
distribution, density of states, Fermi function, and tunneling
probability for carriers that tunnel from the metal into the
semiconductor through the sharp triangular SB at the source
tip. Regarding the calculation of the tunneling probability, one
approach uses the WKB approximation, which is a relatively
simple expression for the tunneling probability that can be
numerically integrated over a range of carrier energies [45].
Unfortunately, this approach may suffer in accuracy for the
conditions of SB-MOS technology [15], [46].
The most accurate technique for calculating the critical tunneling probability over a broad range of device structures and
bias conditions uses Airy functions together with assumptions
about the nature of the potential distribution near the SB contact. Specifically, either a sharp triangular barrier [case 3)] or
an arbitrary barrier [case 4)] are assumed [47]. An example of
Jfe versus E-field for several barrier heights and a broad range
of electric fields is provided by Winstead and Ravaioli [47] and
shows that Jfe varies by four to five orders of magnitude for
E-fields ranging from 5 × 104 to 5 × 106 V/cm, the range of
electric fields typically observed at the source of an SB-MOS
device. This result explains the sensitivity of the ON-state
SB-MOS performance to the E-field generated at the source
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
of the device. Furthermore, the strong sensitivity of Jfe to the
barrier height φb is clearly shown by Winstead and Ravaioli
[47]. For an electric field of 3 × 106 V/cm, Jfe decreases
by a factor of 20 as the barrier height φb increases from
0.13 to 0.39 eV. Generally, in order to maximize the fieldemission current in the ON-state, the barrier height φb should be
low (sub-0.3-eV) and the E-field at the source tip should be high
(greater than 106 V/cm). Finally, Winstead further demonstrates
that a full-band Monte Carlo device simulator coupled to an
Airy-function tunneling model reproduces the measured data
with reasonable accuracy [47].
We provide in Fig. 6 additional dc transistor data for
25-, 60-, and 80-nm-gate-length bulk SB-PMOS devices with
a finite barrier height of ∼ 0.27 eV and no interfacial layer
between the PtSi S/D contacts to the channel region. They
were fabricated using the same process as previously described
above. The ON-state Vg∗ was set to provide an appropriate Eox
for each gate-length device, based on detailed MOS capacitor
simulations described above. For example, applying a Vg∗ of
−1.8 V to an N+ polysilicon gate on a 1.8-nm gate oxide results
in an Eox of 7 MV/cm, which is the same Eox achieved by applying −1.1 V to a metal gate on a 0.9-nm EOT gate insulator,
the metal gate having a work function similar to P+ polysilicon. Table I summarizes the ION and IOFF performance of
these devices and compares them to ITRS specifications [48]–
[50]. These SB-PMOS devices provide total OFF-state leakage
current of 168, 11.9, and 6 nA/µm, ON-state current of 460,
311, and 300 µA/µm, and ION /IOFF ratio of 2700, 26 000,
and 50 000 for the 25-, 60-, and 80-nm devices, respectively.
An upward-sloping sublinear turn-on characteristic is commonly observed in SB-MOS Id −Vd curves [21]. It is not known
yet how this characteristic will affect the digital frequency
response of SB-CMOS technology. It is an artifact of the current
emission process, which depends on high E-fields at the source,
and is not indicative of a high parasitic resistance external to the
channel region. In fact, for the devices shown in Fig. 6, the total
external parasitic resistance is 1% of the total device resistance.
Further, as noted by others, the effect of the sublinear characteristic on ac response may be offset by reduced transit times
due to source-side “hot” carriers having high initial velocities
caused by the strong electric field at the metal source [51], [52].
The devices also have a two-slope subthreshold Id −Vg characteristic, as shown by Fig. 6. The initial slope is due to thermal
emission while the second slope is due to the field-emission
tunneling mechanism. The changing subthreshold slope is not
a signature of the short-channel effect, but instead is caused by
the different SB-MOS current control mechanisms [46].
C. Parasitic Bipolar Gain Eliminated
Latchup and other reliability problems such as soft errors
or single-event upsets are highly sensitive to the source-side
bipolar emitter efficiency. For a doped S/D device, the source
junction is a good emitter, while a rectifying SB junction is generally a poor minority-carrier injector [12]. The
common–emitter current gain β of an SB junction has been
shown previously to be three to six orders of magnitude lower
than that of a conventional source junction, virtually eliminat-
Fig. 6. SB-PMOS Id −Vg and transconductance curves for gate lengths of
(a) 80; (b) 60; and (c) 25 nm. The devices have a channel implant, 1.8-nm
gate oxide, and N+ polysilicon gates, causing a −1.1-V shift in the threshold voltage. The applied gate voltage Vg is the indicated gate voltage Vg∗
minus 1.1 V.
ing the parasitic bipolar effect [53]. Reducing β and eliminating
parasitic bipolar action leads directly to a natural and unconditional immunity to latchup and single transistor latch regardless
of substrate type and doping, Vdd , and layout. Further, other
deleterious effects traceable to the parasitic bipolar effect will
be eliminated or significantly reduced, such as multicell and
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY
1055
TABLE I
COMPARISON OF ITRS PMOS HIGH-PERFORMANCE LOGIC
SPECIFICATIONS WITH THE PERFORMANCE DEMONSTRATED FOR
SB-PMOS TECHNOLOGY. THE GATE VOLTAGE OF THE SB-PMOS DEVICES
FROM THIS PAPER IS SCALED SUCH THAT THE ELECTRIC FIELD IN THE
OXIDE (Eox ) IS APPROXIMATELY EQUIVALENT TO THAT PROVIDED
BY THE ITRS SPECIFICATIONS. THE 25-nm DEVICE BIAS
CONDITIONS PROVIDES A 7.0-MV/cm Eox WHILE THE
60- AND 80-nm DEVICES HAVE A 6.7-MV/cm Eox
cluding conventional NMOS. We have reported here additional
dc data for 25-, 60-, and 80-nm-gate-length devices, which, to
our knowledge, represents the state of the art for dc ION , IOFF ,
and Gm SB-PMOS performance.
A majority of the SB-MOS short-channel literature has
employed a silicide S/D architecture on either bulk or SOI
substrate without using interfacial layers. One exception is the
FinFET device presented by Tsui and Lin [23]. Tsui reports
a metal S/D device that has an interfacial layer placed between the metal S/D and the channel region provided by an
“implant-to-silicide” technique. Tsui reports a drive current of
250 µA/µm and an ON–OFF current ratio of 109 , although a
109 ON–OFF current ratio may be difficult to achieve with a
reasonable threshold voltage and drive current.
Kinoshita et al. disclosed a high-performance 50-nm-gatelength SB-NMOS device using an approximately 10-nm-thick
interfacial dopant layer between the source and drain [35], [36].
The interfacial dopant layer is formed by a dopant-segregation
effect. The device had a 25-Å gate oxide and was operated with
a Vdd of 2.0 V. The drive current of the device is reported to be
1670 µA/µm at an OFF-state leakage current of 100 nA/µm,
which is approximately 20% greater than conventional NMOS
devices fabricated by the same process. Although this qualifies as a Schottky-like device versus a pure SB-NMOS device with no interfacial layer, the SB-NMOS performance of
this Schottky-like device sets the performance standard for
SB-NMOS technology, even though a relatively high Vdd is
used. A first-ever sub-100-nm Schottky-like SB-CMOS ring
oscillator was fabricated. A gate delay of approximately 30 ps is
extracted from the reported data. Scaling the EOT of this device
will significantly improve the ring-oscillator performance.
Other research groups have used interfacial layers, including Nishisaka et al. and Matsumoto et al. who formed a
doped S/D extension between the metal and channel region [30], [31]. However, this extension was laterally 80-nm
long, meaning the device is not a Schottky-like device. Ultrathin
interfacial insulator layers have also been used for the purpose
of passivating the interface between the metal and semiconductor, which reduces the effective barrier height [38], [58], and
[59]. However, to date, no data have been provided in which
a thin interfacial insulating layer is successfully integrated into
an SB-MOS device, perhaps due to integration challenges.
In 2004, Zhu et al. reported using several silicides for the
SB-NMOS S/D formation, including ErSix , DySix , and YbSix ,
with YbSix reported to have a barrier height of 0.27 eV [19].
This is better than the typically reported 0.28-eV barrier for
ErSix , and Zhu further reported that ytterbium provided a
smoother YbSi/Si interface and was not as sensitive to oxygen
as erbium, providing improved manufacturability. YbSi provided a 240% improvement in SB-NMOS ION performance
and the ION −IOFF ratio improved by two to three orders of
magnitude for a 4-µm-gate-length device. Ytterbium silicide
may be a preferred material system for implementing an allmetal SB-NMOS technology.
There is some debate about the optimal SB height needed
for competitive SB-CMOS technology. Some have claimed a
zero or even negative barrier height is required for acceptable
performance [60], while other results suggest that very high
single-cell soft-error rates. Unconditional latchup immunity
and substantially reduced soft-error rates improve circuit reliability for both memory and logic applications, especially
as device geometries scale into the sub-50-nm and sub1.2-V Vdd regimes. This is a significant technology advantage
for highly scaled CMOS, which is becoming increasingly sensitive to parasitic bipolar action and soft errors for both memory
and logic devices [54], [55].
V. SB-MOS: STATE OF THE ART
The SB-MOS device-fabrication literature covers a number
of topics including, for example, the proof-of-concept demonstration of various SB-MOS device architectures, SB height
engineering, and integration of new silicides, such as ErSix and
YbSix , into MOSFET device-fabrication process flows. Table II
provides examples of the state-of-the-art for SB-MOS literature
for devices having gate lengths less than 250 nm. In 1999,
Wang et al. demonstrated a bulk 27-nm-channel-length PtSi
SB-PMOS device, with a drive current of 350 µA/µm, which
initially set the standard for drive-current performance for
highly scaled SB-MOS technology [56]. In 2000, Kedzierski
and co-workers demonstrated sub-25-nm SOI SB-PMOS and
SB-NMOS devices [16], [22], and [57]. OFF-state performance
of the PtSi SB-PMOS and ErSix SB-NMOS devices was significantly improved by using an SOI substrate. For example,
ION of 270 and 190 µA/µm were reported for PMOS and
NMOS, respectively. IOFF was 0.54 and 19 nA/µm, resulting
in ION /IOFF current ratios of 5 × 105 and 104 for PMOS and
NMOS, respectively.
In 2004, we reported SB-PMOS high-performance 280-GHz
cutoff frequency (fT ) data for sub-30-nm devices [21]. This
was the best fT reported for any silicon MOS transistors, in-
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
TABLE II
SUMMARY OF SUB-250-nm-GATE-LENGTH SB-NMOS AND SB-PMOS LITERATURE. THE COLUMN LABELED “TECHNOLOGY” HAS A
COMMA-SEPARATED LIST FOR EACH ROW WITH THE FORMAT TYPE, STR, SIL, SDENG. TYPE IS THE DEVICE TYPE (N = NMOS, P = PMOS). STR IS
THE D EVICE S TRUCTURE (B = BULK, S = SOI, F = FinFET). SIL I S THE S ILICIDE T YPE FOR THE S OURCE AND D RAIN (S ELF E XPLANATORY ).
SDENG IS THE S/D ENGINEERING TYPE (1 = STANDARD, 2 = INTERFACIAL LAYER)
performance can be achieved with devices having a sub-0.3-eV
barrier height [21]. The recent focus on barrier-height lowering techniques is driven by the belief that very low barriers are needed to make SB-MOS performance acceptable for
commercial application, and that the leading silicide material
candidates for SB-NMOS tend to have higher barrier heights of
0.27–0.36 eV. Recently, this issue was addressed by simulation
studies that suggest a finite positive barrier of 0.06–0.1 eV
is needed for SB-PMOS and SB-NMOS to make SB-CMOS
technology speed performance competitive with doped S/D
technology [24], [61]. Experimental SB-CMOS circuit demonstrations in silicon will be needed to resolve the optimal SB
height for SB-CMOS technology.
VI. CONCLUSION
The principle feature of SB-CMOS technology is metal
S/Ds. Metal S/Ds are inherently lower resistance and atomically abrupt, providing a long-term scalability advantage. The
metal S/D junction to the channel forms a SB, which provides improved IOFF leakage control. It further enables lower
doping in the channel region, which results in higher channel
mobility. Fewer implants, reduced implant doses, and dramatically lower S/D temperature of formation (< 600 ◦ C) cause
less damage to mobility-enhancing materials in the channel
region such as strained Si, thereby further improving mobil-
ity. SB junctions also eliminate parasitic bipolar action and
latchup, and are much less sensitive to radiation effects that
induce soft errors. There are no shallow S/D formation implants and high-temperature activation anneals, which provide
several benefits including a simpler, lower mask count lower
cost manufacturing process, and lower temperature S/D formation process. A low-thermal-budget process enables integration of performance-enhancing materials such as high-k gate
dielectrics, metal gates, and strained silicon, all of which lead
to other substantial advantages such as reduced gate leakage,
lower power, and higher effective carrier mobility. Together,
these features and benefits make SB-CMOS technology a worthy candidate for scaling to sub-25-nm gate lengths.
The development of SB-MOS technology has advanced significantly in the past ten years. High-performance SB-PMOS
devices with a PtSi S/D architecture and 25-, 60-, and 80-nmgate-length have been demonstrated. The ON current and
OFF currents of these devices do not yet meet the ITRS
requirements, but extremely high cutoff frequency (fT ) has
been measured to be 280 GHz. SB-NMOS devices fabricated using thin dopant-segregation junctions provide the
highest reported SB-NMOS performance, and were shown
to have superior performance to otherwise identical conventional NMOS devices. For pure metal S/D SB-NMOS devices, YbSix has been identified as an alternative to ErSix for
SB-NMOS technology, providing a slightly lower barrier height
LARSON AND SNYDER: OVERVIEW OF METAL S/D SB MOSFET TECHNOLOGY
1057
(0.27 eV), better film quality, and improved manufacturability.
Sub-100-nm-gate-length SB-CMOS ring oscillators have been
demonstrated using the dopant-segregation technique with
Schottky-like contacts.
Finally, to date, the reported fabricated devices tend to have
nonideal physical parameters such as high EOT and gates with
improper work function. This makes it difficult to compare
the performance of SB-MOS devices to conventional PMOS
and NMOS technology. Demonstration of a sub-50-nm-gatelength SB-CMOS circuit having a proper EOT integrated with
optimized SB-NMOS and SB-PMOS silicide process technologies is critical, and will be a significant step forward for
SB-CMOS state of the art and will help resolve the debate about
the optimal SB height required for competitive SB-CMOS
technology.
MOSFET using Ytterbium silicide,” IEEE Electron Device Lett., vol. 25,
no. 8, pp. 565–567, Aug. 2004.
M. Jang, Y. Kim, J. Shin, and S. Lee, “Characterization of erbiumsilicided Schottky diode junction,” IEEE Electron Device Lett., vol. 26,
no. 6, pp. 354–356, Jun. 2005.
M. Fritze, C. L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt,
C. L. Keast, J. Snyder, and J. Larson, “High-speed Schottky-barrier
pMOSFET with fT = 280 GHz,” IEEE Electron Device Lett., vol. 25,
no. 4, pp. 220–222, Apr. 2004.
J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu,
“Complementary silicide S/D thin-body MOSFETs for the 20 nm gate
length regime,” in IEDM Tech. Dig., 2000, pp. 57–60.
B.-Y. Tsui and C.-P. Lin, “A novel 25-nm modified Schottky-barrier
FinFET with high performance,” IEEE Electron Device Lett., vol. 25,
no. 6, pp. 430–432, Jun. 2004.
D. Connelly, C. Faulkner, and D. E. Grupp, “Optimizing Schottky S/D
offset for 25-nm dual-gate CMOS performance,” IEEE Electron Device
Lett., vol. 24, no. 6, pp. 411–413, Jun. 2003.
A. Itoh, M. Saitoh, and M. Asada, “A 25-nm-long channel metal-gate
p-type Schottky S/D metal-oxide-semiconductor field effect transistor on
separation-by-implanted-oxygen substrate,” Jpn. J. Appl. Phys., vol. 39,
no. 8, pp. 4757–4758, Aug. 2000.
M. Jang, Y. Kim, J. Shin, S. Lee, and K. Park, “A 50-nm-gate-length
erbium-silicided n-type Schottky barrier metal-oxide-semiconductor
field-effect transistor,” Appl. Phys. Lett., vol. 84, no. 5, pp. 741–743,
Feb. 2004.
W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of shortchannel Schottky S/D metal-oxide-semiconductor field-effect transistor on silicon-on insulator substrate and demonstration of sub-50-nm
n-type devices and metal gate,” Jpn. J. Appl. Phys., vol. 38, no. 11,
pp. 6226–6231, Nov. 1999.
H. Sato, H. Sato, T. Iguchi, and M. Asada, “Increase drive current by Pt/W
protection on short-channel Schottky S/D metal-oxide-semiconductor
field-effect transistors with metal gate,” Jpn. J. Appl. Phys., vol. 43,
no. 9A, pp. 6038–6039, 2004.
Q. T. Zhao, P. Kluth, H. L. Bay, S. Lenk, and S. Mantl, “Nanopatterning
of epitaxial CoSi2 using oxidation in a local stress field and fabrication
of nanometer metal-oxide-semiconductor field-effect transistors,” J. Appl.
Phys., vol. 96, no. 10, pp. 5775–5780, Nov. 2004.
S. Matsumoto, M. Nishisaka, and T. Asano, “CMOS application of
Schottky S/D SOI MOSFET with shallow doped extension,” Jpn. J. Appl.
Phys., vol. 43, no. 4B, pp. 2170–2175, 2004.
M. Nishisaka, S. Matsumoto, and T. Asano, “Schottky S/D SOI MOSFET
with shallow doped extension,” Jpn. J. Appl. Phys., vol. 42, no. 4B,
pp. 2009–2013, Apr. 2003.
G. Larrieu and E. Dubois, “Schottky-barrier S/D MOSFETs on ultrathin
SOI body with a tungsten metallic midgap gate,” IEEE Electron Device
Lett., vol. 25, no. 12, pp. 801–803, Dec. 2004.
W. Saitoh, S. Yamagami, A. Itoh, and M. Asada, “35 nm metal gate
SOI-p-MOSFETs with PtSi Schottky S/D,” in Proc. Device Res. Conf.,
1999, pp. 30–31.
S. Y. Zhu, H. Y. Hu, J. D. Chen, S. J. Whang, J. H. Chen, C. Shen,
C. X. Zhu, S. J. Lee, M. F. Li, and D. S. H. Chan et al., “Low temperature
MOSFET technology with Schottky barrier S/D, high-k gate dielectric
and metal gate electrode,” Solid State Electron., vol. 48, no. 10/11,
pp. 1987–1992, Oct./Nov. 2004.
A. Kinoshita, C. Tanaka, K. Uchida, and J. Koga, “High-performance
50-nm-gate-length Schottky-S/D MOSFETs with dopant-segregation
junctions,” in VLSI Symp. Tech. Dig., 2005, pp. 158–159.
A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution
for high-performance Schottky-S/D MOSFETs: Schottky barrier height
engineering with dopant segregation technique,” in VLSI Symp. Tech.
Dig., 2004, pp. 168–169.
B.-Y. Tsui and C.-P. Lin, “Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs,” IEEE Trans. Electron Devices,
vol. 52, no. 11, pp. 2455–2462, Nov. 2005.
M. Tao, D. Udeshi, S. Agarwal, E. Maldonado, and W. P. Kirk, “Negative
Schottky barrier between titanium and n-type Si(001) for low-resistance
ohmic contacts,” Solid State Electron., vol. 48, no. 2, pp. 335–338,
Feb. 2004.
E. H. Rhoderick and R. H. Williams, “Metal-semiconductor contacts,”
in Monographs in Electrical and Electronic Engineering, 2nd ed.
P. Hammond and R. L. Grimsdale, Eds. Oxford, U.K.: Clarendon, 1988.
S. Zhu, R. Li, S. J. Lee, M. F. Li, A. Du, J. Singh, C. Zhu, A. Chin, and
D. L. Kwong, “Germanium pMOSFETs with Schottky-barrier germanide
S/D, high-K gate dielectric and metal gate,” IEEE Electron Device Lett.,
vol. 26, no. 2, pp. 81–83, Feb. 2005.
R EFERENCES
[1] “Front end processes,” in International Technology Roadmap for Semiconductors 2003 Edition. Austin, TX: Semiconductor Industry Assoc.,
2003.
[2] Y. Nishi, “Insulated gate field effect transistor and its manufacturing
method,” Patent 587 527, 1970.
[3] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-effect
transistor using Schottky barrier contacts for source and drain,” Proc.
IEEE, vol. 56, no. 8, pp. 1400–1402, Aug. 1968.
[4] C. J. Koeneke, S. M. Sze, R. M. Levin, and E. Kinsbron, “Schottky
MOSFET for VLSI,” in IEDM Tech. Dig., 1981, pp. 367–370.
[5] C. J. Koeneke and W. T. Lynch, “Lightly doped Schottky MOSFET,” in
IEDM Tech. Dig., 1982, pp. 466–469.
[6] T. Mochizuki and K. D. Wise, “An n-channel MOSFET with
Schottky source and drain,” IEEE Electron Device Lett., vol. EDL-5,
no. 4, pp. 108–111, Apr. 1984.
[7] S. E. Swirhun, E. Sangiorgi, A. J. Weeks, R. M. Swanson, K. C.
Saraswat, and R. W. Dutton, “A VLSI-suitable Schottky-barrier CMOS
process,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 194–202,
Feb. 1985.
[8] C. S. Oh, Y. H. Koh, and C. K. Kim, “A new P-Channel MOSFET
structure with Schottky-Clamped source and drain,” in IEDM Tech. Dig.,
1984, pp. 609–612.
[9] B.-Y. Tsui and M.-C. Chen, “A novel process for high-performance
Schottky barrier PMOS,” J. Electrochem. Soc., vol. 136, no. 5, pp. 1456–
1459, May 1989.
[10] M. Kimura and T. Matsudate, “A new type of Schottky tunnel transistor,”
IEEE Electron Device Lett., vol. 15, no. 10, pp. 412–414, Oct. 1994.
[11] M. Sugino, L. A. Akers, and M. E. Rebeschini, “CMOS latch-up
elimination using Schottky barrier PMOS,” in IEDM Tech. Dig., 1982,
pp. 462–465.
[12] ——, “Latchup-free Schottky-barrier CMOS,” IEEE Trans. Electron
Devices, vol. ED-30, no. 2, pp. 110–118, Feb. 1983.
[13] J. R. Tucker, C. Wang, and P. S. Carney, “Silicon field-effect transistor based on quantum tunneling,” Appl. Phys. Lett., vol. 65, no. 5,
pp. 618–620, Aug. 1994.
[14] J. R. Tucker, C. Wang, J. W. Lyding, T.-C. Shen, and G. C. Abeln,
“Nanometer scale MOSFETs and STM paterning on Si,” in Proc. Int.
Conf. Solid State Devices Mater., 1994, pp. 322–324.
[15] J. P. Snyder, “The physics and technology of platinum silicide source and
drain field effect transistors,” Ph.D. dissertation, Stanford Univ., Stanford,
CA, 1996.
[16] J. Kedzierski, P. Xuan, V. Subramanian, J. Bokor, T.-J. King, C. Hu, and
E. Anderson, “A 20 nm gate-length ultra-thin body p-MOSFET with
silicide S/D,” Superlattices Microstruct., vol. 28, no. 5/6, pp. 445–452,
2000.
[17] E. Dubois and G. Larrieu, “Measurement of low Schottky barrier heights
applied to S/D metal-oxide-semiconductor field effect transistors,” J.
Appl. Phys., vol. 96, no. 1, pp. 729–737, Jul. 2004.
[18] V. W. L. Chin, J. W. V. Storey, and M. A. Green, “Characteristics
of p-type PtSi Schottky diodes under reverse bias,” J. Appl. Phys., vol. 68,
pp. 4127–4132, Oct. 1990.
[19] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du,
C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier S/D
[20]
[21]
[22]
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
[32]
[33]
[34]
[35]
[36]
[37]
[38]
[39]
[40]
1058
[41] M. Fritze, R. Mallen, B. Wheeler, D. Yost, J. P. Snyder, B. Kasprowicz,
B. Eynon, and H. Y. Liu, “Limits of strong phase shift patterning for
device research,” in Proc. SPIE—Optical Microlithography XVI, 2003,
pp. 327–343.
[42] R. Hattori, A. Nakae, and J. Shirafuji, “A new type of tunnel-effect transistor employing internal field emission of Schottky barrier junction,” Jpn.
J. Appl. Phys., vol. 31, no. 10B, pp. L1467–L1469, Oct. 1992.
[43] R. Hattori and J. Shirafuji, “Numerical simulation of tunnel effect transistor employing internal field emission of Schottky barrier junction,” Jpn.
J. Appl. Phys. 1, Regul. Rap. Short Notes, vol. 33, no. 1B, pp. 612–618,
Jan. 1994.
[44] F. A. Padovani and R. Stratton, “Field and thermionic-field emission
in Schottky barriers,” Solid State Electron., vol. 9, no. 7, pp. 695–707,
Jul. 1966.
[45] M. Ieong, P. M. Solomon, S. E. Laux, W.-S. P. Wong, and
D. Chidambarrao, “Comparison of raised and Schottky S/D MOSFETs
using a novel tunneling contact model,” in IEDM Tech. Dig., 1998,
pp. 733–736.
[46] J. Knoch and J. Appenzeller, “Impact of the channel thickness on
the performance of Schottky barrier metal-on-semiconductor field-effect
transistors,” Appl. Phys. Lett., vol. 81, no. 16, pp. 3082–3084, Oct. 2002.
[47] B. Winstead and U. Ravaioli, “Simulation of Schottky barrier MOSFETs
with a coupled quantum injection/Monte Carlo technique,” IEEE Trans.
Electron Devices, vol. 47, no. 6, pp. 1241–1246, Jun. 2000.
[48] International Technology Roadmap for Semiconductors 2004 Update.
Austin, TX: Semiconductor Industry Assoc., 2004.
[49] International Technology Roadmap for Semiconductors 2002 Update.
Austin, TX: Semiconductor Industry Assoc., 2002.
[50] International Technology Roadmap for Semiconductors 2000 Update.
Austin, TX: Semiconductor Industry Assoc., 2000.
[51] S. A. Rishton, K. Ismail, J. O. Chu, K. K. Chan, and K. Y. Lee,
“New complimentary metal-oxide semiconductor technology with selfaligned Schottky S/D and low-resistance T gates,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 15, no. 6, pp. 2795–2798,
Nov. 1997.
[52] K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, “Enhancement of hot-electron generation rate in Schottky source metal-oxidesemiconductor field-effect transistors,” Appl. Phys. Lett., vol. 76, no. 26,
pp. 3992–3994, Jun. 2000.
[53] M. Sugino, L. A. Akers, and M. E. Rebeschini, “Latchup-free Schottkybarrier CMOS,” IEEE Trans. Electron Devices, vol. ED-30, no. 2,
pp. 110–118, Feb. 1983.
[54] T. Iwamoto, T. Ogura, M. Terai, H. Watanebe, H. Watanabe, N. Ikarashi,
M. Miyamura, T. Tatsumi, M. Saitoh, and A. Morioka et al., “A highly
manufacturable low power high speed HfSiO CMOS FET with dual polySi gate electrodes,” in IEDM Tech. Dig., 2003, pp. 27.5.1–27.5.4.
[55] S. S. Mukherjee, J. Emer, and S. K. Reinhardt, “The soft error problem: An architectural perspective,” in Proc. 11th Int. Symp. HPCA-11,
2005, p. 5.
[56] C. Wang, J. P. Snyder, and J. R. Tucker, “Sub-40 nm PtSi Schottky
S/D metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett.,
vol. 74, no. 8, pp. 1174–1176, Feb. 1999.
[57] J. Kedzierski, M. Leong, P. Xuan, J. Bokor, T.-J. King, and C. Hu, “Design
analysis of thin-body silicide S/D devices,” in Proc. IEEE Int. SOI Conf.,
2001, pp. 21–22.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
[58] M. Tao, D. Udeshi, S. Agarwal, N. Basit, E. Maldonado, and W. P.
Kirk, “Low Schottky barrier on N-type Si for N-channel Schottky S/D
MOSFET’s,” in Mater. Res. Soc. Symp. Proc., 2003, pp. 297–302.
[59] D. Connelly, C. Faulkner, D. E. Grupp, and J. S. Harris, “A new route
to zero-barrier metal S/D MOSFETs,” IEEE Trans. Nanotechnol., vol. 3,
no. 1, pp. 98–104, Mar. 2004.
[60] J. Guo and M. Lundstrom, “A computational study of thin-body, doublegate, Schottky barrier MOSFETs,” IEEE Trans. Electron Devices, vol. 49,
no. 11, pp. 1897–1902, Nov. 2002.
[61] S. Xiong, T.-J. King, and J. Bokor, “A comparison study of symmetric
ultrathin-body double-gate devices with metal S/D and doped S/D,” IEEE
Trans. Electron Devices, vol. 52, no. 8, pp. 1859–1867, Aug. 2005.
[62] K. Ikeda, Y. Yamashita, A. Endoh, T. Fukano, K. Hikosaka, and
T. Mimura, “50-nm gate Schottky S/D p-MOSFETs with a SiGe
channel,” IEEE Electron Device Lett., vol. 23, no. 11, pp. 670–672,
Nov. 2002.
John M. Larson (M’02) received the B.A. degree
in mathematics and physics from St. Olaf College,
Northfield, MN, in 1995, and the Ph.D. degree in
mechanical engineering with an emphasis in plasma
technology from the University of Minnesota, Minneapolis, in 2000.
Since 2000, he has been with Spinnaker Semiconductor, Bloomington, MN, as a Principal Scientist, where he has focused on the development of
SB-CMOS process technology. His areas of interest
include integration of SB-CMOS technology in commercial production facilities, including the integration of platinum and erbium
silicides. He is the holder of three patents in these fields.
John P. Snyder (S’93–M’95) received the B.S.
degree in aerospace engineering from the Massachusetts Institute of Technology, Boston, in 1988,
and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in
1989, and 1996, respectively.
After working at National Semiconductor as a
Process Integration Engineer from 1996 to 1998, he
founded Spinnaker Semiconductor in Bloomington,
MN, for the purpose of commercializing Schottkybarrier (SB)-CMOS technology. He currently serves
as Chairman and CTO at Spinnaker. His research interests are in the development of a low-cost commercially manufacturable SB-CMOS technology, and in
the development of compact models required for the development of products
based on SB-CMOS technology. He is the holder of six patents in these areas.