Circuit Mismatch Influence on Performance of Paralleling Silicon Carbide
MOSFETs
Helong Li, Stig Munk-Nielsen, Cam Pham, Szymon Bęczkowski
Department of Energy Technology
Aalborg University
Aalborg, Denmark
E-Mail: {hel, smn, cph, sbe}@et.aau.dk
URL: http://www.iepe.et.aau.dk
Keywords
«Wide bandgap devices)», «Silicon Carbide (SiC)», «MOSFET», «Parallel operation»
Abstract
This paper focuses on circuit mismatch influence on performance of paralleling SiC MOSFETs. Power
circuit mismatch and gate driver mismatch influences are analyzed in detail. Simulation and
experiment results show the influence of circuit mismatch and verify the analysis. This paper aims to
give suggestions on paralleling discrete SiC MOSFETs and designing layout of power modules with
paralleled SiC MOSFETs dies.
Introduction
SiC devices have been undergoing a rapid growth over the last decade, thanks to its high breakdown
voltage, fast switching speed capability and good thermal conductivity. A wide spread use of SiC
devices can be envisaged in many application field, e.g. photovoltaic inverters (PV)[1-3], wind
turbines[4-6], variable speed drives[7, 8], and electric vehicles[9, 10]. Among SiC devices, SiC
MOSFETs are considered as a potential alternative of Si IGBT, whereas the current rating capability
of SiC MOSFET limits its application in high current and high power applications. To increase the
current rating of SiC MOSFETs, either building multichip power module or paralleling discrete SiC
MOSFETs, both of which require a fully understanding of the paralleling performance of SiC
MOSFETs. There are some reported research works about paralleling SiC MOSFETs, which focuses
on current unbalance by the device mismatch or reducing current unbalance by active control [11, 12].
Few research works about circuit mismatch impact on paralleling SiC MOSFETs are reported.
This paper focuses on circuit mismatch impact on paralleling SiC MOSFETs. First, the paralleling SiC
MOSFETs model is analyzed with an inductive clamped circuit. Circuit mismatch impact on the
performance of paralleling SiC MOSFETs is analyzed in detail, including power circuit mismatch and
gate driver circuit mismatch. Simulation results are shown and help to verify the analysis. According
to the analysis, hardware circuits with circuit mismatches are designed, including switching loop stray
inductance mismatch and common source stray inductance mismatch. The experiment results show the
circuit mismatch influence on the performance of paralleling SiC MOSFETs. Finally, paralleling SiC
MOSFETs circuit design suggestions and guidelines are given in the conclusion.
Paralleling SiC MOSFETs Circuit Model and Mismatches Impact
An inductive clamped circuit, as shown in Fig.1, is employed to evaluate the circuit mismatch impact
on performance of paralleling SiC MOSFETs. Paralleling circuit model with power parasitic
parameters (red color) is shown. Ld1 and Ld2 are switching loop stray inductance to SiC MOSFETs Q1
and Q2. Ls1 and Ls2 are the parasitic common source inductance. Cp is the sum of parasitic paralleling
capacitance of the load inductor and diode junction capacitance.
Fig. 1: Paralleling SiC MOSFETs model with power circuit parasitics
This paper mainly focuses on circuit mismatches between Ld1 and Ld2, Ls1 and Ls. Gate driver
mismatch is also analyzed and simulated. Fig.2 shows simulation waveforms without circuit
mismatches (Ld1=Ld2=100nH, Ls1=Ls2=5nH). Two SiC MOSFETs has no current unbalance and
voltage difference.
Fig. 2: Simulation results without circuit mismatch
Ld mismatch influence
As during switching transient, the SiC MOSFETs current (iD) is determined by gate source voltage
(VGS). And the final current value is determined by the load current. Therefore, Ld has little influence
on ID during switching transient, which can be verified by the simulation results in Fig.3 (Ld1=50nH,
Ld2 =150nH). However, Ld has an impact on the drain-source voltage (VDS). Because of Ld, VDS has a
dip during turn on and an overshoot during turn off. As shown in Fig.3, larger Ld causes larger VDS dip
and overshoot.
Fig. 3: Simulation results with Ld imbalance
During on state, it is always considered that the current is constant. However, there are many cases
that the SiC MOSFETs see an inductive load current and iD still changes. During on state period, the
equivalent power circuit is shown as Fig.4.
Fig. 4: On state equivalent circuit of paralleling two SiC MOSFETs
The current calculation is shown as (1). In condition of Ron1=Ron2 and diD1/dt=diD2/dt (determined by
load), the current difference of iD1 and iD2 can be determined as (2), which means different Ld lead to
different on state current. Larger Ld results smaller on state current. A simulation is made to verify the
above analysis. The only difference to the paralleled SiC MOSFETs is that Ld1=50nH and Ld2 =150nH.
L=800μH, uDC=600V, Ron=80mΩ. Fig.3 shows the simulation results. During on state period, there is a
small difference between these two MOSFETs current.
⎧
⎪iD1 + iD 2 = i
⎪⎪ di
⎨ L + uao = uDC
⎪ dt
diD 2
⎪ diD1
⎪⎩ L1 dt + Ron1iD1 = L2 dt + Ron 2iD 2
iD1 − iD2 ≈
L2 − L1 uDC
2 Ron
(1)
(2)
L
Ls mismatch influence
Ls has a large impact on the transient current sharing performance by its negative feedback effect to
the gate-source voltage, as calculated in (3). In saturation region, a linear transfer characteristic is
assumed as (4). With (3) and (4), the difference of iD could be roughly calculated as (5). Ls makes SiC
MOSFET turn on and turn off slow. Different Ls leads to different current rise time and fall time,
which results current unbalance during switching transient. Simulation results with different Ls are
shown in Fig.5, Ls1=5nH, Ls2=10nH.
di
uGS = udriver − iG RG − Ls s
(3)
dt
iD = g s (uGS − VT )
(4)
iD1 − iD 2 = g s ( Ls 2 − Ls1 )
di L
(5)
2dt
Fig. 5: Simulation results with Ls imbalance
Gate driver mismatch influence
Different gate drivers may have some delay between each other, which could lead to current unbalance
of paralleled SiC MOSFETs. The delay may come from gate driver propagation difference. During
saturation region, the gate charge effect could be treated as a RC circuit. According to (3) and (4), the
current difference could be as (6). Simulation results with a 5ns gate driver delay are shown in Fig.6.
iD1 − iD2 = gs ( e
−
t2
RC
−e
−
t1
RC
)
(6)
In real applications, it is strongly recommended that all paralleled SiC MOSFETs are driven by one
gate driver.
Fig. 6: Simulation results with gate driver imbalance
Hardware design and Experiment results
For the circuit mismatch research study, it is necessary to make sure that the paralleled MOSFETs do
not have large device parameters mismatches. Among device parameters, on-resistance Ron and
threshold voltage Vth have significant influence on the performance of paralleling SiC MOSFETs. 8
SiC MOSFETs are tested regarding Ron and Vth. The test results are shown in Fig.7. In this study, the
test condition is different from that in the datasheet. However, the purpose is to find two SiC
MOSFETs with close Ron and Vth. According to Fig.7, M1 and M4 have close Ron and Vth. Therefore,
M1 and M4 are chosen to study the circuit mismatch influence and are renamed as Q1 and Q2. The
hardware setup is shown in Fig.8.
0.2
VGS=20V
T=25°C
400
Id/mA
Ron/Ohm
0.25
500
M1
M2
M3
M4
M5
M6
M7
M8
300
200
M1
M2
M3
M4
M5
M6
M7
M8
VDS=2V
T=25°C
0.15
100
0.1
0
2
4
6
8
10
Id/A
(a)Ron
Fig. 7: SiC MOSFETs Ron and Vth testing results
0
0
1
2
3
4
5
6
VGS/V
(b)Vth
Fig. 8: Hardware setup
Experiment of Ld mismatch influence
The experiment results with different switching loop stray inductance are shown in Fig.9-11. Fig.9 and
Fig.10 show the transient current sharing performance and drain-source voltage comparison. Fig.11
shows the on state current sharing performance. According to Fig.9, with different Ld, two paralleled
SiC MOSFETs current does not have current mismatch during transient switching period. After turn
on and turn off, the SiC MOSFETs currents have different oscillations due to LC resonant. The SiC
MOSFET with larger Ld has larger amplitude current oscillations. Fig.10 shows the Ld mismatch
influence on drain-source voltage. During turn on, SiC MOSFET with larger Ld has more voltage dip
while during turn off has more voltage overshoot, which leads to larger voltage stress on the device.
Fig.11 shows the on state current sharing performance of paralleled SiC MOSFETs with different Ld.
SiC MOSFET with a larger Ld has a lower current than the other SiC MOSFETs.
The switching loss and voltage overshoot analysis is shown in Fig.12. It verifies the analysis in part II.
With larger Ld, the corresponding SiC MOSFET has smaller turn on loss but larger turn off loss.
Totally, SiC MOSFET with larger Ld has a smaller switching loss than that with smaller Ld. According
to Fig.12 (b), the SiC MOSFET suffers higher VDS overshoot with larger Ld.
20
10
Ld1=30nH
0
Ld2=30nH
50
100
150
Ld2=30nH
0
-10
0
200
30
30
20
20
10
Ld1=30nH
0
Ld2=96nH
-10
0
50
100
150
20
50
100
t/ns
150
200
50
100
150
200
L1=30nH
L2=170nH
10
0
Ld2=170nH
-10
0
200
0
20
0
150
L2=96nH
30
Ld1=30nH
100
L1=30nH
-10
0
200
50
10
30
10
Ld1=30nH
10
Current/A
Current/A
Current/A
20
-10
0
Current/A
Drain Current
30
Current/A
Current/A
Drain Current
30
-10
0
50
Fig. 9: Transient current sharing performance with different Ld
Drain Source Voltage
100
t/ns
150
200
Drain Source Voltage
600
Voltage/V
Voltage/V
800
L1=30nH
400
L2=30nH
200
0
0
800
600
400
Ld1=30nH
200
Ld2=30nH
0
50
100
150
200
0
50
100
150
200
600
Voltage/V
Voltage/V
800
L1=30nH
400
L2=96nH
200
0
0
800
600
400
Ld1=30nH
200
Ld2=96nH
0
50
100
150
200
0
50
100
150
200
600
L1=30nH
400
L2=170nH
200
0
0
50
100
t/ns
150
200
Fig. 10: Transient VDS performance with different Ld
Voltage/V
Voltage/V
800
800
600
400
Ld1=30nH
200
0
0
Ld2=170nH
50
100
t/ns
150
200
Drain Current
Current/A
20
L1=30nH
10
L2=30nH
0
0
2
4
6
8
10
Current/A
20
L1=30nH
10
L2=96nH
0
0
2
4
6
8
10
Current/A
20
L1=30nH
10
L2=170nH
0
0
2
4
6
8
10
t/us
Fig. 11: On state current sharing performance with different Ld
300
250
250
Voltage Overshoot/V
300
Loss/uJ
200
150
100
150
100
50
50
0
200
0
66
(Ld2-Ld1)/nH
140
0
0
50
100
Ld/nH
150
(a)Switching loss analysis
(b) VDS overshoot analysis
Fig. 12: Switching loss and voltage overshoot analysis with different Ld
Experiment of Ls mismatch influence
The study with different common source inductance is realized by connecting different source pin
length d1 for Q1 and d2 for Q2. Three different cases are tested, which are d1=d2=6mm, d1=6mm and
d2=10mm, d1=6mm and d2=16mm. The experiment results are shown in Fig.13. According to the
experiment results of case d1=d2=6mm, it can also be seen that the device parameters have very small
mismatch in Ron and Vth. The switching loss analysis and current overshoot analysis is shown in Fig.14
(a) and Fig.14 (b).
According to Fig.13, Ls mismatch leads to current mismatch both in turn on and turn off transient.
During turn on transient, SiC MOSFET Q2 with larger Ls turns on slower as the negative feedback
effect of Ls. As the total current is determined by the circuit parameters and is fixed, the other SiC
MOSFET Q1 switches faster and takes a higher current during turn on. During turn off, Q2 takes more
current and turns off slower while Q1 takes smaller current and turns off faster. As a result of that, with
the increase of Ls difference, Q2 turn on loss decreases and turn off loss increases while Q1 turn on loss
increases and turn off loss decreases, as shown in Fig.14 (a). Q2 has a smaller switching loss than Q1.
With the increase of Ls difference, the switching loss difference increases. The total switching loss
keeps in a similar level. According to Fig.14 (b), the current overshoot of Q1 increases with the Ls
difference increases. The SiC MOSFET with smaller Ls suffers more current stress.
Drain Current
20
20
10
d1=6mm
0
d2=6mm
50
100
150
-10
0
200
30
20
20
d1=6mm
0
50
100
150
30
20
20
d1=6mm
0
50
100
t/ns
150
200
200
d2=10mm
50
100
150
200
d1=6mm
d2=16mm
10
0
d2=16mm
-10
0
150
d1=6mm
-10
0
200
100
0
30
10
50
10
d2=10mm
-10
0
d2=6mm
0
30
10
d1=6mm
10
Current/A
Current/A
-10
0
Current/A
Current/A
30
Current/A
Current/A
Drain Current
30
-10
0
50
Fig. 13: Experiment results with different common source inductance
100
t/ns
150
200
350
10
Current Overshoot/A
300
Loss/uJ
250
200
150
100
6
4
2
50
0
-2
8
0
2
4
6
(d2-d1)/mm
8
10
12
(a)Switching loss analysis
Fig. 14: Switching loss and current overshoot analysis
0
0
2
4
6
(d2-d1)/mm
8
10
(b) iD overshoot analysis
Conclusion
Performance of paralleling SiC MOSFETs under circuit mismatch is analyzed and evaluated in this
paper. With the simulation and experiment results, the analysis is verified. Switching loop stray
inductance Ld mismatch has an impact on drain source voltage VDS during switching transient, which
leads to switching loss mismatch. The SiC MOSFET with larger Ld suffers higher voltage stress.
Besides that, mismatch of Ld also influence the on state current sharing in case the load current still
changes during on state. Common source inductance Ls mismatch has a big influence on the gatesource voltage, which affects the switching transient current sharing performance of SiC MOSFETs.
For the paralleled MOSFETs, larger Ls results slower turn on and turn off process, which leads to
smaller turn on loss and higher turn off loss. The SiC MOSFET with smaller Ls suffers higher current
overshoot during turn on. One gate driver for the paralleled SiC MOSFETs is recommended, since
gate driver delay could result current imbalance and oscillations. With the fully understanding of
circuit imbalance impacts on performance of paralleling SiC MOSFETs, this paper could help to
design the circuit of paralleling discrete SiC MOSFETs and design the layout of power module with
paralleled SiC MOSFET dies.
References
[1]B. Burger and D. Kranzer, "Extreme high efficiency PV-power converters," in IEEE 2009 European
Conference on Power Electronics and Applications, 2009, pp. 1-13.
[2]T. Fujihira, A. Otsuki, Y. Takahashi, T. Ide, M. Kawano and N. Eguchi, "Latest power devices for
photovoltaic inverters," in IEEE International Symposium on Industrial Electronics, 2012, pp. 1791-1794.
[3]O. Mostaghimi, N. Wright and A. Horsfall, "Design and performance evaluation of SiC based DC-DC
converters for PV applications," in IEEE 2012 Energy Conversion Congress and Exposition, 2012, pp.39563963.
[4] M. Adamowicz, S. Giziewski, J. Pietryka, M. Rutkowski and Z. Krzeminski, "Evaluation of SiC JFETs and
SiC schottky diodes for wind generation systems," in IEEE 2011 International Symposium on Industrial
Electronics, 2011, pp. 269-276.
[5] R. A. Friedemann, F. Krismer and J. W. Kolar, "Design of a minimum weight dual active bridge converter
for an airborne wind turbine system," in IEEE 2012 Applied Power Electronics Conference and Exposition,
2012, pp. 509-516.
[6] S. V. Araujo and P. Zacharias, "Perspectives of high-voltage SiC-semiconductors in high power conversion
systems for wind and photovoltaic sources," in IEEE 2011 European Conference on Power Electronics and
Applications, 2011, pp. 1-10.
[7]Xun Gong, J. A. Ferreira and J. Popovic-Gerber, "Comparison and suppression of conducted EMI in SiC
JFET and si IGBT based motor drives," in 2012 Power Electronics and Motion Control Conference, 2012, pp.
DS2c.8-1-DS2c.8-8.
[8] T. Zhao, J. Wang, A. Q. Huang and A. Agarwal, "Comparisons of SiC MOSFET and si IGBT based motor
drive systems," in IEEE 2007 Industry Applications Conference, 2007, pp. 331-335.
[9] A. Antonopoulos, H. Bangtsson, M. Alakula and S. Manias, "Introducing a silicon carbide inverter for hybrid
electric vehicles," in IEEE 2008 Power Electronics Specialists Conference, 2008, pp. 1321-1325.
[10] Hui Zhang, L. M. Tolbert and B. Ozpineci, "Impact of SiC Devices on Hybrid Electric and Plug-In Hybrid
Electric Vehicles," IEEE Transactions on Industry Applications, vol. 47, no. 2, pp. 912-921, March-April 2011.
[11] Xue Yang, Lu Junjie, Wang Zhiqiang, Tolbert, Leon M, Blalock, Benjamin J, Wang, Fred, "Active Current
Balancing for Parallel-Connected Silicon Carbide MOSFETs," in IEEE 2013 Energy Conversion Congress and
Exposition, 2013, pp.1563-1569.
[12] S. Diane-Perle, C. Juan, N. Hans-Peter, "Experimental investigations of static and transient current sharing
of parallel-connected silicon carbide MOSFETs," 15th European Conference on Power Electronics and
Applications(EPE), 2013,pp.1-10.