KL UNIVERISTY
FIRST SEMESTER 2010-11
Course Handout
Academic Division
Dated: 07-07-2010
Course No.
Course Title
Course Structure
Course coordinator
Instructors
: EM C205
: Computer Organization
: 3-0-0
: Manoj Kumar Tyagi
: M.Venkatewara Rao
1. Course Description:
This course provides basic Knowledge necessary to understand the hardware
operation of digital computers and covers the three subjects associated with
computer hardware. It describes Physical organization of a particular computer
including its registers,dataflow,Micro operations and control Function by means of a
hardware description language.
2. Scope and Objective of the Course:
This subject deals with computer architecture as well as computer organization and
design. computer architecture is concerned with the structure and behaviour of the
various functional modules of the computer and how they interact to provide
processing needs of the user. computer organization is concerned with the way the
hardware the components are connected together to form a computer system.
computer design is concerned with the development of the hardware for the
computer taking in to consideration a given set of specification.
3. Books:
(i) Textbook:
a. 1.Morris
M.Mano,”Computer Systems Arichitecture”,3rd Edition,
Prentice Hall of India, New Delhi, 1993.
(ii) Reference Book:
a. John P Hayes,” Computer Arichitecture and Organization”, 3rd
Edition,Mc- Graw Hill,1997,New York,N.Y.,U.S.A.
b. V.Carl Hamacher et.al,”Computer Organization” 5th Edition,McGrawHill,New York,2001,N.Y.,U.S.A.
c. Raja Raman and Radha Krishna,” Computer architecture and
organization”-PHI,2006,New Delhi
4. Syllabus:
UNIT I:
REGISTER TRANSFER & MICRO-OPERATIONS: Register Transfer Language,
Register Transfer, Bus&memory Transfers, Arthmetic Micro-operations, Logic Micro
Operations, Shift Micro-operation, Arithmetic Logic Shift Unit.
UNIT II:
BASIC COMPUTER ORGANISATION AND DESIGN: introduction codes, Computer
Registers, Computer instructions, Timing and Control, Instruction Cycle, MemoryReference
Instruction, Input-Output and interrupt, Design of Basic Computer, Design of
accumulator
1
Logic, MICRO PROGRAMMED CONTROL: Control Memory, Address Sequencing,
Micro-Program example, Design of Control Unit.
UNIT III:
CENTRAL PROCESSING UNIT: General registers Organization, Stack
Organization, Instruction Formats, Addressing Modes, Data Transfer and
Manipulation,
Program Control, Reducted instruction Set Computer (RISC).COMPUTER
ARITHMETIC: Addition and Subtraction, Multiplication Algorithms, Division
Algorithms Floating-point Arithmetic Operations.
UNIT IV:
MEMORY ORGANIZATION: Memory Hierachy,Main Memory, Auxiliary memory,
Associative Men Cache Memory, Virtual Memory, Memory Management
hardware.
UNIT V:
INPUT-OUTPUT ORGANISATION: Peripheral Devices, input-Output interface,
Asynchronous Data Tranfer, Modes of Transfer, Priority interrupt, Direct Memory
Access (DMA), input –output Processor, serial Communication
5.Course Plan:
Course plan is meant as a guideline. There may probably be changes.
Lecture
No.
1
Learning
Topics to be covered
Objectives
Register transfer Register transfer language
language
Register transfer . Register transfer,Control Transfer.
2
4
Bus and memory
transfers
Arithmetic micro
operations
5
Logic
micro
operations
3
6
Reference
s
T1
p. 93
T1
p.95
Three state Bus Buffers,Memory T1
transfer
p.97
Binary
Adder,
Binary
Adder- T1
Subtractor,Binary
p.102
incrementer,Arithemetic Circuit.
List of Logic micro operations. T1
Hardware
Implementation
,Some p.108
applications
Hardware Implementation
T1
p.114
Arithmetic Logic Shift Unit
T1
p.116
7
Shift micro
operations
Arithmetic Logic
Shift Unit
8
Instruction codes
Stored program Organization,Indirect T1 p.125
Address
9
Computer
Registers,Compu
ter Instructions
Timing
&Control,Instructi
on cycle
CommonBus
completeness
10
System,Instructionset T1
p.129-136
Fetch & Decode,determine the type of T1
Instruction,Register
Reference p.137-145
Instruction
2
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Memory
AND to AC,ADD to AC,
reference
LDA:Load to AC,STA,BUN,BSA,ISZ.
Instruction
Input-Output and I/O
Configuration,I/O
Interrupt
Instructions,Program
Interrupt,Interrupt cycle.
Design of Basic Control
Logic
gates,control
of
Computer
registers and memory,control of single
fipflop,control of common bus.
Design
of Control of AC register,adder and logic
accumulator logic circuit
Control Memory
Control Memory
T1
P147
T1
p.152
T1
p.159
T1
p.166
T1
p.215
Addressing
Conditional Branching,mapping of T1
Sequencing
instructions,sub Routines
p.218
Micro
Program Computer
configuration,Micro T1p.222
Example
instruction format,Symbolic micro
instruction,the fetch routine,binary
micri program
Design of Control Micro program Sequencer.
T1
Unit
p.233
General Register Control Word,Examples of micro
T1
Organization
operations
p.244
Stack
Register stack,memory stack,reverse
T1
Organization
polish notation,Evalution of arithemetic p.249
expression.
Instruction
Three- address,two address,one
T1
Format
address,zero address RISC
p.257
instructions.
Addressing
Immediate ,Register,Register
T1
Modes
indirect,implied,Auto
p.262
Increment&decrement,direct,indirect,r
elative,indexed addressing modes
Data Transfer
Data Trasfer&Manipulation
T1
manipulation
instructions arithmetic instruction
p.268
logical and bit manipulation instruction
Program Control Status bit conditions,conditional
T1
branch instructions subroutine call and p.275
return,program interrupt,types of
interrupts.
Reduced
CISC Characterstics,Risc
T1
Instruction Set
Characterstics
p.284
Computer(RISC)
Arithmetic
Additiona Subraction with signed
T1
addition
magnitude data&with signed two,s
P.336
&Subtraction
complement data,Hardware
Algorithm
implementation.
Multiplication
Signed Magnitude data,Hardware
T1
Algorithms
implementation,booth Multiplication
p.342
algorithm,arry multiplier.
Division
Hardware implementation for signed
T1
Algorithms
magnitude data,Devide
p.350
overflow,Hardware algorithm
3
29
30
31
Floating Point
Arithmetic
Operation
Floating Point
Arithmetic
Operation
Memory
hierarchy
Main Memory
32
Auxiliary Memory
Basic Conditions,Register
configuration,addition and subtraction.
T1
p.356
Multiplication&division
T1
p.356
Auxiliary Memory, cache
memory,multiprogramming,
T1
p.445
RAM and ROM Chips,Memory
Address Map,Memory connection
CPU.
Magnetic disk,Magnetic tape
T1
33
34
Associative and
cache Memory
Associative Mapping ,direct,setAssociatives Mapping,writing into
cache ,cache initialization
Virtual Memory
Address space and Memory Space
Address mapping using pages,page
Replacemant
Segmented page Mapping,Memory
Protection
35
36
37
38
Memory
Management
Hardware
Peripheral
Devices
Input-Output
Interface
39
Asynchronous
data transfer
40
Modes of
Transfer
Priority Interrupt
41
42
43
44
45
Direct Memory
Access
Input-Output
Processor
Input-Output
Processor
Serial
Communication
Peripheral.Monitor and
keyboard,printer,Magnetic
tape,Magnatic Disk.
I/O Bus and interface Module,I/O
versus memory buses,isolated versus
Memory mapped I/O.
Strobe control ,Hand
shaking.Asynchronous serial transfer,
Asynchronous communication
interface,FIFO Buffer.
Programmed I/O, Interrupt initiated I/O
Daisy chining priority,parallel priority
interrupt,Priority encoder,interrupt
cycle.
DMA Controller,DMA Transfer
CPU-IOP Communication
Intel 8089 IOP
Character oriented protocol ,Data
Transperency, Bit oriented Protocol
4
p.448
T1
p.454
T1
p.458-471
T1
p.471
T1
p.478
T1
p.383
T1
p.387
T1 p.393
T1
p.402
T1
p.409
T1
p.417
T1
p.422
T1
p.422
T1
p.431
6.Self learning material:
Unit
I
II
III
Topic
Binary adder subtractor
Source
Morris M.Mano,”Computer Systems
Arichitecture”,3rd Edition
Adder and logic circuit
Morris M.Mano,” Computer
Systems Arichitecture”,3rd Edition.
V.Carl Hamacher et.al,”Computer
Organization”2nd Edition
Computer Oraganization by William
Stallings
Morris M.Mano,” Computer
Systems Arichitecture”,3rd Edition
Computer
architecture
and
organization by Raja Raman and
Radha Krishna-PHI
V
Data manipulation
instructions
RISC
V
Numerical Example
V
CPU-IOP
communication
7.Evaluation Scheme:
Duration
Component
(minutes)
Test-1
50 Min
% Weightage
Marks
10
10
Test-2
10
50 Min
Assignement
submission
Assignment Test
10
5
5
30 Min
5
Continuous
0
3 Hrs
0
3 Hrs
60
Quiz
5
Regular Lab Evaluation
Comprehensive Lab
Exam
Comprehensive Exam
Attendance for Theory
& Tutorial
Attendance for Lab
Venue
11-08-2010
9.20 to 10.20
A.M
15-09-2010
9.20 to 10.20
A.M
CSE103,202,
209,309
27-10-2010
9.00 to 10.20
A.M
27-10-2010
9.00 to 10.20
A.M
CSE103,202,
209,309
CSE103,202,
209,309
5
5
50 Min
Date & Time
0
0
60
5
5
0
0
Continuous
Continuous
8. Chamber consultation hour: Informed in the class in first week.
9. Notices: All notices regarding the course will be put in E-learning website
5
CSE103,202,
209,309
Course Coordinator
6