Semiconductor manufacturing - in no particular order

in no particular order
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Chemical vapor deposition
Semiconductor device fabrication
Chemical- mechanical planarization
Physical vapor deposition
Atomic layer deposition
Molecular beam epitaxy
Czochralski process
Plasma ashing
Rapid thermal processing
Furnace anneal
Ion implantation
Etching (microfabrication)
Dry etching
Thermal oxidation
Wafer testing
Wafer prober
Non- contact wafer testing
Die preparation
Integrated circuit packaging
Die attachment
Wire bonding
Flip chip
Quilt packaging
Integrated circuit encapsulation
Semiconductor fabrication plant
Lights out (manufacturing)
Foundry model
Advanced Silicon Etch
Buffered oxide etch
Deep reactive- ion etching
Reactive- ion etching
B- staging
Ball bonding
Barrier metal
Borophosphosilicate glass
Capacitance voltage profiling
Channel- stopper
Alfred Y. Cho
Coining, Inc.
Dark current spectroscopy
Deal- Grove model
Device under test
Doping (semiconductor)
Electron beam induced current
Evaporation (deposition)
Fabless semiconductor company
Focused ion beam
Gas immersion laser doping
Gate count
Health hazards in semiconductor manufacturing occupations
Integrated device manufacturer
Ion Beam Mixing
Ion beam
Ion beam lithography
Laser trimming
Lift- off (microtechnology)
Low temperature co- fired ceramic
Metal- induced crystallization
Metalorganic chemical vapor deposition
Multi- project wafer service
Negative bias temperature instability
Ohmic contact
Overlay Control
Package on package
Phenol formaldehyde resin
Phosphosilicate glass
Planar process
Plasma cleaning
Plasma etcher
Plasma etching
Plasma- immersion ion implantation
Process design kit
Product engineering
Pulsed laser deposition
RCA clean
Reliability (semiconductor)
Rigid needle adapter
Semiconductor Equipment and Materials International
Semiconductor industry
Shallow trench isolation
Silicate glass
Silicon on sapphire
Smart Cut
Spin coating
Spreading Resistance Profiling
Sputter deposition
Substrate mapping
Three- dimensional integrated circuit
Through- silicon via
Titanium nitride
Vapour phase decomposition
Wafer (electronics)
Wafer dicing
Wafer fabrication
Wafer- scale integration
Article Sources and Contributors
Image Sources, Licenses and Contributors
Article Licenses
Chemical vapor deposition
Chemical vapor deposition
Chemical vapor deposition (CVD) is a chemical
high-performance solid materials. The process is
often used in the → semiconductor industry to
produce thin films. In a typical CVD process, the →
wafer (substrate) is exposed to one or more volatile
precursors, which react and/or decompose on the
substrate surface to produce the desired deposit.
Frequently, volatile by-products are also produced,
which are removed by gas flow through the reaction
→ Microfabrication processes widely use CVD to
deposit materials in various forms, including:
monocrystalline, polycrystalline, amorphous, and →
epitaxial. These materials include: silicon, carbon
nanotubes, SiO2, silicon-germanium, tungsten,
silicon carbide, silicon nitride, silicon oxynitride, →
titanium nitride, and various high-k dielectrics. The
CVD process is also used to produce synthetic
DC plasma (violet) enhances the growth of
carbon nanotubes in this laboratory-scale
PECVD apparatus.
Types of chemical vapor deposition
A number of forms of CVD are in wide use and are
frequently referenced in the literature. These
processes differ in the means by which chemical
reactions are initiated (e.g., activation process) and
process conditions.
• Classified by operating pressure
hot-wall thermal CVD (batch operation
• Atmospheric pressure CVD (APCVD) - CVD
processes at atmospheric pressure.
• Low-pressure CVD (LPCVD) - CVD processes at
subatmospheric pressures[1] . Reduced
pressures tend to reduce unwanted gas-phase
reactions and improve film uniformity across
the wafer. Most modern CVD process are either
plasma assisted CVD
• Ultrahigh vacuum CVD (UHVCVD) - CVD processes at a very low pressure, typically
below 10-6 Pa (~ 10-8 torr). Caution: in other fields, a lower division between high and
ultra-high vacuum is common, often 10-7 Pa.
• Classified by physical characteristics of vapor
Chemical vapor deposition
• Aerosol assisted CVD (AACVD) - A CVD process in which the precursors are
transported to the substrate by means of a liquid/gas aerosol, which can be generated
ultrasonically. This technique is suitable for use with non-volatile precursors.
• Direct liquid injection CVD (DLICVD) - A CVD process in which the precursors are in
liquid form (liquid or solid dissolved in a convenient solvent). Liquid solutions are
injected in a vaporization chamber towards injectors (typically car injectors). Then the
precursor vapors are transported to the substrate as in classical CVD process. This
technique is suitable for use on liquid or solid precursors. High growth rates can be
reached using this technique.
• Plasma methods (see also Plasma processing)
• Microwave plasma-assisted CVD (MPCVD)
• Plasma-Enhanced CVD (PECVD) - CVD processes that utilize plasma to enhance
chemical reaction rates of the precursors[2] . PECVD processing allows deposition at
lower temperatures, which is often critical in the manufacture of semiconductors.
• Remote plasma-enhanced CVD (RPECVD) - Similar to PECVD except that the wafer
substrate is not directly in the plasma discharge region. Removing the wafer from the
plasma region allows processing temperatures down to room temperature.
• Atomic layer CVD (ALCVD) – Deposits successive layers of different substances to
produce layered, crystalline films. See Atomic layer epitaxy.
• Hot wire CVD (HWCVD) - also known as catalytic CVD (Cat-CVD) or hot filament CVD
(HFCVD). Uses a hot filament to chemically decompose the source gases.[3]
• → Metalorganic chemical vapor deposition (MOCVD) - CVD processes based on
metalorganic precursors.
• Hybrid Physical-Chemical Vapor Deposition (HPCVD) - Vapor deposition processes that
involve both chemical decomposition of precursor gas and vaporization of solid a source.
• Rapid thermal CVD (RTCVD) - CVD processes that use heating lamps or other methods to
rapidly heat the → wafer substrate. Heating only the substrate rather than the gas or
chamber walls helps reduce unwanted gas phase reactions that can lead to particle
• Vapor phase → epitaxy (VPE)
Substances commonly deposited for ICs
This section discusses the CVD processes often used for integrated circuits (ICs). Particular
materials are deposited best under particular conditions.
Polycrystalline silicon is deposited from silane (SiH4), using the following reaction:
SiH4 → Si + 2H2
This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or a
solution of silane with 70-80% nitrogen. Temperatures between 600 and 650 °C and
pressures between 25 and 150 Pa yield a growth rate between 10 and 20 nm per minute.
An alternative process uses a hydrogen-based solution. The hydrogen reduces the growth
rate, but the temperature is raised to 850 or even 1050 °C to compensate.
Polysilicon may be grown directly with doping, if gases such as phosphine, arsine or
diborane are added to the CVD chamber. Diborane increases the growth rate, but arsine
and phosphine decrease it.
Chemical vapor deposition
Silicon dioxide
Silicon dioxide (usually called simply "oxide" in the semiconductor industry) may be
deposited by several different processes. Common source gases include silane and oxygen,
dichlorosilane (SiCl2H2) and nitrous oxide (N2O), or tetraethylorthosilicate (TEOS;
Si(OC2H5)4). The reactions are as follows:
SiH4 + O2 → SiO2 + 2H2
SiCl2H2 + 2N2O → SiO2 + 2N2 + 2HCl
Si(OC2H5)4 → SiO2 + byproducts
The choice of source gas depends on the thermal stability of the substrate; for instance,
aluminium is sensitive to high temperature. Silane deposits between 300 and 500 °C,
dichlorosilane at around 900 °C, and TEOS between 650 and 750 °C, resulting in a layer of
Low Temperature Oxide (LTO). However, silane produces a lower-quality oxide than the
other methods (lower dielectric strength, for instance), and it deposits nonconformally. Any
of these reactions may be used in LPCVD, but the silane reaction is also done in APCVD.
CVD oxide invariably has lower quality than → thermal oxide, but thermal oxidation can
only be used in the earliest stages of IC manufacturing.
Oxide may also be grown with impurities (alloying or "→ doping"). This may have two
purposes. During further process steps that occur at high temperature, the impurities may
diffuse from the oxide into adjacent layers (most notably silicon) and dope them. Oxides
containing 5% to 15% impurities by mass are often used for this purpose. In addition,
silicon dioxide alloyed with phosphorus pentoxide ("P-glass") can be used to smooth out
uneven surfaces. P-glass softens and reflows at temperatures above 1000 °C. This process
requires a phosphorus concentration of at least 6%, but concentrations above 8% can
corrode aluminium. Phosphorus is deposited from phosphine gas and oxygen:
4PH3 + 5O2 → 2P2O5 + 6H2
Glasses containing both boron and phosphorus (borophosphosilicate glass, BPSG) undergo
viscous flow at lower temperatures; around 850 °C is achievable with glasses containing
around 5 weight % of both constituents, but stability in air can be difficult to achieve.
Phosphorus oxide in high concentrations interacts with ambient moisture to produce
phosphoric acid. Crystals of BPO4 can also precipitate from the flowing glass on cooling;
these crystals are not readily etched in the standard reactive plasmas used to pattern
oxides, and will result in circuit defects in integrated circuit manufacturing.
Besides these intentional impurities, CVD oxide may contain byproducts of the deposition
process. TEOS produces a relatively pure oxide, whereas silane introduces hydrogen
impurities, and dichlorosilane introduces chlorine.
Lower temperature deposition of silicon dioxide and doped glasses from TEOS using ozone
rather than oxygen has also been explored (350 to 500 °C). Ozone glasses have excellent
conformality but tend to be hygroscopic -- that is, they absorb water from the air due to the
incorporation of silanol (Si-OH) in the glass. Infrared spectroscopy and mechanical strain as
a function of temperature are valuable diagnostic tools for diagnosing such problems.
Chemical vapor deposition
Silicon nitride
Silicon nitride is often used as an insulator and chemical barrier in manufacturing ICs. The
following two reactions deposit nitride from the gas phase:
3SiH4 + 4NH3 → Si3N4 + 12H2
3SiCl2H2 + 4NH3 → Si3N4 + 6HCl + 6H2
Silicon nitride deposited by LPCVD contains up to 8% hydrogen. It also experiences strong
tensile stress, which may crack films thicker than 200 nm. However, it has higher resistivity
and dielectric strength than most insulators commonly available in microfabrication (1016
Ω·cm and 10 MV/cm, respectively).
Another two reactions may be used in plasma to deposit SiNH:
2SiH4 + N2 → 2SiNH + 3H2
SiH4 + NH3 → SiNH + 3H2
These films have much less tensile stress, but worse electrical properties (resistivity 106 to
1015 Ω·cm, and dielectric strength 1 to 5 MV/cm).[4]
Some metals (notably aluminium and copper) are seldom or never deposited by CVD. As of
2002[5], a commercially, cost effective, viable CVD process for copper did not exist- though
many people have used Copper Formate, Copper(hfac)2, and other precursors(Cu(II) ethyl
acetoacetate, etc...). Copper deposition of the metal has been done mostly by electroplating
due to cost. Aluminum can be deposited from tri-isobutyl aluminium (TIBAL), or Tri-ethyl
Aluminum (TEA), but → physical vapor deposition methods are usually preferred.
However, CVD processes for molybdenum, tantalum, titanium, nickel, and tungsten are
widely used. These metals can form useful silicides when deposited onto silicon. Mo, Ta and
Ti are deposited by LPCVD, from their pentachlorides. Nickel, Molybdenum, and Tungsten
can be deposited at low temperatures from their carbonyl precursors. In general, for an
arbitrary metal M, the reaction is as follows:
2MCl + 5H → 2M + 10HCl
The usual source for tungsten is tungsten hexafluoride, which may be deposited in two
WF6 → W + 3F2
WF6 + 3H2 → W + 6HF
See also
• → Atomic layer deposition, a more precise and conformal coating technology
• Hot-wire
• Ion plating, a process that may use chemical vapor precursors
• → Physical vapor deposition, the deposition of materials from vapor without chemical
• Plasma-enhanced chemical vapor deposition
Chemical vapor deposition
[1] Low Pressure Chemical Vapor Deposition - Technology and Equipment (http:/ / www. crystec. com/ klllpcvde.
[2] Plasma Enhanced Chemical Vapor Deposition - Technology and Equipment (http:/ / www. crystec. com/
tridepe. htm),
[3] Schropp, R.E.I.; B. Stannowski, A.M. Brockhoff, P.A.T.T. van Veenendaal and J.K. Rath. " Hot wire CVD of
heterogeneous and polycrystalline silicon semiconducting thin films for application in thin film transistors and
solar cells (http:/ / www. ipme. ru/ e-journals/ MPM/ no_2100/ schropp/ schropp. pdf)" (PDF). Materials Physics
and Mechanics. pp. 73–82.
[4] S.M.Sze (2008). Semiconductor devices: physics and technology. Wiley-India. p. 384. ISBN 812651681X.
[5] http:/ / en. wikipedia. org/ wiki/ Chemical_vapor_deposition
• Jaeger, Richard C. (2002). "Film Deposition". Introduction to Microelectronic Fabrication.
Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.
• Smith, Donald (1995). Thin-Film Deposition: Principles and Practice. MacGraw-Hill.
• Dobkin and Zuraw (2003). Principles of Chemical Vapor Deposition. Kluwer.
• ISO 3529/1-1981 Vacuum Technology - Vocabulary - part 1: General terms As quoted by
UK National Physical Laboratory (http:/ / www. npl. co. uk/ pressure/ faqs/ glossary. html)
External links
• Fundamental of Chemical Vapor Deposition (http:/ / www. timedomaincvd. com/
CVD_Fundamentals/ Fundamentals_of_CVD. html), by TimeDomain CVD, Inc.
Semiconductor device fabrication
Semiconductor device fabrication
is the process used to create chips,
the integrated circuits that are
present in everyday electrical and
electronic devices. It is a multiple-step
chemical processing steps during
which electronic circuits are gradually
created on a → wafer made of pure
semiconducting material. Silicon is
semiconductor material today, along
NASA's Glenn Research Center → cleanroom.
The entire manufacturing process
from start to packaged chips ready for shipment takes six to eight weeks and is performed
in highly specialized facilities referred to as fabs.
Semiconductor device fabrication
A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline
cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the
→ Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and
polished to obtain a very regular and flat surface.
Once the wafers are prepared, many process steps are necessary to produce the desired
semiconductor integrated circuit. In general, the steps can be grouped into two areas:[1]
• Front-end processing
• Back-end processing
In semiconductor device fabrication, the various processing steps fall into four general
categories: deposition, removal, patterning, and modification of electrical properties.
• Deposition is any process that grows, coats, or otherwise transfers a material onto the
wafer. Available technologies consist of → physical vapor deposition (PVD), → chemical
vapor deposition (CVD), electrochemical deposition (ECD), → molecular beam epitaxy
(MBE) and more recently, → atomic layer deposition (ALD) among others.
• Removal processes are any that remove material from the wafer either in bulk or
selectively and consist primarily of etch processes, either wet etching or → dry etching. →
Chemical-mechanical planarization (CMP) is also a removal process used between levels.
• Patterning covers the series of processes that shape or alter the existing shape of the
deposited materials and is generally referred to as lithography. For example, in
conventional lithography, the wafer is coated with a chemical called a “photoresist”. The
photoresist is exposed by a “stepper”, a machine that focuses, aligns, and moves the
mask, exposing select portions of the wafer to short wavelength light. The unexposed
regions are washed away by a developer solution. After etching or other processing, the
remaining photoresist is removed by → plasma ashing.
• Modification of electrical properties has historically consisted of doping transistor
sources and drains originally by diffusion furnaces and later by → ion implantation. These
doping processes are followed by → furnace anneal or in advanced devices, by rapid
thermal anneal (RTA) which serve to activate the implanted dopants. Modification of
electrical properties now also extends to reduction of dielectric constant in low-k
insulating materials via exposure to ultraviolet light in UV processing (UVP).
Many modern chips have eight or more levels produced in over 300 sequenced processing
Front-end processing
"Front-end processing" refers to the formation of the transistors directly on the silicon. The
raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer
through → epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step,
tricks are performed to improve the performance of the transistors to be built. One method
involves introducing a "straining step" wherein a silicon variant such as
"silicon-germanium" (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal
lattice becomes stretched somewhat, resulting in improved electronic mobility. Another
method, called "silicon on insulator" technology involves the insertion of an insulating layer
Semiconductor device fabrication
between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method
results in the creation of transistors with reduced parasitic effects.
Silicon dioxide
Front-end surface engineering is followed by: growth of the gate dielectric, traditionally
silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions,
and subsequent implantation or diffusion of dopants to obtain the desired complementary
electrical properties. In memory devices, storage cells, conventionally capacitors, are also
fabricated at this time, either into the silicon surface or stacked above the transistor.
Metal layers
Once the various semiconductor devices have been created they must be interconnected to
form the desired electrical circuits. This "back end of line" (BEOL – the latter portion of the
wafer fabrication, not to be confused with "back end" of chip fabrication which refers to the
package and test stages) involves creating metal interconnecting wires that are isolated by
insulating dielectrics. The insulating material was traditionally a form of SiO2 or a → silicate
glass, but recently new low dielectric constant materials are being used. These dielectrics
presently take the form of SiOC and have dielectric constants around 2.7 (compared to 3.9
for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.
Historically, the metal wires
consisted of aluminum. In this
approach to wiring often
called "subtractive aluminum",
blanket films of aluminum are
deposited first, patterned, and
then etched, leaving isolated
wires. Dielectric material is
exposed wires. The various
holes, called "vias," in the
depositing tungsten in them
Synthetic detail of a standard cell through four layers of planarized
copper interconnect, down to the polysilicon (pink), wells (greyish)
with a → CVD technique. This
and substrate (green).
approach is still used in the
fabrication of many memory
chips such as dynamic random access memory (DRAM) as the number of interconnect
levels is small, currently no more than four.
More recently, as the number of interconnect levels for logic has substantially increased
due to the large number of transistors that are now interconnected in a modern
microprocessor, the timing delay in the wiring has become significant prompting a change
in wiring material from aluminum to copper and from the silicon dioxides to newer low-K
material. This performance enhancement also comes at a reduced cost via damascene
Semiconductor device fabrication
processing that eliminates processing steps. In damascene processing, in contrast to
subtractive aluminum technology, the dielectric material is deposited first as a blanket film,
and is patterned and etched leaving holes or trenches. In "single damascene" processing,
copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting
in filled vias or wire "lines" respectively. In "dual damascene" technology, both the trench
and via are fabricated before the deposition of copper resulting in formation of both the via
and line simultaneously, further reducing the number of processing steps. The thin barrier
film, called copper barrier seed (CBS), is necessary to prevent copper diffusion into the
dielectric. The ideal barrier film is as thin as possible. As the presence of excessive barrier
film competes with the available copper wire cross section, formation of the thinnest
continuous barrier represents one of the greatest ongoing challenges in copper processing
As the number of interconnect levels increases, planarization of the previous layers is
required to ensure a flat surface prior to subsequent lithography. Without it, the levels
would become increasingly crooked and extend outside the depth of focus of available
lithography, interfering with the ability to pattern. CMP (chemical mechanical
planarization) is the primary processing method to achieve such planarization although dry
"etch back" is still sometimes employed if the number of interconnect levels is no more than
Wafer test
The highly serialized nature of wafer processing has increased the demand for metrology in
between the various processing steps. Wafer test metrology equipment is used to verify
that the wafers haven't been damaged by previous processing steps up until testing. If the
number of dies—the integrated circuits that will eventually become chips— etched on a
wafer exceeds a failure threshold (ie. too many failed dies on one wafer), the wafer is
scrapped rather than investing in further processing.
Device test
Once the front-end process has been completed, the semiconductor devices are subjected
to a variety of electrical tests to determine if they function properly. The proportion of
devices on the wafer found to perform properly is referred to as the yield.
The fab → tests the chips on the wafer with an electronic tester that presses tiny probes
against the chip. The machine marks each bad chip with a drop of dye. The fab charges for
test time; the prices are on the order of cents per second. Chips are often designed with
“testability features” such as "built-in self-test" to speed testing, and reduce test costs.
Good designs try to test and statistically manage corners: extremes of silicon behavior
caused by operating temperature combined with the extremes of fab processing steps. Most
designs cope with more than 64 corners.
Semiconductor device fabrication
Die preparation
Once tested, the wafer is scored and then broken into individual die -- → wafer dicing. Only
the good, unmarked chips go on to be packaged.
Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins
on the package, and sealing the die. Tiny wires are used to connect pads to the pins. In the
old days, wires were attached by hand, but now purpose-built machines perform the task.
Traditionally, the wires to the chips were gold, leading to a “lead frame” (pronounced “leed
frame”) of copper, that had been plated with solder, a mixture of tin and lead. Lead is
poisonous, so lead-free “lead frames” are now mandated by ROHS.
Chip-scale package (CSP) is another packaging technology. A plastic dual in-line package,
like most packages, is many times larger than the actual die hidden inside, whereas CSP
chips are nearly the size of the die. CSP can be constructed for each die before the wafer is
diced [2].
The packaged chips are retested to ensure that they were not damaged during packaging
and that the die-to-pin interconnect operation was performed correctly. A laser etches the
chip’s name and numbers on the package.
List of steps
This is a list of processing techniques that are employed numerous times in a modern
electronic device and do not necessarily imply a specific order.
• Wafer processing
• Wet cleans
• → Photolithography
• → Ion implantation (in which dopants are embedded in the wafer creating regions of
increased (or decreased) conductivity)
• → Dry etching
• Wet etching
• → Plasma ashing
• Thermal treatments
• Rapid thermal anneal
• → Furnace anneals
• → Thermal oxidation
→ Chemical vapor deposition (CVD)
→ Physical vapor deposition (PVD)
→ Molecular beam epitaxy (MBE)
Electrochemical Deposition (ECD). See Electroplating
→ Chemical-mechanical planarization (CMP)
→ Wafer testing (where the electrical performance is verified)
• Wafer backgrinding (to reduce the thickness of the wafer so the resulting chip can be
put into a thin device like a smartcard or PCMCIA card.)
• → Die preparation
• Wafer mounting
• Die cutting
Semiconductor device fabrication
• IC packaging
• → Die attachment
• IC Bonding
• → Wire bonding
• → Flip chip
• Tab bonding
• IC encapsulation
• Baking
• → Plating
• Lasermarking
• Trim and form
• IC testing
Hazardous materials note
Many toxic materials are used in the fabrication process. These include:
• poisonous elemental dopants such as arsenic, antimony and phosphorus
• poisonous compounds like arsine, phosphine and silane
• highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid and
hydrofluoric acid
It is vital that workers not be directly exposed to these dangerous substances. The high
degree of automation common in the IC fabrication industry helps to reduce the risks of
exposure of this sort. Most fabrication facilities employ exhaust management systems, such
as wet scrubbers, combustors, heated absorber cartridges etc, to control the risk to
workers and also the environment if these toxic materials are released into the atmosphere.
When feature widths were far greater than about 10 micrometres, purity was not the issue
that it is today in device manufacturing. As devices became more integrated, → cleanrooms
became even cleaner. Today, the fabs are pressurized with filtered air to remove even the
smallest particles, which could come to rest on the wafers and contribute to defects. The
workers in a semiconductor fabrication facility are required to wear cleanroom suits to
protect the devices from human contamination.
In an effort to increase profits, semiconductor device manufacturing has spread from Texas
and California in the 1960s to the rest of the world, such as Europe, Israel, Japan, Taiwan,
Korea, Singapore and China. It is a global business today.
The leading semiconductor manufacturers typically have facilities all over the world. Intel,
the world's largest manufacturer, has facilities in Europe and Asia as well as the U.S. Other
top manufacturers include STMicroelectronics (Europe), Analog Devices (US), Atmel
(US/Europe), Freescale Semiconductor (US), Samsung (Korea), Texas Instruments (US),
GlobalFoundries (Germany, future New York fab in construction), Toshiba (Japan), NEC
Electronics [3] (Japan), Infineon (Europe), Renesas (Japan), Taiwan Semiconductor
Manufacturing Company (Taiwan, see TSMC web site [4]), Chartered Semiconductor
Manufacturing Ltd (Singapore, see Chartered web site [5]), Sony(Japan), NXP
Semiconductors (Europe), Micron Technology (US), Hynix (Korea) and SMIC (China, see
SMIC web site [6]).
Semiconductor device fabrication
See also
→ Atomic layer deposition
→ Cleanrooms
Electronic design automation
Foundry (electronics)
→ Health hazards in semiconductor manufacturing occupations
International Technology Roadmap for Semiconductors
→ Microfabrication
→ SEMI — The semiconductor industry trade association
External links
• Amkor Technology Semiconductor Packaging & Test
• Semiconductor Manufacturing [8]
• Semiconductor Glossary [9]
NEC's Virtual Factory Tour [10]
Semiconductor materials processing [11]
Calculator for Silicon thermal oxidation [12]
BYU Cleanroom - semiconductor properties, calculators, processes, etc.
• Omron An introduction to Application Expertise - Semiconductor, Photo Voltaic &
Electronics Industry [14]
[1] Zeno Gaburro (2004). " Optical Interconnect (http:/ / books. google. com/ books?id=PgmmFRYE6a0C&
pg=PA122& dq="front+ end+ process"+ transistor& lr=& as_brr=3& ei=elK_SKqAHZDwsgPRw63YDA&
sig=ACfU3U3R53OZ9F-6x6e9woPK4C3fuxQJrw)". in Lorenzo Pavesi and David J. Lockwood. Silicon Photonics.
Springer. ISBN 3540210229. .
[2] http:/ / www. uic. com/ wcms/ WCMS2. nsf/ index/ Resources_26. html
[3] http:/ / www. necel. com/ index. html
[4] http:/ / www. tsmc. com/
[5] http:/ / www. charteredsemi. com/
[6] http:/ / www. smics. com/
[7] http:/ / www. amkor. com
[8] http:/ / www. siliconfareast. com/ manufacturing. HTM
[9] http:/ / www. semiconductorglossary. com
[10] http:/ / www. necel. com/ v_factory/ en/ index. html
[11] http:/ / www. logitech. uk. com/ semicon. asp
[12] http:/ / www. lelandstanfordjunior. com/ thermaloxide. html
[13] http:/ / www. ece. byu. edu/ cleanroom/
[14] http:/ / www. omron-semi-pv. eu/
Chemical-mechanical planarization
Chemical-mechanical planarization
Chemical-mechanical planarization or Chemical-mechanical polishing, commonly
abbreviated CMP, is a technique used in semiconductor fabrication for planarizing a
semiconductor → wafer or other substrate.
The process uses an abrasive and corrosive
chemical slurry (commonly a colloid) in conjunction
with a polishing pad and retaining ring, typically of
a greater diameter than the wafer. The pad and
wafer are pressed together by a dynamic polishing
head and held in place by a plastic retaining ring.
The dynamic polishing head is rotated with
different axes of rotation (i.e., not concentric). This
removes material and tends to even out any
irregular topography, making the wafer flat or
planar. This may be necessary in order to set up the
wafer for the formation of additional circuit
elements. For example, this might be necessary in
order to bring the entire surface within the depth of
field of a → photolithography system, or to
selectively remove material based on its position.
Typical depth-of-field requirements are down to
Angstrom levels for the latest 65 nm technology.
How it works
The process of material removal is not simply that
of abrasive scraping, like sandpaper on wood. The
functional principle of CMP
chemicals in the slurry also react with and/or
weaken the material to be removed. The abrasive accelerates this weakening process and
the polishing pad helps to wipe the reacted materials from the surface. The process has
been likened to that of a child eating a gummy candy. If the candy sits on the tongue
without being scraped around, the candy becomes covered with a gel coating, but the
majority of the candy is not affected. Only with a vigorous scraping does the candy dissolve
Another analogy is the act of brushing one's teeth. The toothbrush is the mechanical part
and the toothpaste is the chemical part. Using either the toothbrush or the toothpaste alone
will get one's teeth somewhat clean, but using the toothbrush and toothpaste together
makes a superior process.
Chemical-mechanical planarization
Usage in semiconductor fabrication
Before about 1990 CMP was looked on as too "dirty" to be included in high-precision
fabrication processes, since abrasion tends to create particles and the abrasives themselves
are not without impurities. Since that time, the integrated circuit industry has moved from
aluminium to copper conductors. This required the development of an additive patterning
process, which relies on the unique abilities of CMP to remove material in a planar and
uniform fashion and to stop repeatably at the interface between copper and oxide insulating
layers (see Copper-based chips for details). Adoption of this process has made CMP
processing much more widespread. In addition to aluminum and copper, CMP processes
have been developed for polishing tungsten, silicon dioxide, and (recently) carbon
Key metrics
Key metrics that are important for CMP are the following:
• Rate of removal: How quickly can the material be removed?
• Uniformity of removal: How uniform is the removal across the die (local) and the wafer
• Planarity: How planar/flat is the surface after the removal process is complete?
• Defects: How many defects and of what size are left behind on the wafer?
• Consistency: How consistent is the performance from wafer to wafer?
[1] Awano,Y.:(2006),"Carbon Nanotube (CNT) Via Interconnect Technologies: Low temperature CVD growth and
chemical mechanical planarization for vertically aligned CNTs". Proc. 2006 ICPT, 10
2. "Chemical Mechanical Planarization Experts". (http:/ / www. ims-expertservices. com/
CaseListing. asp?KeywordID=1782) Retrieved on 2009-04-03.
See also
• → RCA clean
• → Etching (microfabrication)
Physical vapor deposition
Physical vapor deposition
Physical vapor deposition (PVD) is a variety of vacuum deposition and is a general term
used to describe any of a variety of methods to deposit thin films by the condensation of a
vaporized form of the material onto various surfaces (e.g., onto semiconductor → wafers).
The coating method involves purely physical processes such as high temperature vacuum
evaporation or plasma sputter bombardment rather than involving a chemical reaction at
the surface to be coated as in → chemical vapor deposition. The term physical vapor
deposition appears originally in the 1966 book “Vapor Deposition by CF Powell, JH Oxley
and JM Blocher Jr, but Michael Faraday was using PVD to deposit coatings as far back as
Variants of PVD include, in order of increasing novelty:
• Evaporative deposition: In which the material to be deposited is heated to a high vapor
pressure by electrically resistive heating in "low" vacuum.
• Electron beam physical vapor deposition: In which the material to be deposited is heated
to a high vapor pressure by electron bombardment in "high" vacuum.
• → Sputter deposition: In which a glow plasma discharge (usually localized around the
"target" by a magnet) bombards the material sputtering some away as a vapor. Here is
an animation of a generic PVD sputter tool: PVD Animation [1]
• Cathodic Arc Deposition: In which a high power arc directed at the target material blasts
away some into a vapor.
• → Pulsed laser deposition: In which a high power laser ablates material from the target
into a vapor.
PVD is used in the manufacture of items including semiconductor devices, aluminized PET
film for balloons and snack bags, and coated cutting tools for metalworking. Besides PVD
tools for fabrication special smaller tools mainly for scientific purposes have been
developed. They mainly serve the purpose of extreme thin films like atomic layers and are
used mostly for small substrates. A good example are mini e-beam evaporators which can
deposit monolayers of virtually all materials with melting points up to 3500°C.
Some of the techniques used to measure the physical properties of PVD coatings are:
• Calo tester: coating thickness test
• Scratch tester: coating adhesion test
• Pin on disc tester: wear and friction coefficient test
See thin-film deposition for a more general discussion of this class of manufacturing
Physical vapor deposition
[1] http:/ / www. syngraphics. com/ whatsnew_PVD. html
• Anders, Andre (editor). Handbook of Plasma Immersion Ion Implantation and Deposition.
New York: Wiley-Interscience, 2000. ISBN 0471246980.
• Bach, Hans, and Dieter Krause (editors). Thin Films on Glass. Schott series on glass and
glass ceramics. London: Springer-Verlag, 2003. ISBN 3540585974.
• Bunshah, Roitan F. (editor). Handbook of Deposition Technologies for Films and
Coatings: Science, Technology and Applications, second edition. Materials science and
process technology series. Park Ridge, N.J.: Noyes Publications, 1994. ISBN 0815513372.
• Gläser, Hans Joachim. Large Area Glass Coating. Dresden: Von Ardenne Anlagentechnik,
2000. ISBN 3000049533.
• Glocker, David A., and S. Ismat Shah (editors). Handbook of Thin Film Process
Technology (2 vol. set). Bristol, U.K.: Institute of Physics Pub, 2002. ISBN 0750308338.
• Mahan, John E. Physical Vapor Deposition of Thin Films. New York: John Wiley & Sons,
2000. ISBN 0471330019.
• Mattox, Donald M. Handbook of Physical Vapor Deposition (PVD) Processing: Film
Formation, Adhesion, Surface Preparation and Contamination Control.. Westwood, N.J.:
Noyes Publications, 1998. ISBN 0815514220.
• Mattox, Donald M. The Foundations of Vacuum Coating Technology. Norwich, N.Y.:
Noyes Publications/William Andrew Pub., 2003. ISBN 0815514956.
• Mattox, Donald M. and Vivivenne Harwood Mattox (editors). 50 Years of Vacuum Coating
Technology and the Growth of the Society of Vacuum Coaters. Albuquerque, N.M.:
Society of Vacuum Coaters, 2007. ISBN 978-1878068279.
• Powell, Carroll F., Joseph H. Oxley, and John Milton Blocher (editors). Vapor Deposition.
The Electrochemical Society series. New York: Wiley, 1966.
• Westwood, William D. Sputter Deposition. AVS Education Committee book series, v. 2.
New York: Education Committee, AVS, 2003. ISBN 0735401055.
• Willey, Ronald R. Practical Monitoring and Control of Optical Thin Films. Charlevoix, MI:
Willey Optical, Consultants, 2007. ISBN 978-0615137605.
• Willey, Ronald R. Practical Equipment, Materials, and Processes for Optical Thin Films.
Charlevoix, MI: Willey Optical, Consultants, 2007. ISBN 978-0615143972.
External links
• Society of Vacuum Coaters (http:/ / www. svc. org/ )
Atomic layer deposition
Atomic layer deposition
Atomic layer deposition (ALD) is a thin film deposition technique that is based on the
sequential use of a gas phase chemical process. The majority of ALD reactions use two
chemicals, typically called precursors. These precursors react with a surface one-at-a-time
in a sequential manner. By exposing the precursors to the growth surface repeatedly, a thin
film is deposited.[1]
ALD is a self-limiting (the amount of film material deposited in each reaction cycle is
constant), sequential surface chemistry that deposits conformal thin-films of materials onto
substrates of varying compositions. ALD is similar in chemistry to → chemical vapor
deposition (CVD), except that the ALD reaction breaks the CVD reaction into two
half-reactions, keeping the precursor materials separate during the reaction. Due to the
characteristics of self-limiting and surface reactions, ALD film growth makes atomic scale
deposition control possible. By keeping the precursors separate throughout the coating
process, atomic layer control of film growth can be obtained as fine as ~0.1 Å (10 pm)per
ALD had been developed and introduced worldwide with the name Atomic layer epitaxy
(ALE) in the late 1970s.[2] For thin film electroluminescent (TFEL) flat-panel displays, high
quality dielectric and luminescent films were required on large-area substrates, thus the
deposition method of ALD was developed. Interest in ALD has increased in steps in the
mid-1990s and 2000s, with the interest focused on silicon-based microelectronics. ALD is
considered as one deposition method with the greatest potential for producing very thin,
conformal films with control of the thickness and composition of the films possible at the
atomic level. A major driving force for the recent interest is the prospective seen for ALD in
scaling down microelectronic devices.
ALD can be used to deposit several types of thin films, including various oxides (e.g. Al2O3,
TiO2, SnO2, ZnO, HfO2),metal nitrides (e.g. TiN, TaN, WN, NbN), metals (e.g. Ru, Ir, Pt),
and metal sulfides (e.g. ZnS).
ALD process
The growth of material layers by ALD consists of repeating the following characteristic four
1) Exposure of the first precursor.
2) Purge or evacuation of the reaction chamber to remove the non-reacted precursors and
the gaseous reaction by-products.
3) Exposure of the second precursor – or another treatment to activate the surface again for
the reaction of the first precursor.
4) Purge or evacuation of the reaction chamber.
Each reaction cycle adds a given amount of material to the surface, referred to as the
growth per cycle. To grow a material layer, reaction cycles are repeated as many as
required for the desired film thickness. One cycle may take time from 0.5s to a few seconds
and deposit between 0.1 and 3 Å of film thickness. Before starting the ALD process, the
Atomic layer deposition
surface is stabilized to a known, controlled state, usually, by a heat treatment. Due to the
self-terminating reactions, ALD is a surface-controlled process, where process parameters
other than the precursors, substrate, and temperature have little or no influence. And,
because of the surface control, ALD-grown films are extremely conformal and uniform in
Advantages and limitations
Using ALD, Film thickness depends only on the number of reaction cycles, which makes the
thickness control accurate and simple. Unlike CVD, there is less need of reactant flux
homogeneity, which gives large area (large batch and easy scale-up) capability, excellent
conformality and reproducibility, and simplifies the use of solid precursors. Also, the growth
of different multilayer structures is straight forward. These advantages make the ALD
method attractive for microelectronics for manufacturing of future generation integrated
circuits. Another advantage of ALD is the wide range of film materials available, and high
density and low impurity level. Also, lower deposition temperature can be used in order not
to affect sensitive substrates.
The major limitation of ALD is its slowness; usually only a fraction of a monolayer is
deposited in one cycle. Fortunately, the films needed for future-generation ICs are very thin
and thus the slowness of ALD is not such an important issue.
Although the selection of film materials grown by ALD is wide, many technologically
important materials (Si, Ge, Si3N4, several multi-component oxides, certain metals) cannot
currently be deposited by ALD in a cost-effective way.
ALD is a chemical technique and thus there is always a risk of residues being left from the
precursors. The impurity content of the films depends on the completeness of the reactions.
In typical oxide processes where metal halides of alkyl compounds are used together with
water as precursors, impurities found in the films are at the 0.1-1 atom % level.
ALD in microelectronics
In microelectronics, ALD is studied as a potential technique to deposit high-k (high
permittivity) gate oxides, high-k memory capacitor dielectrics, ferroelectrics, and metals
and nitrides for electrodes and interconnects. In high-k gate oxides, where the control of
ultra thin films is essential, ALD is only likely to come in to wider use at the 45 nm
technology. In metallizations, conformal films are required; currently it is expected that
ALD will be used in mainstream production at the 65 nm node. In dynamic random access
memories (DRAMs), the conformality requirements are even higher and ALD is the only
method that can be used when feature sizes become smaller than 100 nm.[3]
Atomic layer deposition
Gate oxides
Deposition of the high-k oxides Al2O3, ZrO2, and HfO2 has been one of the most widely
examined areas of ALD. The motivation for high-k oxides comes from the problem of high
tunneling currents through the currently used SiO2 metal-oxide-semiconductor field-effect
transistor (MOSFET) gate dielectric when it is downscaled to a thickness of 1.0 nm and
below. With the high-k oxide, a thicker gate dielectric can be made for the required
capacitance density, thus the tunneling current can be reduced through the structure.
Intel Corporation has reported using ALD to deposit high-k gate dielectric for its 45 nm
CMOS technology.[4]
DRAM capacitors
The development of dynamic random access memory (DRAM) capacitor dielectrics has been
similar to that of gate dielectrics: SiO2 has been widely used in the industry thus far, but it
is likely to be phased out in the near future as the scale of devices are decreased. The
requirements for the downscaled DRAM capacitors are good conformality and permittivity
values above 200, thus the candidate materials are different from those explored for
MOSFET gate dielectrics. (For example, Al2O3, ZrO2, and HfO2) The most extensively
studied candidate has been (Ba,Sr)TiO3. ALD is a very promising method, which can satisfy
the high conformal requirements of DRAM applications. A permittivity of 180 was measured
for SrTiO3 and 165 for BaTiO3 when films thicker than 200 nm were post-deposition annealed, but when
the film thickness was decreased to 50 nm, the permittivity decreased to only 100.
Transition-metal nitrides
Transition-metal nitrides, such as
TiN and TaN find potential use both as
metal barriers and as gate metals.
Metal barriers are used in modern Cu-based chips to avoid diffusion of Cu into the surrounding materials, such as
insulators and the silicon substrate, and also, to prevent Cu contamination by elements diffusing from the
insulators by surround every Cu interconnection with a layer of metal barriers. The metal barriers have strict
demands: they should be pure; dense; conductive; conformal; thin; have good adhesion towards metals and
insulators. The requirements concerning process technique can be fulfilled by ALD. The most studied ALD nitride
and NH3.[6]
is TiN which is deposited from TiCl4
Metal films
Motivations of an interest in metal ALD are
1) Cu interconnects and W plugs, or at least Cu seed layers for Cu electrodeposition and W
seeds for W CVD,
2) transition-metal nitrides (e.g. TiN, TaN, WN) for Cu interconnect barriers
3) noble metals for ferroelectric random access memory (FRAM) and DRAM capacitor
4) high- and low-work function metals for dual-gate MOSFETs.
Atomic layer deposition
See also
Atomic layer epitaxy
→ Chemical vapor deposition
Thin-film deposition
High-k dielectric
http:/ / ald. colorado. edu/ J_Phys_Chem_100. pdf
T. Suntola, J. Antson, U.S. Patent 4,058,430, 1977
A. Ahnd, Semicond. Int. 26, 46-51, 2003.
http:/ / download. intel. com/ technology/ IEDM2007/ HiKMG_paper. pdf A 45nm Logic Technology with
High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100%
Pb-free Packaging
M. Vehkamaki et al., Electrochem. Solid-State Lett. 2, 504-506, 1999.
[6] K.E. Elers et al.,Chem. Vap. Deposition 4,149, 2002
• Mikko Ritala; Markku Leskelä (March 1999). "Atomic layer epitaxy—a valuable tool for
nanotechnology?". Nanotechnology 10 (1): 19–24. doi: 10.1088/0957-4484/10/1/005
(http:/ / dx. doi. org/ 10. 1088/ 0957-4484/ 10/ 1/ 005).
• Markku Leskelä; Mikko Ritala (2003). "Atomic Layer Deposition Chemistry: Recent
Developments and Future Challenges". Angew. Chem. Int. Ed. 42: 5548–5554. doi:
10.1002/anie.200301652 (http:/ / dx. doi. org/ 10. 1002/ anie. 200301652).
• First use of ALD for DRAM applications (http:/ / www. micromagazine. com/ archive/ 05/
07/ chipworks. html)
• Suppliers of high quality ALD equipment (http:/ / www. cambridgenanotech. com/ ) (http:/
/ www. picosun. com) (http:/ / www. beneq. com)
• Journal articles discussing ALD (http:/ / ald. colorado. edu/ J_Phys_Chem_100. pdf) (http:/
/ link. aip. org/ link/ ?JAPIAU/ 97/ 121301/ 1)
• Academic researchers specializing in ALD (http:/ / chem. wayne. edu/ faculty/ winter/ )
(http:/ / www. chem. harvard. edu/ groups/ gordon/ ) (http:/ / www. colorado. edu/ chem/
people/ georges. html)
• Major conferences dedicated to ALD (http:/ / www. phys. tue. nl/ ALD2008/ )
Molecular beam epitaxy
Molecular beam epitaxy
Molecular beam → epitaxy
(MBE), is one of several methods
of depositing single crystals. It was
invented in the late 1960s at Bell
Telephone Laboratories by J. R.
Arthur and → Alfred Y. Cho[1] .
Molecular beam epitaxy takes
place in high vacuum or ultra high
vacuum (10−8 Pa). The most
important aspect of MBE is the
slow deposition rate (typically less
than 1000 nm per hour), which
epitaxially. The slow deposition
rates require proportionally better
vacuum to achieve the same
impurity levels as other deposition
The Molecular Beam Epitaxy System in the William R. Wiley
Environmental Molecular Sciences Laboratory is used to grow
and characterize thin crystalline films of oxides and ceramics to
understand in detail the chemistry that occurs on oxides and
ceramic surfaces.
In solid-source MBE, ultra-pure elements such as gallium and arsenic are heated in
separate quasi-knudsen effusion cells until they begin to slowly sublimate. The gaseous
elements then condense on the wafer, where they may react with each other. In the
example of gallium and arsenic, single-crystal gallium arsenide is formed. The term "beam"
means that evaporated atoms do not interact with each other or vacuum chamber gases
until they reach the wafer, due to the long mean free paths of the atoms.
During operation, RHEED (Reflection High Energy Electron Diffraction) is often used for
monitoring the growth of the crystal layers. A computer controls shutters in front of each
furnace, allowing precise control of the thickness of each layer, down to a single layer of
atoms. Intricate structures of layers of different materials may be fabricated this way. Such
control has allowed the development of structures where the electrons can be confined in
space, giving quantum wells or even quantum dots. Such layers are now a critical part of
many modern semiconductor devices, including semiconductor lasers and light-emitting
In systems where the substrate needs to be cooled, the ultra-high vacuum environment
within the growth chamber is maintained by a system of cryopumps, and cryopanels, chilled
using liquid nitrogen or cold nitrogen gas to a temperature close to 77 Kelvin (−196
degrees Celsius). Cryogenic temperatures act as a sink for impurities in the vacuum, so
vacuum levels need to be several orders of magnitude better to deposit films under these
conditions. In other systems, the wafers on which the crystals are grown may be mounted
on a rotating platter which can be heated to several hundred degrees Celsius during
Molecular beam epitaxy
Molecular beam epitaxy is also used for the deposition of some types of organic
semiconductors. In this case, molecules, rather than atoms, are evaporated and deposited
onto the wafer. Other variations include gas-source MBE, which resembles → chemical
vapor deposition.
ATG instability
The ATG (Asaro-Tiller-Grinfeld) instability, also known as the Grinfeld instability, is an
elastic instability often encountered during molecular beam epitaxy. If there is a mismatch
between the lattice sizes of the growing film and the supporting crystal, elastic energy will
be accumulated in the growing film. At some critical height, the free energy of the film can
be lowered if the film breaks into isolated islands, where the tension can be relaxed
laterally. The critical height depends on Young moduli, mismatch size, and surface tensions.
Some applications for this instability have been researched, such as the self-assembly of
quantum dots. This community uses the name of Stranski-Krastanov for ATG.
1. Stangl, J.; V. Holý and G. Bauer (2004). "Structural properties of self-organized
semiconductor nanostructures [2]". Rev. Mod. Phys. 76 (3): 725–783.
doi:10.1103/RevModPhys.76.725 [3]. http:/ / link. aps. org/ doi/ 10. 1103/ RevModPhys.
76. 725.
2. Shchukin, Vitaliy A.; Dieter Bimberg (1999). "Spontaneous ordering of nanostructures on
crystal surfaces [4]". Rev. Mod. Phys. 71 (4): 1125–1171.
doi:10.1103/RevModPhys.71.1125 [5]. http:/ / prola. aps. org/ abstract/ RMP/ v71/ i4/
p1125_1. Retrieved 2008-08-15.
3. Jaeger, Richard C. (2002). "Film Deposition". Introduction to Microelectronic
Fabrication. Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.
See also
→ Alfred Y. Cho
Colin P Flynn
Arthur Gossard
Herbert Kroemer
Ben G. Streetman
Solar cell
Wetting layer
High Electron Mobility Transistor
Heterojunction Bipolar Transistor
Quantum cascade laser
Molecular beam epitaxy
External links
• Silicon and germanium nanowires by molecular beam epitaxy
• University of Texas MBE group [7]
• Physics of Thin Films: Molecular Beam Epitaxy (class notes)
A. Y. Cho and J. R. Arthur Jr., “Molecular beam epitaxy,” Prog. Solid State Chem., vol. 10, pp. 157-192, 1975
http:/ / link. aps. org/ doi/ 10. 1103/ RevModPhys. 76. 725
http:/ / dx. doi. org/ 10. 1103%2FRevModPhys. 76. 725
http:/ / prola. aps. org/ abstract/ RMP/ v71/ i4/ p1125_1
http:/ / dx. doi. org/ 10. 1103%2FRevModPhys. 71. 1125
http:/ / www. mpi-halle. mpg. de/ department2/ research-areas/ nanowires-nanoobjects/
si-ge-nanowhiskers-by-mbe/ abstract/
[7] http:/ / www. ece. utexas. edu/ projects/ ece/ mrc/ groups/ street_mbe/ mbechapter. html
[8] http:/ / www. uccs. edu/ ~tchriste/ courses/ PHYS549/ 549lectures/ mbe. html
Czochralski process
The Czochralski process is a
method of crystal growth used
to obtain single crystals of
semiconductors (e.g. silicon,
palladium, platinum, silver,
gold), salts, and synthetic
gemstones. The process is
named after Polish scientist
The Czochralski process
discovered the method in 1916
while investigating the crystallization rates of metals.
The most important application may be the growth of large cylindrical ingots, or boules, of
single crystal silicon. Other semiconductors, such as gallium arsenide, can also be grown by
this method, although lower defect densities in this case can be obtained using variants of
the Bridgman-Stockbarger technique.
Czochralski process
Production of Czochralski silicon
High-purity, semiconductor-grade silicon (only a few
parts per million of impurities) is melted down in a
crucible, which is usually made of quartz. Dopant
impurity atoms such as boron or phosphorus can be
added to the molten intrinsic silicon in precise amounts
in order to → dope the silicon, thus changing it into
n-type or p-type extrinsic silicon. This influences the
electrical conductivity of the silicon. A seed crystal,
mounted on a rod, is dipped into the molten silicon. The
A puller rod with seed crystal for
seed crystal's rod is pulled upwards and rotated at the
growing single-crystal silicon by the
same time. By precisely controlling the temperature
Czochralski process
gradients, rate of pulling and speed of rotation, it is
possible to extract a large, single-crystal, cylindrical ingot from the melt. Occurrence of
unwanted instabilities in the melt can be avoided by investigating and visualizing the
temperature and velocity fields during the crystal growth process.[1] This process is
normally performed in an inert atmosphere, such as argon, and in an inert chamber, such
as quartz.
Size of crystals
Due to the efficiencies that can be gained by the adoption of common → wafer
specifications, the semiconductor industry has for some time used wafers with standardized
dimensions. Currently, high-end device manufacturers use 200 mm and 300 mm diameter
wafers. The crystal ingots from which these wafers are sliced can be up to 2 metres in
length, weighing several hundred kilograms. Larger wafers allow improvements in
manufacturing efficiency, as more chips can be fabricated on each wafer, so there has been
a steady drive to increase silicon wafer sizes. The next step up, 450 mm, is currently
scheduled for introduction in 2012[2] .
Silicon wafers are typically about 0.2 - 0.75 mm thick, and can be polished to a very high
flatness for making integrated circuits, or textured for making solar cells.
Impurity incorporation
When silicon is grown by the Czochralski method, the melt is contained in a silica (quartz)
crucible. During growth, the walls of the crucible dissolve into the melt and Czochralski
silicon therefore contains oxygen at a typical concentration of 1018 cm−3. Oxygen
impurities can have beneficial effects. Carefully chosen annealing conditions can allow the
formation of oxygen precipitates. These have the effect of trapping unwanted transition
metal impurities in a process known as gettering. Additionally, oxygen impurities can
improve the mechanical strength of silicon wafers by immobilising any dislocations which
may be introduced during device processing. It was experimentally shown in the 1990s that
the high oxygen concentration is also beneficial for radiation hardness of silicon particle
detectors used in harsh radiation environment (such as CERN's LHC/S-LHC projects).[3] [4]
Therefore, radiation detectors made of Czochralski- and Magnetic Czochralski-silicon are
considered to be promising candidates for many future high-energy physics experiments.[6]
It has also been shown that presence of oxygen in silicon increases impurity trapping
Czochralski process
during post-implantation annealing processes.[8]
However, oxygen impurities can react with boron in an illuminated environment, such as
experienced by solar cells. This results in the formation of an electrically active
boron–oxygen complex that detracts from cell performance. Module output drops by
approximately 3% during the first few hours of light exposure. [9]
Mathematical expression of impurity incorporation from melt
The impurity concentration in the solid crystal that results from freezing an incremental
amount of volume can be obtained from consideration of the segregation coefficient. [10]
: Segregation coefficient
: Initial volume
: Number of impurities
: Impurity concentration in the melt
: Volume of the melt
: Number of impurities in the melt
: Concentration of impurities in the melt
: Volume of solid
: Concentration of impurities in the solid
During the growth process, volume of melt
melt that are removed.
freezes, and there are impurities from the
Czochralski process
Crucibles used in Czochralski
Crucible after being used
Silicon ingot
See also
Bridgman-Stockbarger technique
Float-zone silicon
Laser-heated pedestal growth
External links
• Czochralski doping process
J. Aleksic et al., Ann. of NY Academy of Sci. 972 (2002) 158.
http:/ / www. physorg. com/ news129301282. html
Z. Li et al., IEEE Trans Nucl. Sci. 39 (6) (1992) 1730
A. Ruzin et al., IEEE Trans Nucl. Sci. 46 (5) (1999) 1310
G. Lindström et al., Nucl. Instr. and Meth. A 466 (2001) 308 and cited literature therein.
CERN RD50 Status Report 2004, CERN-LHCC-2004-031 and LHCC-RD-005 and cited literature therein
J. Härkönen et al., Nucl. Instr. and Meth. A 541 (2005)202.
A. Polman et al., J. Appl. Phys., Vol. 75, No. 6, 15 March 1994
Eikelboom, J.A., Jansen, M.J., 2000. Characteristion of PV modules of new generations; results of tests and
simulations. Report ECN-C-00-067, 18.
[10] James D. Plummer, Michael D. Deal, and Peter B. Griffin, Silicon VLSI Technology, Prentice Hall, 2000, p.
[11] http:/ / www. articleworld. org/ index. php/ Czochralski_process
Plasma ashing
Plasma ashing
In semiconductor manufacturing plasma ashing is the process of removing the photoresist
from an → etched wafer. Using a plasma source, a monatomic reactive species is generated.
Oxygen or fluorine are the most common reactive species. The reactive species combines
with the photoresist to form ash which is removed with a vacuum pump.
Typically, monatomic (single atom) oxygen plasma is created by exposing oxygen gas (O2)
to non-ionizing radiation. This process is done under vacuum in order to create a plasma. As
the plasma is formed, many free radicals are created which could damage the wafer.
Newer, smaller circuitry is increasingly susceptible to these particles. Originally, plasma
was generated in the process chamber, but as the need to get rid of free radicals has
increased, many machines now use a downstream plasma configuration, where plasma is
formed remotely and the desired particles are channeled to the wafer. This allows
electrically charged particles time to recombine before they reach the wafer surface, and
prevents damage to the wafer surface.
Two forms of plasma ashing are typically performed on wafers. High temp ashing, or
stripping, is performed to remove as much photo resist as posible. While the "descum"
process is used to remove residual photo resist in trenches. The main difference between
the two processes are the temperature the wafer is exposed to while in an ashing chamber.
Monatomic oxygen is electrically neutral and although it does recombine during the
channeling, it does so at a slower rate than the positively or negatively charged free
radicals, which attract one another. Effectively, this means that when all of the free radicals
have recombined, there is still a portion of the active species available for process. Because
a large portion of the active species is lost to recombination, process times may take longer.
To some extent, these longer process times can be mitigated by increasing the temperature
of the reaction area.
Rapid thermal processing
Rapid thermal processing
Rapid Thermal Processing (or RTP) refers to a semiconductor manufacturing process
which heats silicon wafers to high temperatures (up to 1200 C or greater) on a timescale of
several seconds or less. During cooling, however, wafer temperatures must be brought
down slowly so they do not break due to thermal shock. Such rapid heating rates are often
attained by high intensity lamps or lasers. These processes are used for a wide variety of
applications in semiconductor manufacturing including dopant activation, → thermal
oxidation, metal reflow and chemical vapor deposition.
Temperature Control
One of the key challenges in rapid thermal processing is accurate measurement and control
of the wafer temperature. Monitoring the ambient with a thermocouple has only recently
become feasible, in that the high temperature ramp rates prevent the wafer from coming to
thermal equilibrium with the process chamber. One temperature control strategy involves
in situ pyrometry to effect real time control.
Rapid thermal anneal
Rapid thermal anneal (RTA) is a subset of Rapid Thermal Processing. It is a process used in
semiconductor device fabrication which consists of heating a single → wafer at a time in
order to affect its electrical properties. Unique heat treatments are designed for different
effects. Wafers can be heated in order to activate dopants, change film-to-film or
film-to-wafer substrate interfaces, densify deposited films, change states of grown films,
repair damage from → ion implantation, move dopants or drive dopants from one film into
another or from a film into the wafer substrate.
Rapid thermal anneals are performed by equipment that heats a single wafer at a time
using either lamp based heating, a hot chuck, or a hot plate that a wafer is brought near.
Unlike → furnace anneals they are short in duration, processing each wafer in several
To achieve short time annealing time trade off is made in temperature and process
uniformity ,temperature measurement and control and wafer stress as well as throughput.
Recently, RTP-like processing has found applications in another rapidly growing field —
solar cell fabrication. RTP-like processing, in which an increase in the temperature of the
semiconductor sample is produced by the absorption of the optical flux, is now used for a
host of solar cell fabrication steps, including phosphorus diffusion for N/P junction
formation and impurity gettering, hydrogen diffusion for impurity and defect passivation,
and formation of screen-printed contacts using Ag-ink for the front and Al-ink for back
contacts, respectively.
Rapid thermal processing
External links
| IEEE RTP Conference Homepage [1]
History of RTP [2]
Semiconductor International article on RTP technology
Rapid Thermal Anneal applications and components [4]
http:/ / www. ieee-rtp. org/
http:/ / www. ieee-rtp. org/ archiv/ rtp_history. pdf|
http:/ / www. reed-electronics. com/ semiconductor/ article/ CA338200|
http:/ / www. articleworld. org/ index. php/ Rapid_thermal_anneal
Furnace anneal
Furnace annealing is a process used in semiconductor device fabrication which consist of
heating multiple semiconductor → wafers in order to affect their electrical properties. Heat
treatments are designed for different effects. Wafers can be heated in order to activate
dopants, change film to film or film to wafer substrate interfaces, densify deposited films,
change states of grown films, repair damage from → implants, move dopants or drive
dopants from one film into another or from a film into the wafer substrate.
Furnace anneals may be integrated into other furnace processing steps, such as oxidations,
or may be processed on their own.
Furnace anneals are performed by equipment especially built to heat semiconductor
wafers. Furnaces are capable of processing lots of wafers at a time but each process can
last between several hours and a day.
Increasingly, furnace anneals are being supplanted by Rapid Thermal Anneal (RTA) or
Rapid Thermal Processing (RTP). The reason for this is the relatively long thermal cycles of
furnaces causes dopants that are being actived, especially boron, to diffuse farther than is
intended. RTP or RTA fixes this by having thermal cycles for each wafer that is of the order
of minutes rather than hours for furnace anneals.
Aviza AVP [1]
Tokyo Electron alpha [2]
Kokusai [3] Vertron, Zestone, and ALDINNA
ASM Advance 400 [4]
http:/ / www. aviza. net/ products/ vert. htm
http:/ / www. tel. com/ eng/ product/ spe/ tps/ butps. htm
http:/ / www. ksec. com
http:/ / www. asm. com/ prod_adv400. asp
Ion implantation
Ion implantation
engineering process by which ions of a
material can be implanted into another
solid, thereby changing the physical
properties of the solid. Ion implantation is
used in semiconductor device fabrication
and in metal finishing, as well as various
applications in materials science research.
The ions introduce both a chemical change
in the target, in that they can be a different
element than the target, and a structural
change, in that the crystal structure of the
target can be damaged or even destroyed by
the energetic collision cascades.
An ion implantation system at LAAS technological
facility in Toulouse, France.
General principle
Ion implantation equipment typically consists of an ion
source, where ions of the desired element are
produced, an accelerator, where the ions are
electrostatically accelerated to a high energy, and a
target chamber, where the ions impinge on a target,
which is the material to be implanted. Thus ion
implantation is a special case of particle radiation. Each
ion is typically a single atom or molecule, and thus the
actual amount of material implanted in the target is the
integral over time of the ion current. This amount is
called the dose. The currents supplied by implanters
are typically small (microamperes), and thus the dose
Ion implantation setup with mass
which can be implanted in a reasonable amount of time
is small. Thus, ion implantation finds application in
cases where the amount of chemical change required is small.
Ion implantation
Typical ion energies are in the range of 10 to 500 keV (1,600 to 80,000 aJ). Energies in the
range 1 to 10 keV (160 to 1,600 aJ) can be used, but result in a penetration of only a few
nanometers or less. Energies lower than this result in very little damage to the target, and
fall under the designation ion beam deposition. Higher energies can also be used:
accelerators capable of 5 MeV (800,000 aJ) are common. However, there is often great
structural damage to the target, and because the depth distribution is broad, the net
composition change at any point in the target will be small.
The energy of the ions, as well as the ion species and the composition of the target
determine the depth of penetration of the ions in the solid: A monoenergetic ion beam will
generally have a broad depth distribution. The average penetration depth is called the
range of the ions. Under typical circumstances ion ranges will be between 10 nanometers
and 1 micrometer. Thus, ion implantation is especially useful in cases where the chemical
or structural change is desired to be near the surface of the target. Ions gradually lose their
energy as they travel through the solid, both from occasional collisions with target atoms
(which cause abrupt energy transfers) and from a mild drag from overlap of electron
orbitals, which is a continuous process. The loss of ion energy in the target is called
Application in semiconductor device fabrication
→ Doping
The introduction of dopants in a semiconductor is the most common application of ion
implantation. Dopant ions such as boron, phosphorus or arsenic are generally created from
a gas source, so that the purity of the source can be very high. These gases tend to be very
hazardous. When implanted in a semiconductor, each dopant atom creates a charge carrier
in the semiconductor (hole or electron, depending on if it is a p-type or n-type dopant), thus
modifying the conductivity of the semiconductor in its vicinity.
Silicon on insulator
One prominent method for preparing silicon on insulator (SOI) substrates from
conventional silicon substrates is the SIMOX (Separation by IMplantation of OXygen)
process, wherein a buried high dose oxygen implant is converted to silicon oxide by a high
temperature annealing process.
Mesotaxy is the term for the growth of a crystallographically matching phase underneath
the surface of the host crystal (compare to → epitaxy, which is the growth of the matching
phase on the surface of a substrate). In this process, ions are implanted at a high enough
energy and dose into a material to create a layer of a second phase, and the temperature is
controlled so that the crystal structure of the target is not destroyed. The crystal
orientation of the layer can be engineered to match that of the target, even though the
exact crystal structure and lattice constant may be very different. For example, after the
implantation of nickel ions into a silicon wafer, a layer of nickel silicide can be grown in
which the crystal orientation of the silicide matches that of the silicon.
Ion implantation
Application in metal finishing
Tool steel toughening
Nitrogen or other ions can be implanted into a tool steel target (drill bits, for example). The
structural change caused by the implantation produces a surface compression in the steel,
which prevents crack propagation and thus makes the material more resistant to fracture.
The chemical change can also make the tool more resistant to corrosion.
Surface finishing
In some applications, for example prosthetic devices such as artificial joints, it is desired to
have surfaces very resistant to both chemical corrosion and wear due to friction. Ion
implantation is used in such cases to engineer the surfaces of such devices for more reliable
performance. As in the case of tool steels, the surface modification caused by ion
implantation includes both a surface compression which prevents crack propagation and an
alloying of the surface to make it more chemically resistant to corrosion.
Problems with ion implantation
Crystallographic damage
Each individual ion produces many point defects in the target crystal on impact such as
vacancies and interstitials. Vacancies are crystal lattice points unoccupied by an atom: in
this case the ion collides with a target atom, resulting in transfer of a significant amount of
energy to the target atom such that it leaves its crystal site. This target atom then itself
becomes a projectile in the solid, and can cause successive collision events. Interstitials
result when such atoms (or the original ion itself) come to rest in the solid, but find no
vacant space in the lattice to reside. These point defects can migrate and cluster with each
other, resulting in dislocation loops and other defects.
Damage recovery
Because ion implantation causes damage to the crystal structure of the target which is
often unwanted, ion implantation processing is often followed by a thermal annealing. This
can be referred to as damage recovery.
The amount of crystallographic damage can be enough to completely amorphize the surface
of the target: i.e. it can become an amorphous solid (such a solid produced from a melt is
called a glass). In some cases, complete amorphization of a target is preferable to a highly
defective crystal: An amorphized film can be regrown at a lower temperature than required
to anneal a highly damaged crystal.
Ion implantation
Some of the collision events result in atoms being ejected (sputtered) from the surface, and
thus ion implantation will slowly etch away a surface. The effect is only appreciable for very
large doses.
Ion channelling
If there is a crystallographic structure to the target, and especially in
semiconductor substrates where the crystal structure is more open,
particular crystallographic directions offer much lower stopping than
other directions. The result is that the range of an ion can be much
longer if the ion travels exactly along a particular direction, for
example the <110> direction in silicon and other diamond cubic
materials. This effect is called ion channelling, and, like all the
channelling effects, is highly nonlinear, with small variations from
perfect orientation resulting in extreme differences in implantation
depth. For this reason, most implantation is carried out a few degrees
off-axis, where tiny alignment errors will have more predictable
effects. There is no relation between this effect and ion channel of a
cell membrane.
A diamond cubic
crystal viewed from
the <110> direction,
showing hexagonal
ion channels.
Ion channelling can be used directly in Rutherford backscattering and related techniques as
an analytical method to determine the amount and depth profile of damage in crystalline
thin film materials.
Hazardous Materials Note
In the ion implantation semiconductor fabrication process of → wafers, it is important for
the workers to minimize their exposure to the toxic materials used in the ion implanter
process. Such hazardous elements, solid source and gasses are used, such as Arsine and
Phosphine. For this reason, the semiconductor fabrication facilities are highly automated,
and may feature negative pressure gas bottles safe delivery system (SDS). Other elements
may include Antimony, Arsenic, Phosphorus, and Boron. Residue of these elements show up
when the machine is opened to atmosphere, and can also be accumulated and found
concentrated in the vacuum pumps hardware. It is important not to expose yourself to these
carcinogenic, corrosive, flammable, and toxic elements. Many overlapping safety protocols
must be used when handling these deadly compounds. Use safety, and read MSDS's.
High Voltage Safety
High voltage power supplies in ion implantation equipment can pose a risk of electrocution.
In addition, high-energy atomic collisions can, in some cases, generate radionuclides.
Operators and Maintenance personnel should learn and follow the safety advice of the
manufacturer and/or the institution responsible for the equipment. Prior to entry to high
voltage area, terminal components must be grounded using a grounding stick. Next, power
supplies should be locked in the off state and tagged to prevent unauthorized energizing.
Ion implantation
Manufacturers of Ion Implantation Equipment
Advanced Ion Beam Technology [1]
Applied Materials [2]
Axcelis Technologies [3]
Complete Ions [4]
Facilitation Centre for Industrial Plasma Technologies
Global Technologies, R&D equipment and Service [6]
Ion Beam Services [7]
Nissin Ion Equipment [8]
SemEquip [9]
SEN Corporation (a SHI and Axcelis company) [10]
Tokyo Electron Limited [11]
Ulvac Technologies [12]
Varian Semiconductor Equipment [13]
External links
• SEMI [14] -- a semiconductor standards clearinghouse and trade organization
• Ion Implantation [15]
• James Ziegler's code for simulating ion implantation. [16]
[1] http:/ / www. aibt-inc. com
[2] http:/ / www. appliedmaterials. com
[3] http:/ / www. axcelis. com
[4] http:/ / www. completeions. com
[5] http:/ / www. plasmaindia. com
[6] http:/ / www. global-technologies. fr
[7] http:/ / www. ion-beam-services. com
[8] http:/ / www. nissin-ion. co. jp
[9] http:/ / www. semequip. com
[10] http:/ / www. senova. co. jp/ english/ index. html
[11] http:/ / www. tel. com/ eng/ about/ index. htm
[12] http:/ / www. ulvac. com
[13] http:/ / www. vsea. com
[14] http:/ / www. semi. org
[15] http:/ / www. casetechnology. com/ implant. html
[16] http:/ / www. srim. org
Etching (microfabrication)
Etching (microfabrication)
Etching is used in → microfabrication to
chemically remove layers from the surface
of a → wafer during manufacturing. Etching
is a critically important process module,
and every wafer undergoes many etching
steps before it is complete.
For many etch steps, part of the wafer is
protected from the etchant by a "masking"
material which resists etching. In some
cases, the masking material is photoresist
which has been patterned using →
photolithography. Other situations require
a more durable mask, such as silicon
Etching tanks used to perform Piranha, Hydrofluoric
acid or → RCA clean on 4-inch wafer batches at LAAS
technological facility in Toulouse, France.
Figures of merit
If the etch is intended to make a cavity in a material, the depth of the cavity may be
controlled approximately using the etching time and the known etch rate. More often,
though, etching must entirely remove the top layer of a multilayer structure, without
damaging the underlying or masking layers. The etching system's ability to do this depends
on the ratio of etch rates in the two materials (selectivity).
Some etches undercut the masking layer and form cavities with sloping sidewalls. The
distance of undercutting is called bias. Etchants with large bias are called isotropic,
because they erode the substrate equally in all directions. Modern processes greatly prefer
anisotropic etches, because they produce sharp, well-controlled features.
Yellow: layer to be removed; blue: layer to remain
1. A poorly selective etch removes the top layer, but also attacks the
underlying material.
2. A highly selective etch leaves the underlying material unharmed.
Red: masking layer; yellow: layer to be removed
1. A perfectly isotropic etch produces round sidewalls.
2. A perfectly anisotropic etch produces vertical sidewalls.
Etching (microfabrication)
Etching media and technology
The two fundamental types of etchants are liquid-phase ("wet") and plasma-phase ("dry").
Each of these exists in several varieties.
Wet etching
The first etching processes used liquid-phase ("wet") etchants. The wafer can be immersed
in a bath of etchant, which must be agitated to achieve good process control. For instance,
buffered hydrofluoric acid (BHF) is used commonly to etch silicon dioxide over a silicon
Different specialised etchants can be used to characterise the surface etched.
Wet etchants are usually isotropic, which leads to large bias when etching thick films. They
also require the disposal of large amounts of toxic waste. For these reasons, they are
seldom used in state-of-the-art processes. However, the photographic developer used for
photoresist resembles wet etching.
As an alternative to immersion, single wafer machines use the Bernoulli principle to employ
a gas (usually, pure nitrogen) to cushion and protect one side of the wafer while etchant is
applied to the other side. It can be done to either the front side or back side. The etch
chemistry is dispensed on the top side when in the machine and the bottom side is not
affected. This etch method is particularly effective just before "backend" processing
(BEOL), where wafers are normally very much thinner after wafer backgrinding, and very
sensitive to thermal or mechanical stress. Etching a thin layer of even a few micrometres
will remove microcracks produced during backgrinding resulting in a the wafer having
dramatically increased strength and flexibility without breaking.
Anisotropic wet etching
Some wet etchants etch crystalline
materials at very different rates
depending upon which crystal face is
exposed. In single-crystal materials
(e.g. silicon wafers), this effect can
allow very high anisotropy, as shown
in the figure.
Several anisotropic wet etchants are
available for silicon. For instance,
potassium hydroxide (KOH) can
An anisotropic wet etch on a silicon wafer creates a cavity
achieve selectivity of 400 between
with a trapezoidal cross-section. The bottom of the cavity is a
<100> plane (see Miller indices), and the sides are <111>
<100> and <111> planes. Another
planes. The yellow material is an etch mask, and the blue
option is EDP (an aqueous solution of
material is silicon.
ethylene diamine and pyrocatechol),
which also displays high selectivity
for p-type doping. Neither of these etchants may be used on wafers that contain CMOS
integrated circuits. Both of them etch aluminium, commonly used as a metallization (wiring)
material. KOH introduces mobile potassium ions into silicon dioxide, and EDP is highly
corrosive and carcinogenic. Tetramethylammonium hydroxide (TMAH) presents a safer
alternative, although it has even worse selectivity between <100> and <111> planes in
Etching (microfabrication)
silicon than does EDP.
Plasma etching
Modern VLSI processes avoid wet etching, and use → plasma etching instead. → Plasma
etchers can operate in several modes by adjusting the parameters of the plasma. Ordinary
plasma etching operates between 0.1 and 5 torr. (This unit of pressure, commonly used in
vacuum engineering, equals approximately 133.3 pascals.) The plasma produces energetic
free radicals, neutrally charged, that react at the surface of the wafer. Since neutral
particles attack the wafer from all angles, this process is isotropic.
The source gas for the plasma usually contains small molecules rich in chlorine or fluorine.
For instance, carbon tetrachloride (CCl4) etches silicon and aluminium, and
trifluoromethane etches silicon dioxide and silicon nitride. A plasma containing oxygen is
used to oxidize ("→ ash") photoresist and facilitate its removal.
Ion milling, or sputter etching, uses lower pressures, often as low as 10-4 torr (10 mPa). It
bombards the wafer with energetic ions of noble gases, often Ar+, which knock atoms from
the substrate by transferring momentum. Because the etching is performed by ions, which
approach the wafer approximately from one direction, this process is highly anisotropic. On
the other hand, it tends to display poor selectivity. → Reactive-ion etching (RIE) operates
under conditions intermediate between sputter and plasma etching (between 10-3 and 10-1
torr). → Deep reactive-ion etching (DRIE) modifies the RIE technique to produce deep,
narrow features.
Common etch processes used in microfabrication
Etchants for common microfabrication materials
Material to be
Wet etchants
Plasma etchants
Aluminium (Al)
80% phosphoric acid (H3PO4) + 5% acetic acid
+ 5% nitric acid (HNO3) + 10% water (H2O) at 35–45 °C
Indium tin oxide [ITO]
Hydrochloric acid (HCl) + nitric acid (HNO3) + water (H2O)
(1:0.1:1) at 40 °C
Chromium (Cr)
• "Chrome etch": ceric ammonium nitrate
((NH4)2Ce(NO3)6) + nitric acid (HNO3)
• Hydrochloric acid (HCl)
Gold (Au)
Aqua regia
Cl2, CCl4, SiCl4, BCl3
Molybdenum (Mo)
Organic residues and
Piranha etch: sulfuric acid (H2SO4) + hydrogen peroxide
Platinum (Pt)
Aqua regia
Silicon (Si)
Nitric acid (HNO3) + hydrofluoric acid (HF)
Silicon dioxide (SiO2)
• Hydrofluoric acid (HF)
• → Buffered oxide etch [BOE]: ammonium fluoride (NH4F)
and hydrofluoric acid (HF)
O2 (→ ashing)
• CF4, SF6, NF3
• Cl2, CCl2F2
CF4, SF6, NF3
Etching (microfabrication)
Silicon nitride (Si3N4)
• 85% Phosphoric acid (H3PO4) at 180 °C
etch mask)
• Hydrofluoric acid (HF)
(Requires SiO2 CF , SF , NF
Tantalum (Ta)
Titanium (Ti)
Hydrofluoric acid (HF)
→ Titanium nitride
• Nitric acid (HNO3) + hydrofluoric acid (HF)
• SC1
Tungsten (W)
• Nitric acid (HNO3) + hydrofluoric acid (HF)
• Hydrogen Peroxide (H2O2)
• CF4
• SF6
• Jaeger, Richard C. (2002). "Lithography". Introduction to Microelectronic Fabrication.
Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.
• Ibid, "Processes for MicroElectroMechanical Systems (MEMS)"
See also
• → Chemical-Mechanical Polishing
• Ingot sawing
External links
• BYU Cleanroom Chemical Etching
[1] Wolf, S.; R.N. Tauber (1986). Silicon Processing for the VLSI Era: Volume 1 - Process Technology. Lattice
Press. pp. 531–534. ISBN 0-961672-3-7.
[2] Wolf, S.; R.N. Tauber (1986). Silicon Processing for the VLSI Era: Volume 1 - Process Technology. Lattice
Press. p. 546. ISBN 0-961672-3-7.
Bahadur, Birendra (1990). Liquid Crystals: Applications and Uses. World Scientific. p. 183. ISBN 9810229755.
Walker, Perrin; William H. Tarn (1991). CRC Handbook of Metal Etchants. pp. 287–291. ISBN 0-8949-3623-6.
Kohler, Michael (1999). Etching in Microsystem Technology. John Wiley & Son Ltd. p. 329. ISBN 3527295615.
http:/ / www. ee. byu. edu/ cleanroom/ chemical. phtml
Dry etching
Dry etching
Dry etching refers to the removal of material, typically a masked pattern of semiconductor
material, by exposing the material to a bombardment of ions (usually a plasma of reactive
gases such as fluorocarbons, oxygen, chlorine, boron trichloride; sometimes with addition
of nitrogen, argon, helium and other gases) that dislodge portions of the material from the
exposed surface. Unlike with many (but not all, see isotropic etching) of the wet chemical
etchants used in wet etching, the dry etching process typically etches directionally or
Dry etching is used in conjunction with → photolithographic techniques to attack certain
areas of a semiconductor surface in order to form recesses in material, such as contact
holes (which are contacts to the underlying semiconductor substrate) or via holes (which
are holes that are formed to provide an interconnect path between conductive layers in the
layered semiconductor device) or to otherwise remove portions of semiconductor layers
where predominantly vertical sides are desired. In conjunction with semiconductor
manufacturing, micromachining and display production the removal of organic residues by
oxygen plasmas is sometimes correctly described as a dry etch process. However, also the
term → plasma ashing may be used.
Dry etching is particularly useful for materials and semiconductors which are chemically
resistant and could not be wet etched, such as silicon carbide or gallium nitride
See also
• → Plasma etcher
• → Etching (microfabrication)
Epitaxy refers to the method of depositing a monocrystalline film on a monocrystalline
substrate. The deposited film is denoted as epitaxial film or epitaxial layer. The term
epitaxy comes from the Greek roots epi, meaning "above", and taxis, meaning "in ordered
manner". It can be translated "to arrange upon".
Epitaxial films may be grown from gaseous or liquid precursors. Because the substrate acts
as a seed crystal, the deposited film takes on a lattice structure and orientation identical to
those of the substrate. This is different from other thin-film deposition methods which
deposit polycrystalline or amorphous films, even on single-crystal substrates. If a film is
deposited on a substrate of the same composition, the process is called homoepitaxy;
otherwise it is called heteroepitaxy.
Homoepitaxy is a kind of epitaxy performed with only one material. In homoepitaxy, a
crystalline film is grown on a substrate or film of the same material. This technology is
applied to growing a more purified film than the substrate and fabricating layers with
different doping levels.
Heteroepitaxy is a kind of epitaxy performed with materials that are different from each
other. In heteroepitaxy, a crystalline film grows on a crystalline substrate or film of another
material. This technology is often applied to growing crystalline films of materials of which
single crystals cannot be obtained and to fabricating integrated crystalline layers of
different materials. Examples include gallium nitride (GaN) on sapphire or aluminium
gallium indium phosphide (AlGaInP) on gallium arsenide (GaAs).
Heterotopotaxy is a process similar to heteroepitaxy except for the fact that thin film
growth is not limited to two dimensional growth. Here the substrate is similar only in
structure to the thin film material.
Epitaxy is used in silicon-based manufacturing processes for BJTs and modern CMOS, but it
is particularly important for compound semiconductors such as gallium arsenide.
Manufacturing issues include control of the amount and uniformity of the deposition's
resistivity and thickness, the cleanliness and purity of the surface and the chamber
atmosphere, the prevention of the typically much more highly doped substrate wafer's
diffusion of dopant to the new layers, imperfections of the growth process, and protecting
the surfaces during the manufacture and handling.
Epitaxy is used in nanotechnology and in semiconductor fabrication. Indeed, epitaxy is the
only affordable method of high crystalline quality growth for many semiconductor
materials, including technologically important materials as silicon-germanium, gallium
nitride, gallium arsenide, indium phosphide and graphene.
Epitaxy is also used to grow layers of pre-→ doped silicon on the polished sides of silicon →
wafers, before they are processed into semiconductor devices.
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Epitaxial silicon is usually grown using vapor-phase epitaxy (VPE), a modification of →
chemical vapor deposition. Molecular-beam and liquid-phase epitaxy (MBE and LPE) are
also used, mainly for compound semiconductors. Solid-phase epitaxy is used primarily for
crystal-damage healing.
Silicon is most commonly deposited from silicon tetrachloride in hydrogen at approximately
1200 °C:
SiCl4(g) + 2H2(g) ↔ Si(s) + 4HCl(g)
This reaction is reversible, and the growth rate depends strongly upon the proportion of the
two source gases. Growth rates above 2 micrometres per minute produce polycrystalline
silicon, and negative growth rates (→ etching) may occur if too much hydrogen chloride
byproduct is present. (In fact, hydrogen chloride may be added intentionally to etch the
wafer.) An additional etching reaction competes with the deposition reaction:
SiCl4(g) + Si(s) ↔ 2SiCl2(g)
Silicon VPE may also use silane, dichlorosilane, and trichlorosilane source gases. For
instance, the silane reaction occurs at 650 °C in this way:
SiH4 → Si + 2H2
This reaction does not inadvertently etch the wafer, and takes place at lower temperatures
than deposition from silicon tetrachloride. However, it will form a polycrystalline film
unless tightly controlled, and it allows oxidizing species that leak into the reactor to
contaminate the epitaxial layer with unwanted compounds such as silicon dioxide.
VPE is sometimes classified by the chemistry of the source gases, such as hydride VPE and
metalorganic VPE.
Liquid phase epitaxy (LPE) is a method to grow semiconductor crystal layers from the melt
on solid substrates. This happens at temperatures well below the melting point of the
deposited semiconductor. The semiconductor is dissolved in the melt of another material.
At conditions that are close to the equilibrium between dissolution and deposition the
deposition of the semiconductor crystal on the substrate is slow and uniform. Typical
deposition rates for monocrystalline films range from 0.1 to 1 μm/minute. The equilibrium
conditions depend very much on the temperature and on the concentration of the dissolved
semiconductor in the melt. The growth of the layer from the liquid phase can be controlled
by a forced cooling of the melt. Impurity introduction can be strongly reduced. Doping can
be achieved by the addition of dopants.
The method is mainly used for the growth of compound semiconductors. Very thin, uniform
and high quality layers can be produced. A typical example for the liquid phase epitaxy
method is the growth of ternery and quarternery III-V compounds on gallium arsenide
(GaAs) substrates. As a solvent quite often gallium is used in this case. Another frequently
used substrate is indium phosphide (InP). However also other substrates like glass or
ceramic can be applied for special applications. To facilitate nucleation, and to avoid
tension in the grown layer the thermal expansion coefficient of substrate and grown layer
should be similar.
Solid Phase Epitaxy (SPE) is a transition between the amorphous and crystalline phases of a
material. It is usually done by first depositing a film of amorphous material on a crystalline
substrate. The substrate is then heated to crystallize the film. The single crystal substrate
serves as a template for crystal growth. The annealing step used to recrystallize or heal
silicon layers amorphized during ion implantation is also considered one type of Solid Phase
Epitaxy. The Impurity segregation and redistribution at the growing crystal-amorphus layer
interface during this process is used to incorporate low-solubility dopants in metals and
Silicon. [1]
In MBE, a source material is heated to produce an evaporated beam of particles. These
particles travel through a very high vacuum (10-8 Pa; practically free space) to the
substrate, where they condense. MBE has lower throughput than other forms of epitaxy.
This technique is widely used for growing III-V semiconductor crystals.[2] [3] .
An epitaxial layer can be doped during deposition by adding impurities to the source gas,
such as arsine, phosphine or diborane. The concentration of impurity in the gas phase
determines its concentration in the deposited film. As in CVD, impurities change the
deposition rate. Additionally, the high temperatures at which CVD is performed may allow
dopants to diffuse into the growing layer from other layers in the wafer ("out-diffusion").
Also, dopants in the source gas, liberated by evaporation or wet etching of the surface, may
diffuse into the epitaxial layer ("autodoping"). The dopant profiles of underlying layers
change as well, however not as significantly.
See also
Island growth
Atomic layer epitaxy
→ Epiwafer
Exchange bias
Quantum cascade laser
Selective area epitaxy
→ Silicon on sapphire
• Single event upset
• Wake Shield Facility
• Zhores Ivanovich Alferov
• Jaeger, Richard C. (2002). "Film Deposition". Introduction to Microelectronic Fabrication.
Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.
External links
• [4]: a central forum for the epitaxy-communities
• Epitaxial growth [5]
• Deposition processes [6]
[1] A. Polman et al., J. Appl. Phys., Vol. 75, No. 6, 15 March 1994
[2] A. Y. Cho, “Growth of III\–V semiconductors by molecular beam epitaxy and their properties,” Thin Solid Films,
vol. 100, pp. 291-317, 1983.
[3] Cheng, K.-Y., "Molecular beam epitaxy technology of III-V compound semiconductors for optoelectronic
applications," Proceedings of the IEEE , vol.85, no.11, pp.1694-1714, Nov 1997 URL: http:/ / ieeexplore. ieee.
org/ stamp/ stamp. jsp?arnumber=649646& isnumber=14175
[4] http:/ / www. epitaxy. net/
[5] http:/ / www. sandia. gov/ mstc/ technologies/ photonics/ gallery006. html
[6] http:/ / www. memsnet. org/ mems/ processes/ deposition. html
Optical lithography, is a process used in → microfabrication to selectively remove parts of a
thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a
photo mask to a light-sensitive chemical photo resist, or simply "resist," on the substrate. A
series of chemical treatments then engraves the exposure pattern into the material
underneath the photo resist. In complex integrated circuits, for example a modern CMOS, a
wafer will go through the photolithographic cycle up to 50 times.
Optical lithography shares some fundamental principles with photography in that, the
pattern in the etching resist is created by exposing it to light, either using a projected
image or an optical mask. This procedure is comparable to a high precision version of the
method used to make printed circuit boards. Subsequent stages in the process have more in
common with etching than to lithographic printing. It is used because it affords exact
control over the shape and size of the objects it creates, and because it can create patterns
over an entire surface simultaneously. Its main disadvantages are that it requires a flat
substrate to start with, it is not very effective at creating shapes that are not flat, and it can
require extremely clean operating conditions.
Basic procedure
A single iteration of photolithography combines
several steps in sequence. Modern cleanrooms use
automated, robotic wafer track systems to
coordinate the process. The procedure described
here omits some advanced treatments, such as
thinning agents or edge-bead removal.[1]
If organic or inorganic contaminations are present
on the wafer surface, they are usually removed by
wet chemical treatment, e.g. the → RCA clean
procedure based on solutions containing hydrogen
The wafer track portion of an aligner that
uses 365 nm ultraviolet light.
The wafer is initially heated to a temperature sufficient to drive off any moisture that may
be present on the wafer surface. Wafers that have been in storage must be chemically
cleaned to remove contamination. A liquid or gaseous "adhesion promoter", such as
Bis(trimethylsilyl)amine ("hexamethyldisilazane", HMDS), is applied to promote adhesion of
the photoresist to the wafer. The phrase "adhesion promoter" is in fact incorrect, as the
surface layer of Silicondioxide on the wafer reacts with the agent to form Methylated
Silicon-hydroxide, a highly water repellent layer not unlike the layer of wax on a car's paint.
This water repellent layer prevents the aqueous developer from penetrating between the
photoresist layer and the wafer's surface, thus preventing so-called lifting of small
photoresist structures in the (developing) pattern.
Photoresist application
The wafer is covered with photo resist by spin coating. A viscous, liquid solution of photo
resist is dispensed onto the wafer, and the wafer is spun rapidly to produce a uniformly
thick layer. The spin coating typically runs at 1200 to 4800 rpm for 30 to 60 seconds, and
produces a layer between 0.5 and 2.5 micrometres thick. The spin coating process results
in a uniform thin layer, usually with uniformity of within 5 to 10 nanometres. This
uniformity can be explained by detailed fluid-mechanical modelling, which shows that
essentially the resist moves much faster at the top of the layer than at the bottom, where
viscous forces bind the resist to the wafer surface. Thus, the top layer of resist is quickly
ejected from the wafer's edge while the bottom layer still creeps slowly radially along the
wafer. In this way, any 'bump' or 'ridge' of resist is removed, leaving a very flat layer. Final
thickness is also determined by the evaporation of liquid solvents from the resist. For very
small, dense features (<125 or so nm), thinner resist thicknesses (<0.5 microns) are
needed to overcome collapse effects at high aspect ratios; typical aspect ratios are <4:1.
The photo resist-coated wafer is then prebaked to drive off excess, typically at 90 to 100 °C
for 30 to 60 seconds on a hotplate.
Exposure and developing
After prebaking, the photoresist is exposed to a pattern of intense light. Optical lithography
typically uses ultraviolet light (see below). Positive photoresist, the most common type,
becomes soluble in the basic developer when exposed; negative photoresist becomes
insoluble in the (organic) developer. This chemical change allows some of the photoresist to
be removed by a special solution, called "developer" by analogy with photographic
developer. To learn more about the process of exposure and development of positive resist,
see: Ralph Dammel, "Diazonaphtoquinone-based resists", SPIE Optical Engineering Press,
Vol TT11 (1993).
A PEB (post-exposure bake) is performed before developing, typically to help reduce
standing wave phenomena caused by the destructive and constructive interference patterns
of the incident light. In DUV (deep ultraviolet, or 248 nm exposure wavelength) lithography,
CAR (chemically amplified resist) chemistry is used. This process is much more sensitive to
PEB time, temperature, and delay, as most of the "exposure" reaction (creating acid,
making the polymer soluble in the basic developer) actually occurs in the PEB.[2]
The develop chemistry is delivered on a spinner, much like photoresist. Developers
originally often contained sodium hydroxide (NaOH). However, sodium is considered an
extremely undesirable contaminant in MOSFET fabrication because it degrades the
insulating properties of gate oxides (specifically, sodium ions can migrate in and out of the
gate, changing the threshold voltage of the transistor and making it harder or easier to turn
the transistor on over time). Metal-ion-free developers such as tetramethylammonium
hydroxide (TMAH) are now used.
The resulting wafer is then "hard-baked" if a non-chemically amplified resist was used,
typically at 120 to 180 °C for 20 to 30 minutes. The hard bake solidifies the remaining
photoresist, to make a more durable protecting layer in future → ion implantation, wet
chemical etching, or → plasma etching.
In etching, a liquid ("wet") or plasma ("dry") chemical agent removes the uppermost layer
of the substrate in the areas that are not protected by photoresist. In semiconductor
fabrication, dry etching techniques are generally used, as they can be made anisotropic, in
order to avoid significant undercutting of the photoresist pattern. This is essential when the
width of the features to be defined is similar to or less than the thickness of the material
being etched (ie when the aspect ratio approaches unity). Wet etch processes are generally
isotropic in nature, which is often indispensable for microelectromechanical systems, where
suspended structures must be "released" from the underlying layer.
The development of low-defectivity anisotropic dry-etch process has enabled the
ever-smaller features defined photolithographically in the resist to be transferred to the
substrate material.
Photoresist removal
After a photoresist is no longer needed, it must be removed from the substrate. This usually
requires a liquid "resist stripper", which chemically alters the resist so that it no longer
adheres to the substrate. Alternatively, photoresist may be removed by a plasma containing
oxygen, which oxidizes it. This process is called → ashing, and resembles dry etching.
Exposure ("printing") systems
Exposure systems typically produce an image on the
wafer using a photomask. The light shines through the
photomask, which blocks it in some areas and lets it
pass in others. (Maskless lithography projects a precise
beam directly onto the wafer without using a mask, but
it is not widely used in commercial processes.)
Exposure systems may be classified by the optics that
transfer the image from the mask to the wafer.
Karl Süss manual contact aligner for
small volume processing.
Contact and proximity
A contact printer, the simplest exposure system, puts a photomask in direct contact with
the wafer and exposes it to a uniform light. A proximity printer puts a small gap between
the photomask and wafer. In both cases, the mask covers the entire wafer, and
simultaneously patterns every die.
Contact printing is liable to damage both the mask and the wafer, and this was the primary
reason it was abandoned for high volume production. Both contact and proximity
lithography require the light intensity to be uniform across an entire wafer, and the mask to
align precisely to features already on the wafer. As modern processes use increasingly
large wafers, these conditions become increasingly difficult.
Research and prototyping processes often use contact lithography, because it uses
inexpensive hardware and can achieve high optical resolution. The resolution is
approximately the square root of the product of the wavelength and the gap distance.
Hence, contact printing offers the best resolution, because its gap distance is
approximately zero (neglecting the thickness of the photoresist itself). In addition,
nanoimprint lithography may revive interest in this familiar technique, especially since the
cost of ownership is expected to be low.
Very-large-scale integration lithography uses projection systems. Unlike contact or
proximity masks, which cover an entire wafer, projection masks (known as "reticles") show
only one die or an array of die (known as a "field"). Projection exposure systems (steppers)
project the mask onto the wafer many times to create the complete pattern.
The image for the mask originates from a computerized data file. This data file is converted
to a series of polygons and written onto a square fused quartz substrate covered with a
layer of chrome using a photolithographic process. A laser beam (laser writer) or a beam of
electrons (e-beam writer) is used to expose the pattern defined in the data file and travels
over the surface of the substrate in either a vector or raster scan manner. Where the
photoresist on the mask is exposed, the chrome can be etched away, leaving a clear path
for the light in the stepper/scanner systems to travel through.
Resolution in projection systems
The ability to project a clear image of a
small feature onto the wafer is limited by
the wavelength of the light that is used,
and the ability of the reduction lens system
to capture enough diffraction orders from
state-of-the-art photolithography tools use
wavelengths of 248 and 193 nm, which
allow minimum feature sizes down to
50 nm.
The minimum feature size that a projection
system can print is given approximately by:
The filtered fluorescent lighting in photolithography
cleanrooms contains no ultraviolet or blue light in
order to avoid exposing photoresists. The spectrum of
light emitted by such fixtures gives virtually all such
spaces a bright yellow color.
is the minimum feature size (also called the critical dimension, target design rule). It
is also common to write 2 times the half-pitch.
(commonly called k1 factor) is a coefficient that encapsulates process-related factors,
and typically equals 0.4 for production
is the wavelength of light used
is the numerical aperture of the lens as seen from the wafer
According to this equation, minimum feature sizes can be decreased by decreasing the
wavelength, and increasing the numerical aperture (to achieve a tighter focused beam and
a smaller spot size). However, this design method runs into a competing constraint. In
modern systems, the depth of focus is also a concern:
is another process-related coefficient. The depth of focus restricts the thickness of
the photoresist and the depth of the topography on the wafer. Chemical mechanical
polishing is often used to flatten topography before high-resolution lithographic steps.
Light sources
Historically, photolithography has
combination with noble gases such
as xenon. These lamps produce
light across a broad spectrum with
several strong peaks in the
ultraviolet range. This spectrum is
filtered to select a single spectral
line, usually the "g-line" (436 nm)
or "i-line" (365 nm).
produced by excimer lasers. (In
lithography, wavelengths below
300 nm are called "deep UV".)
The evolution of lithography wavelength corresponding to
different light sources. It is worth noting that the same light
source may be used for several technology generations.
248-nm spectral line, and argon
fluoride a 193-nm line. Generally,
changing wavelength is not a trivial matter, as the method of generating the new
wavelength is completely different, as well as the absorption by different materials. Air
begins to absorb significantly around the 193 nm wavelength; moving to shorter
wavelengths would require installing vacuum pump and purge equipment on the
lithography tools (a significant expense). Furthermore, insulating materials such as silicon
dioxide (SiO2), when exposed to photons with energy greater than the band gap, release
free electrons and holes which subsequently cause adverse charging.
Optical lithography can be extended to feature sizes below 50 nm using 193 nm and liquid
immersion techniques. Also termed immersion lithography, this enables the use of optics
with numerical apertures exceeding 1.0. The liquid used is typically ultra-pure, deionised
water, which provides for a refractive index above that of the usual air gap between the
lens and the wafer surface. This is continually circulated to eliminate thermally-induced
distortions. Water will only allow NA's of up to ~1.4, but materials with higher refractive
indices will allow the effective NA to be increased further.
Changing the lithography wavelength is significantly limited by
absorption. Air absorbs below ~ 185 nm.
Tools using 157 nm wavelength
DUV in a manner similar to
current exposure systems have
been developed. These were once
targeted to succeed 193 nm at the
65 nm feature size node but have
now all but been eliminated by the
lithography. This was due to
persistent technical problems with
157 nm
provided strong incentives for the
193 nm
technology. High-index immersion
extension of 193 nm lithography to
be considered. In 2006, features
30 nm
demonstrated by IBM using this technique.[3]
Experimental methods
Photolithography has been defeating predictions of its demise for many years. For instance,
it was predicted that features smaller than 1 micrometre could not be printed optically.
Modern techniques already print features with dimensions a fraction of the wavelength of
light used - an amazing optical feat. Current research is exploring new tricks in the
ultraviolet regime, as well as alternatives to conventional UV, such as electron beam
lithography, X-ray lithography, extreme ultraviolet lithography, ion projection lithography,
and immersion lithography.
See also
• Alternative types of lithography
• nanoimprint lithography
• dip-pen nanolithography
• soft lithography
• Magnetolithography
• computational lithography
• stereolithography, a macroscale process used to produce three-dimensional shapes
• wafer foundry
[1] Jaeger, Richard C. (2002). "Lithography". Introduction to Microelectronic Fabrication. Upper Saddle River:
Prentice Hall. ISBN 0-201-44494-7.
[2] Nalamasu, Omkaram, et al.. " An Overview of Resist Processing for DUV Photolithography (http:/ / www.
journalarchive. jst. go. jp/ jnlpdf. php?cdjournal=photopolymer1988& cdvol=4& noissue=3& startpage=299&
lang=en& from=jnlabstract)". .
[3] Hand, Aaron. " High-Index Lenses Push Immersion Beyond 32 nm (http:/ / www. reed-electronics. com/
semiconductor/ article/ CA6319061)". .
• Eli Yablonovitch, Rutger B. Vrijen, <Optical projection lithography at half the Rayleigh
resolution limit by two-photon exposure> http:/ / www. ee. ucla. edu/ labs/ photon/ pubs/
ey1999oe382. pdf
• Model Car Tech, http:/ / modeltech. tripod. com/ etching. htm
External links
• BYU Photolithography Resources (http:/ / www. ee. byu. edu/ cleanroom/ lithography.
• Semiconductor Lithography (http:/ / www. lithoguru. com/ scientist/ lithobasics. html) —
Overview of lithography
• Optical Lithography Introduction (http:/ / www. research. ibm. com/ journal/ rd/ 411/
chiu. html) — IBM site with lithography-related articles
• Immersion Lithography Article (http:/ / sst. pennnet. com/ Articles/ Article_Display.
cfm?Section=ARCHI& Subsection=Display& ARTICLE_ID=205024& p=28) — Shows
how depth-of-focus is increased with immersion lithography
Thermal oxidation
Thermal oxidation
In → microfabrication, thermal oxidation
is a way to produce a thin layer of oxide
(usually silicon dioxide) on the surface of a
wafer (semiconductor). The technique
forces an oxidizing agent to diffuse into the
wafer at high temperature and react with it.
The rate of oxide growth is often predicted
by the → Deal-Grove model. Thermal
oxidation may be applied to different
materials, but this article will only consider
oxidation of silicon substrates to produce
silicon dioxide.
The chemical reaction
performed at a temperature between 800
and 1200°C, resulting in so called High
Temperature Oxide layer (HTO). It may
use either water vapor (steam) or molecular
oxygen as the oxidant; it is consequently
called either wet or dry oxidation. The
reaction is one of the following:
Furnaces used for diffusion and thermal oxidation at
LAAS technological facility in Toulouse, France.
The oxidizing ambient may also contain several percent of hydrochloric acid (HCl). The
chlorine removes metal ions that may occur in the oxide.
Thermal oxide incorporates silicon consumed from the substrate and oxygen supplied from
the ambient. Thus, it grows both down into the wafer and up out of it. For every unit
thickness of silicon consumed, 2.27 unit thicknesses of oxide will appear[1] . Conversely, if a
bare silicon surface is oxidized, 46% of the oxide thickness will lie below the original
surface, and 54% above it.
Thermal oxidation
Deal-Grove model
According to the commonly-used Deal-Grove model, the time t required to grow an oxide of
thickness Xo, at a constant temperature, on a bare silicon surface, is:
where the constants A and B encapsulate the properties of the reaction and the oxide layer,
If a wafer that already contains oxide is placed in an oxidizing ambient, this equation must
be modified by adding a corrective term τ, the time that would have been required to grow
the pre-existing oxide under current conditions. This term may be found using the equation
for t above.
Solving the quadratic equation for Xo yields:
Oxidation technology
Most thermal oxidation is performed in furnaces, at temperatures between 800 and 1200°C.
A single furnace accepts many wafers at the same time, in a specially designed quartz rack
(called a "boat"). Historically, the boat entered the oxidation chamber from the side (this
design is called "horizontal"), and held the wafers vertically, beside each other. However,
many modern designs hold the wafers horizontally, above and below each other, and load
them into the oxidation chamber from below.
Vertical furnaces stand higher than horizontal furnaces, so they may not fit into some
microfabrication facilities. However, they help to prevent dust contamination. Unlike
horizontal furnaces, in which falling dust can contaminate any wafer, vertical furnaces only
allow it to fall on the top wafer in the boat.
Vertical furnaces also eliminate an issue that plagued horizontal furnaces: non-uniformity of
grown oxide across the wafer. Horizontal furnaces typically have convection currents inside
the tube which causes the bottom of the tube to be slightly colder than the top of the tube.
As the wafers lie vertically in the tube the convection and the temperature gradient with it
causes the top of the wafer to have a thicker oxide than the bottom of the wafer. Vertical
furnaces solve this problem by having wafer sitting horizontally, and then having the gas
flow in the furnace flowing from top to bottom, significantly dampening any thermal
Vertical furnaces also allow the use of load locks to purge the wafers with nitrogen before
oxidation to limit the growth of native oxide on the Si surface.
Oxide quality
Wet oxidation is preferred to dry oxidation for growing thick oxides, because of the higher
growth rate. However, fast oxidation leaves more dangling bonds at the silicon interface,
which produce quantum states for electrons and allow current to leak along the interface.
(This is called a "dirty" interface.) Wet oxidation also yields a lower-density oxide, with
lower dielectric strength.
Thermal oxidation
The long time required to grow a thick oxide in dry oxidation makes this process
impractical. Thick oxides are usually grown with a long wet oxidation bracketed by short
dry ones (a dry-wet-dry cycle). The beginning and ending dry oxidations produce films of
high-quality oxide at the outer and inner surfaces of the oxide layer, respectively.
Mobile metal ions can degrade performance of MOSFETs (sodium is of particular concern).
However, chlorine can immobilize sodium by forming sodium chloride. Chlorine is often
introduced by adding hydrogen chloride or trichloroethylene to the oxidizing medium. Its
presence also increases the rate of oxidation.
Other notes
• Thermal oxidation can be performed on selected areas of a wafer, and blocked on others.
Areas which are not to be oxidized are covered with a film of silicon nitride, which blocks
diffusion of oxygen and water vapor. The nitride is removed after oxidation is complete.
This process cannot produce sharp features, because lateral (parallel to the surface)
diffusion of oxidant molecules under the nitride mask causes the oxide to protrude into
the masked area.
• Because impurities dissolve differently in silicon and oxide, a growing oxide will
selectively take up or reject dopants. This redistribution is governed by the segregation
coefficient, which determines how strongly the oxide absorbs or rejects the dopant, and
the diffusivity.
• The orientation of the silicon crystal affects oxidation. A <100> wafer (see Miller indices)
oxidizes more slowly than a <111> wafer, but produces an electrically cleaner oxide
• Thermal oxidation of any variety produces a higher-quality oxide, with a much cleaner
interface, than → chemical vapor deposition of oxide resulting in Low Temperature
Oxide layer (reaction of TEOS at about 600 °C). However, the high temperatures
required to produce High Temperature Oxide (HTO) restrict its usability. For instance, in
MOSFET processes, thermal oxidation is never performed after the doping for the source
and drain terminals is performed, because it would disturb the placement of the dopants.
[1] http:/ / www. siliconfareast. com/ oxidation2. htm
• Jaeger, Richard C. (2001). "Thermal Oxidation of Silicon". Introduction to Microelectronic
Fabrication. Upper Saddle River: Prentice Hall. ISBN 0-201-44494-1.
External links
• Oxide growth time calculator (http:/ / www. ee. byu. edu/ cleanroom/ OxideTimeCalc.
• Online calculator including deal grove and massoud oxidation models, with pressure and
doping effects at: http:/ / www. lelandstanfordjunior. com/ thermaloxide. html
Wafer testing
Wafer testing
Wafer testing is a step performed during semiconductor device fabrication. During this
step, performed before a wafer is sent to → die preparation, all individual integrated
circuits that are present on the wafer are tested for functional defects by applying special
test patterns to them. The wafer testing is performed by a piece of test equipment called a
→ wafer prober. The process of wafer testing can be referred to in several ways: Wafer Sort
(WS), Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are
probably the most common. [1]
The wafer prober also exercises any test circuitry on the wafer scribe lines. Some
companies get most of their information about device performance from these scribe line
test structures.[2] [3] [4]
When all test patterns pass for a specific die, its position is remembered for later use
during → IC packaging. Sometimes a die has internal spare resources available for
repairing (i.e. flash memory IC); if it does not pass some test patterns these spare resources
can be used. If redundancy of failed die is not possible the die is considered faulty and is
discarded. Non-passing circuits are typically marked with a small dot of ink in the middle of
the die, or the information of passing/non-passing is stored in a file, named a wafermap.
This map categorizes the passing and non-passing dies by making use of bins. A bin is then
defined as a good or bad die. This wafermap is then sent to the → die attachment process
which then only picks up the passing circuits by selecting the bin number of good dies. The
process where no ink dot is used to mark the bad dies is named → substrate mapping. When
ink dots are used, vision systems on subsequent die handling equipment can disqualify the
die by recognizing the ink dot.
In some very specific cases, a die that passes some but not all test patterns can still be used
as a product, typically with limited functionality. The most common example of this is a
microprocessor for which only one part of the on-die cache memory is functional. In this
case, the processor can sometimes still be sold as a lower cost part with a smaller amount
of memory and thus lower performance. Additionally when bad dies have been identified,
the die from the bad bin can be used by production personnel for assembly line setup.
The contents of all test patterns and the sequence by which they are applied to an
integrated circuit are called the test program.
After IC packaging, a packaged chip will be tested again during the IC testing phase,
usually with the same or very similar test patterns. For this reason, one might think that
wafer testing is an unnecessary, redundant step. In reality this is not usually the case, since
the removal of defective dies saves the considerable cost of packaging faulty devices.
However, when the production yield is so high that wafer testing is more expensive than
the packaging cost of defect devices, the wafer testing step can be skipped altogether and
dies will undergo blind assembly.
Wafer testing
Fundamentals of Digital Semiconductor Testing(Version 4.0) by Guy A. Perry (Spiral-bound
- Mar 1, 2003)
Principles of Semiconductor Network Testing (Test & Measurement) (Hardcover)by Amir
Power-Constrained Testing of VLSI Circuits (Frontiers in Electronic Testing) by Nicola
Nicolici and Bashir M. Al-Hashimi (Kindle Edition - Feb 28, 2003)
Semiconductor Memories: Technology, Testing, and Reliability by Ashok K. Sharma
(Hardcover - Sep 9, 2002)
See also
• → Wafer prober
• → Non-contact wafer testing
[1] " Silicon Wafer Technology (http:/ / www. maviye. com/ comments. asp?id=67)". . Retrieved 2008-02-23.
[2] "Startup enables IC variability characterization" (http:/ / www. eetasia. com/
ART_8800419948_480100_NT_648c3def. HTM) by Richard Goering 2006
[3] "Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry" (http:/ / www2. computer. org/ portal/
web/ csdl/ doi/ 10. 1109/ ATS. 2008. 68) (abstract)
[4] Design for Manufacturability And Statistical Design: A Constructive Approach, by Michael Orshansky, Sani
Nassif, Duane Boning 2007. ISBN 0387309284 ISBN 9780387309286 (http:/ / books. google. com/
books?id=sZ-NPuM-ScYC& pg=PA84& lpg=PA84& dq=scribe+ line+ test+ structures& source=bl&
ots=uH52TiBixk& sig=LSHJm1EkcT07D-mysd8d419NyH8& hl=en& ei=-fyLSqrbJ5PclAf99ty7CA& sa=X&
oi=book_result& ct=result& resnum=10#v=onepage& q=scribe line test structures& f=false) p. 84
Amkor RF Wafer Probe Test Development (http:/ / www. amkor. com/ go/ test-services/
Wafer prober
Wafer prober
A wafer prober is a machine used to test integrated circuits.
Integrated circuits are fabricated in large numbers by a complex series of printing steps on
silicon → wafers. This process permits integrated circuits to be produced cheaply but each
chip must be tested prior to its separation from the wafer (using a process known as →
wafer dicing). The testing of the wafer in this process is also known as wafer sort.
For electrical testing a set of microscopic contacts or probes called a Probe card are held in
place whilst the wafer, vacuum-mounted on a Wafer Chuck, is moved into electrical contact.
When a die (or array of dice) have been electrically tested the prober moves the wafer to
the next die (or array) and the next test can start. The Wafer Prober is usually responsible
for loading and unloading the wafers from their carrier (or cassette) and is equipped with
automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy
to ensure accurate registration between the contact pads on the wafer and the tips of the
Fundamentals of Digital Semiconductor Testing(Version 4.0) by Guy A. Perry (Spiral-bound
- Mar 1, 2003)
Principles of Semiconductor Network Testing (Test & Measurement) (Hardcover)by Amir
Power-Constrained Testing of VLSI Circuits (Frontiers in Electronic Testing) by Nicola
Nicolici and Bashir M. Al-Hashimi (Kindle Edition - Feb 28, 2003)
Semiconductor Memories: Technology, Testing, and Reliability by Ashok K. Sharma
(Hardcover - Sep 9, 2002)
Non-contact wafer testing
Non-contact wafer testing
Traditional (contact) wafer testing
→ Wafer testing is a normal step in → semiconductor device fabrication, used to detect
defects in integrated circuits (IC) before they are assembled during the IC packaging step.
However, probing these ICs while they are still on the wafer normally requires that contact
be made between the automatic test equipment (ATE) and IC. This contact is usually made
with some form of mechanical probe. A set of mechanical probes will often be arranged
together on a probe card, which is attached to the wafer prober. The wafer is lifted by the
wafer prober until metal pads on one or more ICs on the wafer make physical contact with
the probes. A certain amount of over-travel is required after the first probe makes contact
with the wafer, for two reasons:
• to guarantee that all probes have made contact (to account for non-planarity of the
• to break through the thin oxidized layer (if the metal pad is Aluminum) on the pad
There are numerous types of mechanical probes available commercially: their shape can be
in the form of a cantilever, spring, or membrane, and they can be bent into shape, stamped,
or made by MEMS processing.
Using mechanical probes has certain drawbacks:
• mechanical probing can damage the circuits under the probe pad on the IC
• repeated probing can damage [2] the probe pad on the IC, making further probing of that
IC impossible
• the probe card may be damaged from repeated contact, or become contaminated with
debris created by contact with the wafer[3]
• the probe will act as a circuit and affect the results of the test. For this reason, the tests
performed at wafer sort cannot always be identical and as extensive as those performed
at the final device test after packaging is complete [4]
• since the probe pads are typically on the perimeter of the IC, the IC can soon become
• shrinking pad sizes makes design & manufacturing of smaller & more accurate probes a
Non-contact (wireless) wafer testing
Alternatives to mechanical probing of ICs have been explored by various groups ( Slupsky[5]
, Moore[6] , Scanimetrics[7] , Kuroda[8] ). These methods use tiny RF antennae (similar to
RFID tags, but on a much smaller scale) to replace both the mechanical probes and the
metal probe pads. If the antennae on the probe card and IC are properly aligned, then a
transmitter on the probe card can send data wirelessly to the receiver on the IC via RF
This method has several advantages:
• no damage is done to circuits, pads, nor probe cards
• no debris is created
• probe pads are no longer required, on the periphery of the IC
• wireless probe points can be placed anywhere on the IC, not just on the periphery
Non-contact wafer testing
• repeated probing is possible without damaging the probe points
• faster data rates are possible than with mechanical probes
• the wafer prober does not have to exert any force on the probe location (in traditional
probing this can be a significant amount of force, when hundreds or thousands of probes
are used)
[1] " Test & Measurement World (http:/ / www. tmworld. com/ article/ CA6436545. html)". Probe-mark inspection.
[2] http:/ / images. pennnet. com/ articles/ sst/ thm/ th_0707sstprocess01. jpg
[3] " Test & Measurement World (http:/ / www. tmworld. com/ article/ CA187445. html)". Investigation Conquers
Probe-Card Problems. .
[4] " StatsChipPac (http:/ / www. statschippac. com/ services/ testservices/ wafersort. aspx)". Wafer Sort. .
[5] " Slupsky, Steven (http:/ / patft. uspto. gov/ netacgi/ nph-Parser?Sect1=PTO1& Sect2=HITOFF& d=PALL&
p=1& u=/ netahtml/ PTO/ srchnum. htm& r=1& f=G& l=50& s1=6885202. PN. & OS=PN/ 6885202& RS=PN/
6885202)". Non-contact tester for electronic circuits. .
[6] " Moore, Brian (http:/ / patft. uspto. gov/ netacgi/ nph-Parser?Sect1=PTO1& Sect2=HITOFF& d=PALL& p=1&
u=/ netahtml/ PTO/ srchnum. htm& r=1& f=G& l=50& s1=6759863. PN. & OS=PN/ 6759863& RS=PN/
6759863)". Wireless radio frequency technique design and method for testing of integrated circuits and wafers.
[7] " Scanimetrics (http:/ / www. scanimetrics. com)". Scanimetrics, Inc. provides non-contact test solutions to the
semiconductor industry. .
[8] " Kuroda, Tadahiro (http:/ / www. wipo. int/ pctdb/ en/ wo. jsp?WO=2008056739)". System debug method
using a wireless communication interface. .
Die preparation
Die preparation is a step of semiconductor device
fabrication during which a → wafer is prepared for IC
packaging and IC testing. The process of die
preparation typically consists of 2 steps: wafer
mounting and → wafer dicing.
Wafer mounting
Wafer mounting is a step that is performed during the
die preparation of a → wafer as part of the process of
Wafer glued on blue tape and cut into
semiconductor fabrication. During this step, the wafer
is mounted on a plastic tape that is attached to a ring.
Wafer mounting is performed right before the wafer is
cut into separate dice. The adhesive tape on which the wafer is mounted ensures that the
individual dice remain firmly in place during 'dicing', as the process of cutting the wafer is
The picture below shows a 200 mm wafer after it was mounted and diced. The blue plastic
is the adhesive tape. The wafer is the round disc in the middle. In this case, a large number
of dice were already removed.
Die preparation
Semiconductor-die cutting
In the manufacturing of micro-electronic devices, die cutting or dicing is a process of
reducing a → wafer containing multiple identical integrated circuits to dice each containing
one of those circuits.
During this process, a wafer with up to thousands of circuits is cut into individual pieces,
each called a die. In between the functional parts of the circuits, a thin non-functional
spacing is foreseen where a saw can safely cut the wafer without damaging the circuit. This
spacing is called the scribe or saw street. The width of the scribe is very small, typically
around 100 μm. A very thin and accurate saw is therefore needed to cut the wafer into
pieces. Usually the dicing is performed with a water-cooled circular saw with
diamond-tipped teeth.
Types of blades
The most common make up of blade used is either a metal or resin bond containing
abrasive grit of natural or more commonly synthetic diamond, or borazon in various forms.
Alternatively, the bond and grit may be applied as a coating to a metal former. Link to
diamond tools.
Integrated circuit packaging
Integrated circuit packaging is the final stage of
semiconductor device fabrication per se, followed by IC
In the integrated circuit industry it is called simply
packaging and sometimes semiconductor device
assembly, or simply assembly. Also, sometimes it is
called → encapsulation or seal, by the name of its last
step, which might lead to confusion, because the term
packaging generally comprises the steps or the
technology of mounting and interconnecting of devices
(see Chip carrier, Category:Chip carriers).
Early USSR made integrated circuit
The earliest integrated circuits were packaged in ceramic flat packs, which continued to be
used by the military for their reliability and small size for many years. Commercial circuit
packaging quickly moved to the dual in-line package (DIP), first in ceramic and later in
plastic. In the 1980s pin counts of VLSI circuits exceeded the practical limit for DIP
packaging, leading to pin grid array (PGA) and leadless chip carrier (LCC) packages.
Surface mount packaging appeared in the early 1980s and became popular in the late
1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified
by small-outline integrated circuit — a carrier which occupies an area about 30 – 50% less
than an equivalent DIP, with a typical thickness that is 70% less. This package has "gull
wing" leads protruding from the two long sides and a lead spacing of 0.050 inches.
Integrated circuit packaging
Small-outline integrated circuit (SOIC) and Plastic leaded chip carrier (PLCC) packages. In
the late 1990s, plastic quad flat pack(PQFP) and thin small-outline packages (TSOP)
became the most common for high pin count devices, though PGA packages are still often
used for high-end microprocessors. Intel and AMD are currently transitioning from PGA
packages on high-end microprocessors to land grid array (LGA) packages.
Ball grid array (BGA) packages have existed since the 1970s. Flip-chip Ball Grid Array
packages, which allow for much higher pin count than other package types, were developed
in the 1990s. In an FCBGA package the die is mounted upside-down (flipped) and connects
to the package balls via a package substrate that is similar to a printed-circuit board rather
than by wires. FCBGA packages allow an array of input-output signals (called Area-I/O) to
be distributed over the entire die rather than being confined to the die periphery.
Traces out of the die, through the package, and into the printed circuit board have very
different electrical properties, compared to on-chip signals. They require special design
techniques and need much more electric power than signals confined to the chip itself.
When multiple dies are stacked in one package, it is called SiP, for System In Package, or →
three-dimensional integrated circuit. When multiple dies are combined on a small
substrate, often ceramic, it's called an MCM, or Multi-Chip Module. The boundary between
a big MCM and a small printed circuit board is sometimes fuzzy.
The following operations are performed at the stage of packaging.
• Die attaching
• IC Bonding
• → Wire bonding
• Down bonding
• → Flip chip
• → Quilt packaging
• Tab bonding
• Film attaching
• Spacer attaching
• IC encapsulation
→ Plating
Trim and form
Unusual packaging
The vast majority of integrated circuits are packaged in opaque ceramic or plastic
insulation. The only connection to the outside world is through metal pins (sometimes
called "leads") through the insulation.
The rare exceptions include proximity communication [1] ; "blob on PCB" that attaches the
raw die directly to a PCB, bonds the die wires directly to the PCB traces, then covers the
die and the die wires with a blob of insulator; and partially or totally transparent packaging
for optical input and/or output of optoelectronic devices and EPROM.
Integrated circuit packaging
See also
Chip carrier
→ B-staging
Potting (electronics)
→ Quilt packaging
Electronic packaging
External links
• Wikihowto on identifying chip packages
• The Nordic Electronics Packaging Guideline [3] Investigation on the technical
performance of different packaging and interconnection systems
[1] "Proximity Communication" (http:/ / research. sun. com/ spotlight/ 2004-09-20. feature-proximity. html)
[2] http:/ / howto. wikia. com/ wiki/ Howto_identify_chip_packages
[3] http:/ / extra. ivf. se/ ngl/
Die attachment
Die attachment is the step during the →
integrated circuit packaging phase of
semiconductor device fabrication during
which a die is mounted and fixed to the
package or support structure.
For high-powered applications, the die is
Die attachment process (Photo by Creative Materials
usually eutectic bonded onto the package
(for good heat conduction). For low-cost,
low-powered applications, the die is often
glued directly onto a substrate (such as a printed wiring board) using an epoxy adhesive.
External links
• Related machines for die attach
• Oerlikon Esec, global provider of chip assembly equipment and system solutions for the
semiconductor industry [3]
[1] http:/ / www. creativematerials. com
[2] http:/ / www. finetech. de/ enid/ 535153298e55179581806996fb1e4c79,0/ Micro_Assembly_Equipment/
FINEPLACER__Lambda__Flip_Chip_/ _Die_Bonder__36. html
[3] http:/ / www. oerlikon. com/ ecomaXL/ index. php?site=ESEC_EN_products
Wire bonding
Wire bonding
Wire bonding is the primary method of
integrated circuit (IC) and a printed circuit
board (PCB) during semiconductor device
fabrication. Although less common, wire
bonding can be used to connect an IC to
other electronics or to connect from one
PCB to another. Wire bonding is generally
considered the most cost-effective and
flexible interconnect technology, and is
used to assemble the vast majority of
semiconductor packages.
Gold wire ball-bonded to a gold contact pad
Bondwires usually consist of one of the
following materials:
• Gold
• Aluminum
• Copper
Wire diameters start at 15 µm and can be
up to several hundred micrometres for
high-powered applications.
Copper wire has become one of the
preferred materials for wire bonding
interconnects in many semiconductor and
microelectronic applications. Copper is
used for fine wire ball bonding in sizes up
to 0.003 inch (75 microns). Copper wire
has the ability of being used at smaller
diameters providing the same performance
as gold without the high material cost.[1]
Aluminium wires wedge-bonded to a KSY34 transistor
Copper wire up to 0.010 inch (250 microns)
can be successfully wedge bonded with the
proper set-up parameters. Large diameter
copper wire can and does replace
aluminum wire where high current carrying
capacity is needed or where there are
The interconnections in a power package are made
Annealing and process steps used by
using thick (250 to 400 µm), wedge-bonded,
manufacturers enhance the ability to use
aluminium wires.
large diameter copper wire to wedge bond
to silicon without damage occurring to the die.[1]
Copper wire does pose some challenges in that it is harder than both gold and aluminum, so
bonding parameters must be kept under tight control. The formation of oxides is inherent
Wire bonding
with this material, so storage and shelf life are issues that must be considered. Special
packaging is required in order to protect copper wire and achieve a longer shelf life.[1]
Pure gold wire doped with controlled amounts of beryllium and other elements is normally
used for → ball bonding. This process brings together the two materials that are to be
bonded using heat, pressure and ultrasonic energy. The most common approach in
thermosonic bonding is to ball-bond to the chip, then stitch-bond to the substrate. Very
tight controls during our processing enhance looping characteristics and eliminate sagging.
Junction size, bond strength and conductivity requirements typically determine the most
suitable wire size for a specific wire bonding application. Typical manufacturers make gold
wire in diameters from 0.0005 inch (12.5 microns) and larger. Production tolerance on gold
wire diameter is +/-3%. [2]
Alloyed aluminum wires are generally preferred to pure aluminum wire except in
high-current devices because of greater drawing ease to fine sizes and higher pull-test
strengths in finished devices. Pure aluminum and 0.5% magnesium-aluminum are most
commonly used in sizes larger than 0.004 inch.
All aluminum systems in semiconductor fabrication eliminate the "purple plague" (brittle
gold-aluminum intermetallic compound) sometimes associated with pure gold bonding wire.
Aluminum is particularly suitable for ultrasonic bonding.
In order to assure that high quality bonds can be obtained at high production speeds,
special controls are used in the manufacture of 1% silicon-aluminum wire. One of the most
important characteristics of high grade bonding wire of this type is homogeneity of the
alloy system. Homogeneity is given special attention during the manufacturing process.
Microscopic checks of the alloy structure of finished lots of 1% silicon-aluminum wire are
performed routinely. Processing also is carried out under conditions which yield the
ultimate in surface cleanliness and smooth finish and permits entirely snag-free de-reeling.
There are two main classes of wire bonding:
• → Ball bonding
• Wedge bonding
Ball bonding usually is restricted to gold and copper wire and usually requires heat. Wedge
bonding can use either gold or aluminum wire, with only the gold wire requiring heat.
In either type of wire bonding, the wire is attached at both ends using some combination of
heat, pressure, and ultrasonic energy to make a weld.
See also
purple plague (intermetallic)
→ ball bonding
silver epoxy
eutectic bonding process
thermosonic bonding
gold ribbon bonding
parallel gap welding
[1] http:/ / www. coininginc. com/ Copper_Wire. asp
[2] http:/ / www. coininginc. com/ gold_wire_and_ribbon. asp
[3] http:/ / www. coininginc. com/ aluminum_and_silicon_ribbon. asp
Flip chip
Flip chip
Flip chip, also known as Controlled Collapse Chip Connection or its acronym, C4, is a
method for interconnecting semiconductor devices, such as IC chips and MEMS, to external
circuitry with solder bumps that have been deposited onto the chip pads. The solder bumps
are deposited on the chip pads on the top side of the wafer during the final → wafer
processing step. In order to mount the chip to external circuitry (e.g., a circuit board or
another chip or wafer), it is flipped over so that its top side faces down, and aligned so that
its pads align with matching pads on the external circuit, and then the solder is flowed to
complete the interconnect. This is in contrast to → wire bonding, in which the chip is
mounted upright and wires are used to interconnect the chip pads to external circuitry.
Process steps
• Integrated circuits are created on the wafer
• Pads are metalized on the surface of the chips
• Solder dots are deposited on each of the pads
• Chips are cut
• Chips are flipped and positioned so that the solder balls are facing the connectors on the
external circuitry
• Solder balls are then remelted (typically using hot air reflow)
• Mounted chip is “underfilled” using an electrically-insulating adhesive
Flip chip
Comparison of mounting technologies
Wire bonding
systems chips are built up in large numbers
on a single large "wafer" of semiconductor
material, typically silicon. The individual
chips are patterned with small pads of
metal near their edges that serve as the
connections to an eventual mechanical
carrier. The chips are then cut out of the
wafer and attached to their carriers,
The interconnections in a power package are made
typically with small wires (see → wire
using thick aluminium wires (250 to 400 µm)
bonding). These wires eventually lead to
pins on the outside of the carriers, which
are attached to the rest of the circuitry making up the electronic system.
Flip chip
The processing of a flip chip is similar to
conventional IC fabrication with the
addition of a few steps.[1] Near the end of
the process the attachment pads are
"metalized" to make them more suitable for
being soldered onto. This typically consists
of several treatments. A small dot of solder
is then deposited on each of the pads. The
chips are then cut out of the wafer as normal.
Side-view schematic of a typical flip chip mounting
Recently high speed mounting methodology evolved through a co-operation between Reel
Service Ltd. and Siemens AG in the development of a high speed mounting tape known as
'MicroTape.'[2]. By adding a tape and reel process into the assembly methodology,
placement at high speed, typically 20,000 placements per hour are achievable using
standard PCB assembly equipment, much to the delight of the mobile handset industry.
To attach the flip chip into a circuit, it is inverted to bring the solder dots down onto
connectors on the underlying electronics or circuit board. The solder is then re-melted to
produce an electrical connection, typically using an ultrasonic or alternatively reflow solder
process. This also leaves a small space between the chip's circuitry and the underlying
mounting. In most cases an electrically-insulating adhesive is then "underfilled" to provide
a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are
not stressed due to differential heating of the chip and the rest of the system.
Flip chip
The resulting completed flip chip assembly is much smaller than a traditional carrier-based
system; the chip sits directly on the circuit board, and is much smaller than the carrier both
in area and height. The short wires greatly reduce inductance, allowing higher-speed
signals, and also carry heat better.
Flip chips have several disadvantages as well. The lack of a carrier means they are not
suitable for easy replacement, or manual installation. They also require very flat surfaces to
mount to, which is not always easy to arrange, or sometimes difficult to maintain as the
boards heat and cool. Also, the short connections are very stiff, so the thermal expansion of
the chip must be matched to the supporting board or the connections can crack.[3]
The process was originally introduced commercially by IBM in the 1960s for ICs being used
in the mainframe systems.[4] DEC followed IBM's lead but was unable to achieve the quality
they demanded, and eventually gave up on the concept. In the 1970s it was taken up by
Delco Electronics, and has since become very common in automotive applications.
Since the flip chip's introduction a number of alternatives to the solder bumps have been
introduced, including gold balls or molded studs, electrically conductive plastics, and the
"plated bump" process that removes an insulating plating by chemical means. Flip chips
have recently gained popularity among manufacturers of cell phones, pagers and other
small electronics where the size savings are valuable.
See also
• Solid Logic Technology
• Wikihowto: Guide to IC packages
• “Challenges in the Assembly of Large Die, High Bump Density Pb-Free Flip Chip
Packages”, J. Libres, K. Robinson , Int’l Electronics Manufacturing Technology
Symposium 2007 p. 346
• “Thermal and Mechanical Behaviors of Underfills for Flip-Chip Packaging”, H. Wu, C.
Poo, L. Waf, and W. Mee, Electronics Packaging Technology Conference 2005 p. 842
• “Flip Chip Processing Using Wafer-Applied Underfills”, S. Busch and D. Baldwin [Ga
Tech], Electronic Components and Technology Conference 2005 p. 297
• “The effect of underfill imperfections on the reliability of flip chip modules: FEM
simulations and experiments”, S. Rzepka, F. feustel, E. Meusel, M. Korhonen and C. Li,
1998 Electronic Components and Technology Conference p. 362
• “Manufacturing Multichip Modules”, p. 391ff, by Rakesh Agarwal and Michael Pecht, in
Physical Architecture of VLSI Systems, ed. Robert J. Hannemann, Allan D. Kraus and
Michael Pecht; John Wiley & Sons Inc., New York (1994)
• “Solderable Contacts for Flip Chip Integrated Circuit Devices”, William D. Higdon, Susan
Mach, and Ralph Cornell, US Patent 5,547,740, Aug 20, 1996
Flip chip
• “Solder jet printing of micropads and vertical interconnects”, Wallace, D.B.; Hayes, D.J.,
SMTA National Symposium, Emerging Technologies. Proceeding of the Technical
Program Edina, MN, USA: Surface Mount Technol. Assoc, 1997. p.55-61 Conference:
Bloomington, MN, USA, 20-23 Oct 1997
• “Advanced solder flip chip processes” , Rinne, G.; Koopman, N.; Magill, P.; Nangalia, S.;
Berry, C.; Mis, D.; Rogers, V.; Adema, G.; Berry, M.; Deane, P. SMI. Surface Mount
International. Advanced Electronics Manufacturing Technologies. Proceedings of The
Technical Program Edina, MN, USA: Surface Mount Technol. Assoc, 1996. p.282-92 vol.1
of 2 vol. 826 pp. Conference: San Jose, CA, USA, 10-12 Sept 1996
• “Solder Bump Transfer Device for Flip Chip Integrated Circuit Devices”, Shing Yeh,
William Higdon, Ralph Cornell, US Patent 5,607,099 Mar 4, 1997
• “Process for Converting a Wire Bond Pad to a Flip Chip Solder Bump Pad and Pad
Formed Thereby”, Curt Erickson, US Patent 5,891,756 April 6, 1999
• “Process for Manufacturing a Multilayer Bumped Semiconductor Device”, Kamaran
Manteghi, US Patent 5,863,812 Jan 26, 1999
• “Method of forming solder bumps”, Toshiharu Yanagida , US Patent 5,866,475; Feb. 2,
• “Flip-chip packaging for smart MEMS” , Mayer, F.; Ofner, G.; Koll, A.; Paul, O.; Baltes,
H., Proceedings of the SPIE (1998) vol.3328, p.183-93. Conference: Smart Structures and
Materials 1998: Smart Electronics and MEMS. San Diego, CA, USA, 2-4 March 1998
• “Wafer bumping technologies. A comparative analysis of solder deposition processes and
assembly considerations”, Patterson, D.S.; Elenius, P.; Leal, J.A., Advances in Electronic
Packaging 1997. Proceedings of the Pacific Rim/ASME International Intersociety
Electronic and Photonic Packaging Conference. INTERpack ASME, 1997. p.337-51
vol.1Conference: Kohala Coast, HI, USA, 15-19 June 1997
• “Solder Flip Chips Employing Electroless Nickel: An Evaluation of Reliability and Cost”,
F. Stepniak , Advances in Electronic Packaging 1997 p. 353 (EEP Vol 19-1), ASME 1997
• “Zincation characterization for electroless Ni/Au UBM of solder bumping technology”,
Tan, Q.; Beddingfield, C.; Mistry, A.; Mathew, V., Twenty Third IEEE/CPMT International
Electronics Manufacturing Technology Symposium,New York, NY, USA: IEEE, 1998.
p.34; Conference: Austin, TX, USA, 19-21 Oct 1998
• “Solder bumping methods for flip chip packaging”, Rinne, G.A., 1997 Proceedings. 47th
Electronic Components and Technology Conference IEEE, 1997. p.240 Conference: San
Jose, CA, USA, 18-21 May 1997
• “Flip-chip packaging with micromachined conductive polymer bumps”, Oh, K.W.; Ahn,
C.H. , Proceedings of 3rd International Conference on Adhesive Joining and Coating
Technology in Electronics Manufacturing 1998, p.224 Conference: Binghamton, NY, USA,
28-30 Sept 1998
• “Low cost solder flip chip”, Rinne, G.A.; Magill, P.A. , Proceedings. 3rd International
Symposium on Advanced Packaging Materials Processes, Properties and Interfaces 1997.
p.113 Conference: Braselton, GA, USA, 9-12 March 1997
• “Flip-chip packaging using micromachined conductive polymer bumps and alignment
pedestals for MOEMS”, Oh, K.W.; Ahn, C.H.; Roenker, K.P., IEEE Journal of Selected
Topics in Quantum Electronics (Jan.-Feb. 1999) vol.5, no.1, p.119
Flip chip
External links
Flip chip assembly videos [6]
Flip chip tutorials [7]
Flip Chip Assembly [8]
Flip Chip (C4) Benefits [9]
Kyocera America, Inc. - White Paper: Flip Chip Challenges [10]
A case for the application of MicroTape [11]
Pushing the barriers of wafer level device integration to higher assembly speed
Flip Chip Packaging Technology Solutions [12]
Molded Flip Chip - FCmBGA White Paper [13]
[1] Solder Bump Flip Chip (http:/ / www. flipchips. com/ tutorial02a. html)
[2] http:/ / www. epp-online. de/ epp/ live/ en/ fachartikelarchiv/ ha_artikel/ detail/ 31627038. html
[3] Demerjian, Charlie (2008-12-17), Nvidia chips show underfill problems (http:/ / www. theinquirer. net/
inquirer/ news/ 052/ 1050052/ nvidia-chips-show-underfill-problems), The Inquirer, , retrieved 2009-01-30
[4] Introduction to Flip Chip: What, Why, How (http:/ / www. flipchips. com/ tutorial01. html)
[5] http:/ / en. howto. wikia. com/ wiki/ Guide_to_IC_packages
[6] http:/ / www. finetech. de/ enid/ flipchip_videos
[7] http:/ / www. flipchips. com/ tutorials. html
[8] http:/ / www. siliconfareast. com/ flipchipassy. htm
[9] http:/ / www. articleworld. org/ index. php/ Flip_chip
[10] http:/ / americas. kyocera. com/ kai/ semiparts/ pdfs/ flipchip. pdf
[11] http:/ / www. reelservice. com/ pdf/ WLPAssemblyMicroTape. pdf
[12] http:/ / www. amkor. com/ go/ packaging/ all-packages/ flip-chip-packaging-technology-solutions/
[13] http:/ / www. amkor. com/ index. cfm?objectid=430121B4-5056-AA0A-E2086030E51A87AC
Quilt packaging
Quilt packaging
Quilt packaging is an electronic packaging technology
under research that allows microchips made of
dissimilar materials to be attached like squares in a
quilt. Chips are connected in a way that minimizes both
thermal stress and interchip delay times. The reflection
coefficient s11 has been measured at less than -25dB at
40GHz in high resistivity silicon. Connections between
microchips are made by thin metal lines which extend
over the edge of each chip.
Copper interconnects prepared for
joining via quilt packaging
The current process involves the etching and deposition
of silicon dioxide, evaporating and electroplating of
thick copper bumps, → Chemical-mechanical planarization of the copper, and the advanced
silicon etch process to separate into individual chips with undercut metal nodules extending
off the edges. The nodules can be joined together using ordinary lead-free soldering. [1]
[1] "Quilt packaging research website" http:/ / nd. edu/ ~kander19/ QP/ QuiltPackaging. htm
Integrated circuit encapsulation
Integrated circuit encapsulation (IC encapsulation, encapsulation) is the design and
manufacturing of protective packages for integrated circuits.
It is often the last stage of IC packaging (semiconductor package assembly) in
semiconductor device fabrication. The integrated circuit die is being encapsulated with
ceramic, plastic, or epoxy to prevent physical damage or corrosion.
Sometimes the term "encapsulation" is used synonymously to "packaging".
See also
• Potting (electronics)
Plating describes surface-covering where a metal is deposited on a conductive surface.
Plating has been done for hundreds of years, but it is also critical for modern technology.
Plating is used to decorate objects, for corrosion inhibition, to improve solderability, to
harden, to improve wearability, to reduce friction, to improve paint adhesion, to alter
conductivity, for radiation shielding, and for other purposes. Jewelry typically uses plating
to give a silver or gold finish. Thin-film deposition has plated objects as small as an atom,
therefore some plating is nanotechnology.
There are several plating methods, and many variations. In one method, a solid surface is
covered with a metal sheet, and then heat and pressure are applied to fuse them (a version
of this is Sheffield plate). Other plating techniques include vapor deposition under vacuum
and → sputter deposition. Recently, plating often refers to using liquids. Metallizing refers
to coating metal on non-metallic objects.
In electroplating, an ionic metal is supplied with electrons to form a non-ionic coating on a
substrate. A common system involves a chemical solution with the ionic form of the metal,
an anode (positively charged) which may consist of the metal being plated (a soluble anode)
or an insoluble anode (usually carbon, platinum, titanium, lead, or steel), and finally, a
cathode (negatively charged) where electrons are supplied to produce a film of non-ionic
Electroless plating
Electroless plating, also known as chemical or auto-catalytic plating, is a non-galvanic type
of plating method that involves several simultaneous reactions in an aqueous solution,
which occur without the use of external electrical power. The reaction is accomplished
when hydrogen is released by a reducing agent, normally sodium hypophosphite, and
oxidized thus producing a negative charge on the surface of the part. The most common
electroless plating method is electroless nickel plating.
Specific cases
Gold plating
Gold plating is a method of depositing a thin layer of gold on the surface of other metal,
most often copper or silver.
Gold plating is often used in electronics, to provide a corrosion-resistant electrically
conductive layer on copper, typically in electrical connectors and printed circuit boards.
With direct gold-on-copper plating, the copper atoms have the tendency to diffuse through
the gold layer, causing tarnishing of its surface and formation of an oxide/sulfide layer. A
layer of a suitable → barrier metal, usually nickel, has therefore to be deposited on the
copper substrate, forming a copper-nickel-gold sandwich.
Metals may also be coated with gold for ornamental purposes, using a number of different
processes usually referred to as gilding.
Silver plating
For less demanding applications in electronics, silver is often used as a cheaper
replacement for gold. (Although silver is a better conductor than gold it does oxidize and so
gold is better for contacts. However, variable capacitors are considered of the highest
quality when they have silver plated plates. In this application there is no make and break
contact so gold would not offer any advantage over silver).
Care should be used for parts exposed to high humidity environments. When the silver layer
is porous or contains cracks, the underlying copper undergoes rapid galvanic corrosion,
flaking off the plating and exposing the copper itself; a process known as red plague.
Historically, silver plate was used to provide a cheaper version of items that might
otherwise be made of silver, including cutlery and candlesticks. The earliest kind was Old
Sheffield Plate, but in the 19th century new methods of production (including
electroplating) were introduced: see Sheffield Plate.
Another method that can be used to apply a thin layer of silver to several objects, such as
glass, is the Tollen's Test method, which usually is prepared as follows. Using this method
the final reaction can occur by placing Tollen's Reagent in a glass and then adding
Glucose/Dextrose and shaking the bottle to perform the reaction.
AgNO3 + KOH -> AgOH + KNO3
AgOH + 2NH3 -> [Ag(NH3)2]1+ + [OH]1- (Note: See Tollen's Reagent)
[Ag(NH3)2]1+ + [OH]1- + Aldehyde(Usually Glucose/Dextrose) -> Ag + 2NH3 + H2O
Rhodium plating
Rhodium plating is occasionally used on white gold, silver or copper and its alloys. A barrier
layer of nickel is usually deposited on silver first, though in this case it is not to prevent
migration of silver through rhodium, but to prevent contamination of the rhodium bath with
silver and copper, which slightly dissolve in the sulfuric acid, usually present in the bath
Chrome plating
Chrome plating is a finishing treatment utilizing the electrolytic deposition of chromium.
The most common form of chrome plating is the thin, decorative bright chrome, which is
typically a 10-µm layer over an underlying nickel plate. When plating on iron or steel, an
underlying plating of copper allows the nickel to adhere. The pores (tiny holes) in the nickel
and chromium layers also promote corrosion resistance. Bright chrome imparts a
mirror-like finish to items such as metal furniture frames and automotive trim. Thicker
deposits, up to 1000 µm, are called hard chrome and are used in industrial equipment to
reduce friction and wear.
The traditional solution used for industrial hard chrome plating is made up of about 250 g/l
of CrO3 and about 2.5 g/l of SO4-. In solution, the chrome exists as chromic acid, known as
hexavalent chromium. A high current is used, in part to stabilize a thin layer of
chromium(+2) at the surface of the plated work. Acid chrome has poor throwing power,
fine details or holes are further away and receive less current resulting in poor plating.
Zinc plating
Zinc coatings prevent oxidation of the protected metal by forming a barrier and by acting as
a sacrificial anode if this barrier is damaged. Zinc oxide is a fine white dust that (in contrast
to iron oxide) does not cause a breakdown of the substrate's surface integrity as it is
formed. Indeed the zinc oxide, if undisturbed, can act as a barrier to further oxidation, in a
way similar to the protection afforded to aluminum and stainless steels by their oxide
layers. The majority of hardware parts are zinc plated, rather than cadmium plated.[2]
Tin plating
The tin-plating process is used extensively to protect both ferrous and nonferrous surfaces.
Tin is a useful metal for the food processing industry since it is non-toxic, ductile and
corrosion resistant. The excellent ductility of tin allows a tin coated base metal sheet to be
formed into a variety of shapes without damage to the surface tin layer. It provides
sacrificial protection for copper, nickel and other non-ferrous metals, but not for steel.
Tin is also widely used in the electronics industry because of its ability to protect the base
metal from oxidation thus preserving its solderability. In electronic applications, lead may
be added to prevent the growth of metallic "whiskers" in compression stressed deposits,
which would otherwise cause electrical shorting
Alloy plating
In some cases, it is desirable to co-deposit two or more metals resulting in an electroplated
alloy deposit. Depending on the alloy system, an electroplated alloy may be solid solution
strengthened or precipitation hardened by heat treatment to improve the plating's physical
and chemical properties. Nickel-Cobalt is a common electroplated alloy.
Composite plating
Metal matrix composite plating can be manufactured when a substrate is plated in a bath
containing a suspension of ceramic particles. Careful selection of the size and composition
of the particles can fine-tune the deposit for wear resistance, high temperature
performance, or mechanical strength. Tungsten carbide, silicon carbide, chromium carbide,
and aluminum oxide (alumina) are commonly used in composite electroplating.
Cadmium plating
Cadmium plating is under scrutiny because of the environmental toxicity of the cadmium
metal. However, cadmium plating is still widely used in some applications such as
aerospace fasteners and it remains in military and aviation specs.[3] Cadmium plating (or
"cad plating") has offers a long list of technical advantages such as excellent corrosion
resistance even at relatively low thickness and in salt atmospheres, softness and
malleability, freedom from sticky and/or bulky corrosion products, galvanic compatibility
with aluminum, freedom from stick-slip thus allowing reliable torqueing of plated threads,
can be dyed to many colors and clear, has good lubricity and solderability, and works well
either as a final finish or as a paint base. [2] [4]
Nickel plating
The chemical reaction for nickel plating is:
At cathode: Ni -> Ni2+ + 2eAt anode: H2PO2 + H2O -> H2PO3 + 2H+
Compared to cadmium plating, nickel plating offers a shinier and harder finish, but lower
corrosion resistance, lubricity, and malleability, resulting in a tendency to crack or flake if
the piece is further processed.[2]
See also
Hull Cell
Mechanical plating
Organic Solderability Preservative plating.
Sheffield plate
Via (electronics)
External links
• Electrochemistry Encyclopedia
[1] Pushpavanam, M (1981). "Rhodium — Electrodeposition and applications". Surface Technology 12: 351. doi:
10.1016/0376-4583(81)90029-7 (http:/ / dx. doi. org/ 10. 1016/ 0376-4583(81)90029-7).
[2] " Cadmium vs. Zinc vs. Nickel Plating Comparison (http:/ / www. finishing. com/ 130/ 89. shtml)"
[3] Cad plating letters-to-the-editor from http:/ / www. finishing. com/ 136/ 09. shtml
[4] Cadmium plating fact sheet from the Erie Plating Company, available http:/ / erieplating. com/
cadmium-plating (used with their permission).
[5] http:/ / electrochem. cwru. edu/ encycl/ art-e01-electroplat. htm
Semiconductor fabrication plant
Semiconductor fabrication plant
In the microelectronics industry, a semiconductor fabrication plant (commonly called a
fab) is a factory where devices such as integrated circuits are manufactured.
A business that operates a semiconductor fab for the purpose of fabricating the designs of
other companies, such as → fabless semiconductor companies, is known as a foundry. If a
foundry does not also produce its own designs, it is known as a pure-play semiconductor
Fabs require many expensive devices to function. Estimates put the cost of building a new
fab over one billion US dollars with values as high as $3-4 billion not being uncommon.
The central part of a fab is the clean room, an area where the environment is controlled to
eliminate all dust, since even a single speck can ruin a microcircuit, which has features
much smaller than dust. The clean room must also be dampened against vibration and kept
within narrow bands of temperature and humidity. Controlling temperature and humidity is
critical for minimizing static electricity.
The clean room contains the steppers for → photolithography, → etching, cleaning, doping
and dicing machines. All these devices are extremely precise and thus extremely expensive.
Prices for most common pieces of equipment for the processing of 300 mm wafers range
from $700,000 to upwards of $4,000,000 each with a few pieces of equipment reaching as
high as $50,000,000 each (e.g. steppers). A typical fab will have several hundred equipment
Typically an advance in chip-making technology requires a completely new fab to be built.
In the past, the equipment to outfit a fab was not terribly expensive and there were a huge
number of smaller fabs producing low-volume chips. However, the cost of the most
up-to-date equipment has since grown to the point where a new fab can cost on the order of
several billion dollars.
Another side effect of the cost has been the challenge to make use of older fabs. For many
companies these older fabs are useful for producing designs for unique markets, such as
embedded processors, flash memory, and microcontrollers. However for companies with
more limited product lines, it's often best to either rent out the fab, or close it entirely. This
is due to the tendency of the cost of upgrading an existing fab to produce devices requiring
newer technology to exceed the cost of a completely new fab.
There has been a trend to produce ever larger → wafers, so each process step is being
performed on more and more chips at once. The goal is to spread production costs
(chemicals, fab time) over a larger number of saleable chips. It is impossible (or at least
impracticable) to retrofit machinery to handle larger wafers. This is not to say that
foundries using smaller wafers are necessarily obsolete; older foundries can be cheaper to
operate, have higher yields for simple chips and still be productive.
The current state-of-the-art for wafer size is considered to be 300 mm (12 in). However,
Intel is currently pushing semiconductor equipment manufacturers to move to the 450 mm
wafer size. Additionally, there is a large push to completely automate the production of
semiconductor chips from beginning to end. This is often referred to as the "→ lights-out
fab" concept. A similar phenomenon was witnessed in the automobile manufacturing
Semiconductor fabrication plant
business during the 1980s.
The International Sematech Manufacturing Initiative (ISMI), an extension of the US
consortium SEMATECH, is sponsoring the "300 mm Prime" initiative. An important goal of
this initiative is to enable fabs to produce smaller lots of chips; this is a response to shorter
lifecycles seen in consumer electronics. The logic is that a fab that can produce smaller lots
can more easily and efficiently switch its production to supply chips for a variety of
electronic devices as they rapidly emerge in the marketplace. Another important goal is to
reduce fabrication time by reducing the waiting time between processing steps.[1] [2]
See also
• Semiconductor fabrication for the process of manufacturing devices
• → Foundry model for the business aspects of foundries and fabless companies
• Handbook of Semiconductor Manufacturing Technology, Second Edition by Robert
Doering and Yoshio Nishi (Hardcover - Jul 9, 2007)
• Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda (Paperback
- Nov 19, 2000)
• Fundamentals of Semiconductor Manufacturing and Process Control by Gary S. May and
Costas J. Spanos (Hardcover - May 22, 2006)
• The Essential Guide to Semiconductors (Essential Guide Series) by Jim Turley (Paperback
- Dec 29, 2002)
• Semiconductor Manufacturing Handbook (McGraw-Hill Handbooks) by Hwaiyu Geng
(Hardcover - April 27, 2005)
External links
• Chip Makers Watch Their Waste, Wall Street Journal, July 19, 2007, p.B3
• ISMI Press Release [3]
• Challenges of the gigawatt fab [4].
Chip Makers Watch Their Waste
ISMI Press Release
http:/ / ismi. sematech. org/ corporate/ news/ releases/ 20070719. htm
http:/ / www. pv-tech. org/ featured_articles/ _a/ first_edition_challenges_of_the_gigawatt_fab/
Lights out (manufacturing)
Lights out (manufacturing)
Lights out or lights-out manufacturing is a manufacturing methodology (or philosophy),
rather than a specific process. Factories that run lights out are fully automated and require
no human presence on-site. Thus, these factories can be run with the lights off. Many
factories are capable of lights-out production, but very few run exclusively lights-out.
Typically, workers are necessary to set up tombstones holding parts to be manufactured,
and to remove the completed parts. As the technology necessary for lights-out production
becomes increasingly available, many factories are beginning to utilize lights-out
production between shifts (or as a separate shift) to meet increasing demand or to save
Economics of lights-out manufacturing
With the mass layoffs being handed down to human employees as a result of the global
economic slowdown that followed years of offshoring jobs away from North America and
Western Europe, it is said that lights-out manufacturing could dominate the way that things
are manufactured. This statement is true when it concerns the geographic and political
regions that are currently served with highly-paid unionized laborers (e.g., Canada, the
United States of America, and the European Union). Products would be sold at a cheaper
price (improving the affordability of the item) because the robots don't have to be put on
the payroll, given a company pension, or handed out benefits for full-time labor. People
maintaining the robots would need the money, benefits, and the company pension.
However, the amount that would be paid to these human workers would be minimal
compared to paying the human laborers that the robots in the lights out manufacturing
technique will ultimately replace.
In developing countries like Honduras, El Salvador and Mexico, human labor will continue
to be in strong demand for decades. This is due to the fact that companies in Third World
countries must have low-paying jobs or no jobs at all. It is only due to the fact that the
service sector is predominant in developed countries that allows manufacturing plants and
factories to go lights out without significantly affecting the entire work force. Most
developing countries are either semi-agrarian or going through a nascent stage of
industrialization; making lights out manufacturing counterproductive there as the service
sector in those countries are not established enough to absorb the people that automation
eliminates from most blue collar jobs.
The future of lights-out manufacturing
Nanofactories would be the ultimate goal of the lights out manufacturing philosophy once
the global economy recovers. Using nanotechnology, both the finished objects and the
necessary components in creating them would be created in unlimited amounts by building
up the necessary elements on a sub-atomic level (i.e., food, water, fuel, electricity). These
molecular assemblers would be roughly the size of a desktop computer and would need
absolutely no human labor (except maintenance staff).
Lights out (manufacturing)
• CNN Money [1]
• Industrial Lasers
[1] http:/ / money. cnn. com/ magazines/ business2/ business2_archive/ 2003/ 06/ 01/ 343371/ index. htm
[2] http:/ / www. industrial-lasers. com/ articles/ article_display. html?id=252532
Foundry model
In microelectronics, the → foundry model refers to the separation of a → semiconductor
fabrication plant operation from an integrated circuit design operation, into separate
companies or business units.
Although many companies continue to both design and manufacture integrated circuits
(achieving efficiency through vertical integration), these Integrated Device Manufacturers
(IDMs) are not alone in the marketplace. Economic forces have led to the existence of many
companies that only design devices, known as fabless semiconductor companies, as well as
merchant foundries that only manufacture devices under contract by other companies,
without designing them.
IC production facilities are expensive to build and maintain. Unless they can be kept at
nearly full utilization, they will become a drain on the finances of the company that owns
them. The foundry model uses two methods to avoid these costs: Fabless companies avoid
costs by not owning such facilities. Merchant foundries, on the other hand, find work from
the worldwide pool of fabless companies, and by careful scheduling, pricing, and
contracting keep their plants at full utilization.
Originally, microelectronic devices were manufactured by companies that both designed
and produced the devices. This was necessary because manufacturing involved tweaking
parameters, precise understanding of the manufacturing processes being used, and the
occasional need to redesign. These manufacturers were involved in both the research and
development of manufacturing processes and the research and development of microcircuit
However, as manufacturing techniques developed, microelectronic devices became more
standardised allowing them to be used by more than a single manufacturer. This
standardization allowed design to be split from manufacture. A design that obeyed the
appropriate design rules could be manufactured by different companies that had
compatible manufacturing methods. An important development that allowed this was the
introduction of advances in electronic design automation (EDA), which allowed circuit
designers to exchange design data with other designers using different foundries.
Because of the separation of manufacture and design, new types of companies were
founded. One type of company was called a fabless company. These companies did not have
Foundry model
any semiconductor manufacturing capability but rather contracted production from a
manufacturer. This manufacturer was called a merchant foundry. The fabless company
concentrates on the research and development of an IC-product; the foundry concentrates
solely on fabricating and testing the physical product.
An absolute separation into fabless and foundry companies is not necessary. Some
companies continue to exist which perform both operations and benefit from the close
coupling of their skills. Some companies manufacture some of their own designs and
contract out to have others manufactured or designed, in cases where they see value or
seek special skills. The foundry model is a business vision that seeks to optimize
The very first merchant foundries were part of the → MOSIS service. The MOSIS service
gave limited production-access to designers with limited means, such as students,
researchers at a universities, and engineers at small startups. The designer submitted
designs and these submissions were manufactured with the commercial company's extra
capacity. Manufacturers could insert some → wafers for a MOSIS design into a collection of
their own wafers when a processing step was compatible with both operations. The
commercial company (serving as foundry) was already running the process so effectively
were being paid by MOSIS for something they were already doing. A factory with excess
capacity during slow periods could also run MOSIS designs in order to avoid having
expensive capital equipment standing idle.
Under-utilization of an expensive manufacturing plant could lead to the financial ruin of the
owner, so selling surplus wafer capacity was a way to maximize the fab's utilization. Hence,
economic factors created a climate where fab operators wanted to sell surplus
wafer-manufacturing capacity, and designers wanted to purchase manufacturing capacity
rather than try to build it.
Although MOSIS opened the doors to some fabless customers, earning additional revenue
for the foundry and providing inexpensive service to the customer, running a business
around MOSIS production was difficult. The merchant foundries sold wafer capacity on a
surplus basis, as a secondary business activity. Services to the customers were secondary
to the commercial business, with little guarantee of support. The choice of merchant
dictated the design, development flow, and available techniques to the fabless customer.
Merchant foundries might require proprietary and non-portable preparation steps.
Foundries concerned with protecting what they considered trade secrets of their
methodologies might only be willing to release data to designers after an onerous
nondisclosure procedure.
Dedicated foundry
In 1987, the world's first dedicated merchant foundry opened its doors: Taiwan
Semiconductor Manufacturing Company (TSMC). The distinction of 'dedicated' is in
reference to the typical merchant foundry of the era, whose primary business activity was
building and selling of its own IC-products. The dedicated foundry offers several key
advantages to its customers: First, it does not sell finished IC-products into the supply
channel; thus a dedicated foundry will never compete directly with its fabless customers
(obviating a common concern of fabless companies). Second, the dedicated foundry can
Foundry model
scale production capacity to a customer's needs, offering low-quantity shuttle services in
addition to full-scale production lines. Finally, the dedicated foundry offers a "COT-flow"
(customer owned tooling) based on industry-standard EDA systems, whereas many IDM
merchants required its customers to use proprietary (non-portable) development tools. The
COT advantage gave the customer complete control over the design process, from concept
to final design.
Foundry sales leaders by year
• Pure-play semiconductor foundry is a company that does not offer a significant
amount of IC products of its own design, but instead operates → semiconductor
fabrication plants focused on producing ICs for other companies.
• → IDM semiconductor foundry is where companies such as Texas Instruments, IBM,
and Samsung join in to provide foundry services as long as there is no conflict of interest
between relevant parties.
As of 2008, the top 18 pure-play semiconductor foundries were:
Country of origin
Revenue (million
South Korea
He Jian
Tower Semiconductor
Jazz Semiconductor
Polar Semiconductor
CR Micro (1)
(1) Merged with CR Logic in 2008, reclassified as an IDM foundry
Foundry model
As of 2007, the top 14 semiconductor foundries include:
Foundry type
Country of origin
Revenue (million
Texas Instruments → IDM
South Korea
South Korea
He Jian
South Korea
For ranking in worldwide Semiconductor sales leaders by year:
Country of origin
Revenue (million $USD)
As of 2004, the top 10 pure-play semiconductor foundries were:
Rank 2004
Country of origin
South Korea
Jazz Semiconductor
Foundry model
Financial and IP issues
Like all industries, the semiconductor industry faces upcoming challenges and obstacles.
The cost to stay on the leading edge has steadily increased with each generation of chips.
The financial strain is being felt by both large merchant foundries and their fabless
customers. The cost of a new foundry exceeds $1 billion. These costs must be passed on to
customers. Many merchant foundries have entered into joint ventures with their
competitors in an effort to split research and design expenditures and fab-maintenance
Chip design companies sometimes avoid other companies' patents simply by purchasing the
products from a licensed foundry with broad cross-license agreements with the patent
Stolen design data is also a concern; data is rarely directly copied, because blatant copies
are easily identified by distinctive features in the chip,[5] placed there either for this
purpose or as a byproduct of the design process. However, the data including any
procedure, process system, method of operation or concept may be sold to a competitor,
who may save months or years of tedious reverse engineering.
See also
→ Integrated device manufacturer
Semiconductor fabrication
Original design manufacturer
Original equipment manufacturer
Semiconductor sales leaders by year
Semiconductor fabless sales leaders by year
Semiconductor equipment sales leaders by year
External links
• Compound Semiconductor "Foundry model could be key to InP industry future"
[1] IC Insights, "Leading Pure-Play Foundry Companies" March 2009 (http:/ / www. semiconductor. net/ articles/
blog/ 270000427/ 20090304/ TopFoundries520. jpg)
[2] IC Insights, "2007 Major IC Foundries" (http:/ / www. eetasia. com/ IMAGES/ EEOL_2008MAY08_MFG_NT_02.
[3] IC Insights, "Worldwide 2006 Top 25 Semiconductor Sales Leaders" (http:/ / i. cmpnet. com/ eetimes/
eedesign/ 2007/ chart1_031407. gif)
[4] R. H. Abramson (28 Feb-4 Mar 1994). " When the chickens come home to roost: the licensed foundry defensein
patent cases (http:/ / ieeexplore. ieee. org/ xpl/ freeabs_all. jsp?tp=& arnumber=282907)". Compcon Spring '94,
Digest of Papers.: 348–354. doi: 10.1109/CMPCON.1994.282907 (http:/ / dx. doi. org/ 10. 1109/ CMPCON.
1994. 282907). .
[5] Carol Marsh and Tom Kean. " A Security Tagging Scheme for ASIC Designs and Intellectual Property Cores
(http:/ / www. design-reuse. com/ articles/ 15105/
a-security-tagging-scheme-for-asic-designs-and-intellectual-property-cores. html)". Design & Reuse. .
[6] http:/ / www. compoundsemiconductor. net/ articles/ magazine/ 11/ 8/ 1/ 1
Advanced Silicon Etch
Advanced Silicon Etch
Advanced Silicon Etch (ASE) is a deep reactive ion etching (DRIE) technique to rapidly
etch deep and high aspect ratio structures in silicon. ASE was pioneered by Surface
Technology Systems Plc. (STS) in 1994 in the UK. STS has continued to develop this
process with even greater etch rates while maintaining side wall roughness and selectivity.
STS developed the switched process originally invented by Dr. Larmer at Bosch, Stuttgart.
ASE consists in combining the fast etch rates achieved in an isotropic Si etch (usually
making use of an SF6 plasma) with a deposition or passivation process (usually utilising a
C4F8 plasma condensation process) by alternating the two process steps. This approach
achieves the fastest etch rates whilst maintaining the ability to etch anisotropically,
typically vertically in Microelectromechanical Systems (MEMS) applications.
"The ASE HRM is an evolution of the previous generations of ICP design, now
incorporating a decoupled plasma source (patent pending). This decoupled source
generates very high density plasma which is allowed to diffuse into a separate process
chamber. Through careful chamber design, the excess ions that are detrimental to
process control are reduced, leaving a uniform distribution of fluorine free-radicals at
a higher density than that available from the conventional ICP sources. The higher
fluorine free-radical density facilitates increased etch rates, typically over three times
the etch rates achieved with the original Bosch process. Also, as a result of the
reduction in the effect of localised depletion of these species, improved uniformity for
many applications can be achieved."
[1] Hopkins et al. 2004 Developments in Si and SiO2 Etching for MEMS-based Optical Applications (2004)
Scholar search
Hopkins, J (–
(http:/ / scholar. google. co. uk/ scholar?hl=en& lr=&
q=author:Hopkins+ intitle:Developments+ in+ Si+ and+ SiO2+ Etching+ for+
MEMS-based+ Optical+ Applications+ (2004)& as_publication=& as_ylo=& as_yhi=&
btnG=Search)), Developments in Si and SiO2 Etching for MEMS-based Optical Applications
(2004) (http:/ / www. stsystems. com/ pages/ process_content. asp?menuID=33&
subID=80& menuTitle=Technical Papers& mainMenuTitle=Publications), http:/ / www.
menuTitle=Technical%20Papers& mainMenuTitle=Publications, retrieved 2008-04-01.
Further reading
Publications on this subject can be read at Surface Technology Systems (http:/ / www.
stsystems. com/ pages/ process_content. asp?preview=YES& contID=1071& menuID=33&
contTitle=Technical Papers)
Buffered oxide etch
Buffered oxide etch
Buffered oxide etch, also known as buffered HF or BHF, is a wet → etchant used in →
microfabrication. Its primary use is in etching thin films of silicon dioxide (SiO2) or silicon
nitride (Si3N4). It is comprised of a mixture of a buffering agent, such as ammonium
fluoride (NH4F), and hydrofluoric acid (HF). Concentrated HF (typically 49% water) etches
silicon dioxide too quickly for good process control. Buffered oxide etch is commonly used
for more controllable etching. [1]
Some oxides produce insoluble products in HF solutions. Thus, HCl is often added to BHF
solutions in order to dissolve these insoluble products and produce a higher quality etch.[2]
A common buffered oxide etch solution comprises a 6:1 volume ratio of 40% NH4F in water
to 49% HF in water. This solution will etch thermally grown oxide at approximately 2
nanometres per second at 25 degrees Celsius.[1]
[1] Wolf, S.; R.N. Tauber (1986). Silicon Processing for the VLSI Era: Volume 1 - Process Technology. pp. 532-533.
ISBN 0-961672-3-7.
[2] Iliescua, Ciprian (Aug 2005). "Characterization of masking layers for deep wet etching of glass in an improved
HF/HCl solution". J. Surf. Coat. 198 (1-3): 314. doi: 10.1016/j.surfcoat.2004.10.094 (http:/ / dx. doi. org/ 10.
1016/ j. surfcoat. 2004. 10. 094).
Deep reactive-ion etching
Deep reactive-ion etching (DRIE) is a highly anisotropic etch process used to create
deep, steep-sided holes and trenches in wafers, with aspect ratios of 20:1 or more. It was
developed for microelectromechanical systems (MEMS), which require these features, but
is also used to excavate trenches for high-density capacitors for DRAM and more recently
for creating through wafer via's (TSV)'s in advanced 3D wafer level packaging technology .
There are two main technologies for high-rate DRIE: cryogenic and Bosch, although the
Bosch process is the only recognised production technique. Both Bosch and cryo processes
can fabricate 90° (truly vertical) walls, but often the walls are slightly tapered, e.g. 88° or
92° ("retrograde").
Another mechanism is sidewall passivation: SiOxFy functional groups (which originate from
sulphur hexafluoride and oxygen etch gases) condensate on the sidewalls, and protect them
from lateral etching. As a combination of these processes deep vertical structures can be
Cryogenic process
In cryo-DRIE, the wafer is chilled to −110 °C (163 K). The low temperature slows down the
chemical reaction that produces isotropic etching. However, ions continue to bombard
upward-facing surfaces and etch them away. This process produces trenches with highly
vertical sidewalls. The primary issues with cryo-DRIE is that the standard masks on
substrates crack under the extreme cold, plus etch by-products have a tendency of
depositing on the nearest cold surface, i.e. the substrate or electrode.
Deep reactive-ion etching
Bosch process
The Bosch process, also known as pulsed or time-multiplexed etching, alternates repeatedly
between two modes to achieve nearly vertical structures.
1. A standard, nearly isotropic plasma etch. The plasma contains some ions, which attack
the wafer from a nearly vertical direction. (For silicon, this often uses sulfur hexafluoride
2. Deposition of a chemically inert passivation layer. (For instance, C4F8 source gas yields a
substance similar to Teflon.)
Each phase lasts for several seconds. The passivation layer protects the entire substrate
from further chemical attack and prevents further etching. However, during the etching
phase, the directional ions that bombard the substrate attack the passivation layer at the
bottom of the trench (but not along the sides). They collide with it and sputter it off,
exposing the substrate to the chemical etchant.
These etch/deposit steps are repeated many times over resulting in a large number of very
small isotropic etch steps taking place only at the bottom of the etched pits. To etch
through a 0.5 mm silicon wafer, for example, 100–1000 etch/deposit steps are needed. The
two-phase process causes the sidewalls to undulate with an amplitude of about 100–500
nm. The cycle time can be adjusted: short cycles yield smoother walls, and long cycles yield
a higher etch rate.
RIE "deepness" depends on application:
• in DRAM memory circuits, capacitor trenches may be 10–20 µm deep,
• in MEMS, DRIE is used for anything from a few micrometers to 0.5 mm.
What distinguishes DRIE from RIE is etch depth: Practical etch depths for RIE (as used in
IC manufacturing)would be limited to around 10µm at a rate up to 1µm/min, while DRIE
can etch features much greater, up to 600µm or more with rates up to 20µm/min or more in
some applications.
DRIE of glass requires high plasma power, which makes it difficult to find suitable mask
materials for truly deep etching. Polysilicon and nickel are used for 10–50 µm etched
depths. In DRIE of polymers, Bosch process with alternating steps of SF6 etching and C4F8
passivation take place. Metal masks can be used however are expensive to use in that
several additional photo and deposition steps are always required. Metal masks are not
necessary however on various substrates (Si [up to 800 µm], InP [up to 40 µm] or glass [up
to 12 µm]) if using chemically amplified negative resists from providers such as Futurrex,
Inc. or others.
See also
• → Reactive-ion etching
• Microelectromechanical systems
Reactive-ion etching
Reactive-ion etching
Reactive ion etching (RIE) is an → etching technology used in → microfabrication. It uses
chemically reactive plasma to remove material deposited on → wafers. The plasma is
generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from
the plasma attack the wafer surface and react with it.
A typical (parallel plate) RIE system consists of a cylindrical vacuum chamber, with a →
wafer platter situated in the bottom portion of the chamber. The wafer platter is electrically
isolated from the rest of the chamber, which is usually grounded. Gas enters through small
inlets in the top of the chamber, and exits to the vacuum pump system through the bottom.
The types and amount of gas used vary depending upon the etch process; for instance,
sulfur hexafluoride is commonly used for etching silicon. Gas pressure is typically
maintained in a range between a few millitorr and a few hundred millitorr by adjusting gas
flow rates and/or adjusting an exhaust orifice.
Other types of RIE systems exist, including inductively coupled plasma (ICP) RIE. In this
type of system, the plasma is generated with an RF powered magnetic field. Very high
plasma densities can be achieved, though etch profiles tend to be more isotropic.
A combination of parallel plate and inductively coupled plasma RIE is possible. In this
system, the ICP is employed as a high density source of ions which increases the etch rate,
whereas a separate RF bias is applied to the substrate (silicon wafer) to create directional
electric fields near the substrate to achieve more anisotropic etch profiles.
Reactive-ion etching
Method of operation
Plasma is initiated in the
system by applying a strong
electromagnetic field to the
wafer platter. The field is
typically set to a frequency of
13.56 megahertz, applied at a
oscillating electric field ionizes
the gas molecules by stripping
them of electrons, creating a
In each cycle of the field, the
accelerated up and down in
striking both the upper wall of
A diagram of a common RIE setup. An RIE consists of two electrodes
the chamber and the wafer
(1 and 4) that create an electric field (3) meant to accelerate ions (2)
platter. At the same time, the
toward the surface of the samples (5).
much more massive ions move
relatively little in response to the RF electric field. When electrons are absorbed into the
chamber walls they are simply fed out to ground and do not alter the electronic state of the
system. However, electrons absorbed into the wafer platter cause the platter to build up
charge due to its DC isolation. This charge build up develops a large negative voltage on
the platter, typically around a few hundred volts. The plasma itself develops a slightly
positive charge due to the higher concentration of positive ions compared to free electrons.
Because of the large voltage difference, positive ions tend to drift toward the wafer platter,
where they collide with the samples to be etched. The ions react chemically with the
materials on the surface of the samples, but can also knock off (sputter) some material by
transferring some of their kinetic energy. Due to the mostly vertical delivery of reactive
ions, reactive ion etching can produce very anisotropic etch profiles, which contrast with
the typically isotropic profiles of wet chemical etching.
Etch conditions in an RIE system depend strongly on the many process parameters, such as
pressure, gas flows, and RF power. A modified version of RIE is → deep reactive-ion
etching, used to excavate deep features.
Reactive-ion etching
See also
• → Deep RIE (Bosch Process)
• Plasma Etcher
External links
BYU Cleanroom - RIE Etching [1]
Bosch Process [2]
Plasma Etch Fundamentals [3]
UC Davis Northern California Nanotechnology Center: RIE Operating Manual
http:/ / www. ee. byu. edu/ cleanroom/ rie_etching. phtml
http:/ / www. oxfordplasma. de/ process/ sibo_1. htm
http:/ / www. clarycon. com/ plasmaetchfundam. html
http:/ / ncnc. engineering. ucdavis. edu/ pages/ equipment/ rie. html
Airgap is an invention in microelectronic fabrication by IBM.
By insulating copper wires within a chip with vacuum holes, capacitance can be minimized
enabling chips to work faster or draw less power. A vacuum is believed to be the ultimate
insulator for what is known as wiring capacitance, which occurs when two adjacent wires
on a chip draw electrical energy from one another, generating undesirable heat and
slowing the speed at which data can move through a chip. IBM estimates that this
technology alone can lead to 35% higher speeds in current flow or 15% lower power
Fabrication techniques
IBM researchers have figured out a way to manufacture these "airgaps" on a massive scale,
using the self-assembly properties of certain polymers, and then combine this with regular
CMOS → manufacturing techniques, saving enormous resources since they don't have to
retool the entire process. When making the chips the entire → wafer is prepared with a
polymer material that when removed at a later stage leaves trillions of holes, just 20
nanometers in diameter, evenly spaced. Even though the name suggests that the holes are
filled with air, they are in fact filled with nothing, vacuum. IBM has already proven this
technique in their labs, and is already deployed in their manufacturing plant in East
Fishkill, New York where they have made prototype POWER6 processors using this
technology. Full scale deployment is scheduled for IBM's 45 nm node in 2009 after which
this technology will also be available to IBM's customers.
Airgap was developed in a collaborative effort between IBM's Almaden Research Center
and T.J. Watson Research Center, and the University of Albany, New York.
• Snowflakes promise faster chips, BBC [1]
• IBM Brings Nature to Computer Chip Manufacturing, IBM
• IBM's catches air, touts Top Ten list, Ars Technica [3]
[1] http:/ / news. bbc. co. uk/ 2/ hi/ technology/ 6618919. stm
[2] http:/ / www-03. ibm. com/ press/ us/ en/ pressrelease/ 21473. wss
[3] http:/ / arstechnica. com/ news. ars/ post/ 20070503-ibms-catches-air-touts-top-ten-list. html
B-staging is a process that utilizes heat or UV light to remove the majority of solvent from
an adhesive, thereby allowing construction to be “staged.” In between adhesive application,
assembly and curing, the product can be held for a period of time, without sacrificing
Attempts to use traditional epoxies in IC packaging often created expensive production
bottlenecks, because, as soon as the epoxy adhesive was applied, the components had to be
assembled and cured immediately. B-staging eliminates these bottlenecks by allowing the
IC manufacturing to proceed efficiently, with each step performed on larger batches of
• Advanced Packaging, UV B-Stage Technology Provides Process & Performance
Advantages [1]
[1] http:/ / ap. pennnet. com/ Articles/ Article_Display. cfm?Section=Articles& Subsection=Display&
Ball bonding
Ball bonding
Ball bonding is a type of → wire bonding,
and is the most common way to make the
electrical interconnections between a
microchip and the outside world as part of
semiconductor device fabrication.
Gold or copper wire can be used, though
gold is more common because its oxide is
not as problematic in making a weld. If
copper wire is used, nitrogen must be used
as a cover gas to prevent the copper oxides
from forming during the wire bonding
process. Copper is also harder than gold,
Gold wire ball-bonded to a gold contact pad
which makes damage to the surface of the
microchip more likely. However copper is
cheaper than gold and has superior electrical properties, and so remains a compelling
Almost all modern ball bonding processes use a combination of heat, pressure, and
ultrasonic energy to make a weld at each end of the wire. The wire used can be as small as
15 µm in diameter — such that several welds could fit across the width of a human hair.
A person upon first seeing a ball bonder will usually compare its operation to that of a
sewing machine. In fact there is a needle-like disposable tool called the capillary, through
which the wire is fed. A high-voltage electric charge is applied to the wire. This melts the
wire at the tip of the capillary. The tip of the wire forms into a ball because of the surface
tension of the molten metal.
The ball quickly solidifies, and the capillary is lowered to the surface of the microchip,
which is typically heated to at least 125°C. The machine then pushes down on the capillary
and applies ultrasonic energy with an attached transducer. The combined heat, pressure,
and ultrasonic energy create a weld between the copper or gold ball and the surface of the
microchip - which is usually copper or aluminum. All aluminum systems in semiconductor
fabrication eliminate the "purple plague" (brittle gold-aluminum intermetallic compound)
sometimes associated with pure gold bonding wire. This property makes Aluminium ideal
for ultrasonic bonding. This is the so-called ball bond that gives the process its name.[1]
Next the wire is passed out through the capillary and the machine moves over a few
millimeters to the location that the microchip needs to be wired up to (usually called the
substrate). The machine again descends to the surface, this time without making a ball so
that the wire is crushed between the substrate and the tip of the capillary. This time the
surface is usually gold, palladium, or silver - but the weld is made in the same way. The
resulting weld is quite different in appearance from the ball bond, and is referred to as the
wedge bond, tail bond, or simply as the second bond.
In the final step the machine pays out a small length of wire and tears the wire from the
surface using a set of clamps. This leaves a small tail of wire hanging from the end of the
capillary. The cycle then starts again with the high-voltage electric charge being applied to
this tail.
Ball bonding
The process where wire is cut right after ball is formed is also called stud bumping. Stud
bumping is used when stacking chips in system in package (SIP) modules.[2]
The current state-of-the-art machines (as of 2003[3]) can repeat this cycle about 20 times
per second. A modern ball bonder is fully automatic and is essentially a self-sufficient
industrial robot, complete with a vision system, sensors, and complex servo systems.
[1] http:/ / www. coininginc. com/ aluminum_and_silicon_ribbon. asp
[2] http:/ / www. coininginc. com/ Packaging. asp
[3] http:/ / en. wikipedia. org/ wiki/ Ball_bonding
Barrier metal
A barrier metal is a material used in integrated circuits to chemically isolate
semiconductors from soft metal interconnects, while maintaining an electrical connection
between them. For instance, a layer of barrier metal must surround every copper
interconnection in modern copper-based chips, to prevent diffusion of copper into
surrounding materials.
As the name implies, a barrier metal must have high electrical conductivity in order to
maintain a good electronic contact, while maintaining a low enough copper diffusivity to
sufficiently chemically isolate these copper conductor films from underlying device silicon.
The thickness of the barrier films is also quite important; with too thin a barrier layer, the
inner copper may contact and poison the very devices that they supply with energy and
information; with barrier layers too thick, these wrapped stacks of two barrier metal films
and an inner copper conductor can have a greater total resistance than the traditional
aluminum interconnections would have, eliminating any benefit derived from the new
metallization technology.
Some materials that have been used as barrier metals include cobalt, ruthenium, tantalum,
tantalum nitride, indium oxide, tungsten nitride, and → titanium nitride (the last four being
conductive ceramics, but "metals" in this context).
See also diffusion barrier.
Borophosphosilicate glass
Borophosphosilicate glass
Borophosphosilicate glass, commonly known as BPSG, is a type of → silicate glass that
includes additives of both boron and phosphorus. Silicate glasses such as → PSG and
borophosphosilicate glass are commonly used in semiconductor device fabrication for
intermetal layers, i.e., insulating layers deposited between succeedingly higher metal or
conducting layers.
BPSG has been implicated in increasing a device's susceptibility to soft errors since the
Boron-10 isotope is good at capturing thermal neutrons from cosmic radiation. It then
undergoes fission producing a gamma ray, an alpha particle, and a lithium ion. These
products may then dump charge into nearby structures, causing data loss (bit flipping, or
single event upset).
In critical designs, depleted boron consisting almost entirely of Boron-11 is used to avoid
this effect as a radiation hardening measure. Boron-11 is a by-product of the nuclear
Capacitance voltage profiling
The "CV", or more correctly "C-V", in C-V profiling, stands for capacitance-voltage, and
refers to a technique used for characterization of semiconductor materials and devices. The
technique uses a metal-semiconductor junction (Schottky barrier) or a p-n junction [1] or a
MOSFET to create a depletion region, a region which is empty of conducting electrons and
holes, but may contain ionized donors and electrically active defects or traps. The depletion
region with its ionized charges inside behaves like a capacitor. By varying the voltage
applied to the junction it is possible to vary the depletion width. The dependence of the
depletion width upon the applied voltage provides information on the semiconductor's
internal characteristics, such as its doping profile and electrically active defect densities.[2] ,
Measurements may be done at DC, or using both DC and a small-signal AC signal (the
conductance method [3] , [4] ), or using a large-signal transient voltage.[5]
Many researchers use capacitance voltage (C-V) testing to determine semiconductor
parameters, particularly in MOSCAP and MOSFET structures. However, C-V measurements
are also widely used to characterize other types of semiconductor devices and technologies,
including bipolar junction transistors, JFETs, III-V compound devices, photovoltaic cells,
MEMS devices, organic thin film transistor (TFT) displays, photodiodes, and carbon
nanotubes (CNTs).
These measurements’ fundamental nature makes them applicable to a wide range of
research tasks and disciplines. For example, researchers use them in university and
semiconductor manufacturers’ labs to evaluate new processes, materials, devices, and
circuits. These measurements are extremely valuable to product and yield enhancement
engineers who are responsible for improving processes and device performance. Reliability
engineers also use these measurements to qualify the suppliers of the materials they use, to
monitor process parameters, and to analyze failure mechanisms.
A multitude of semiconductor device and material parameters can be derived from C-V
measurements with appropriate methodologies, instrumentation, and software. This
information is used throughout the semiconductor production chain. This begins with
Capacitance voltage profiling
evaluating epitaxially grown crystals, including parameters such as average doping
concentration, doping profiles, and carrier lifetimes. C-V measurements can reveal oxide
thickness, oxide charges, contamination from mobile ions, and interface trap density in
wafer processes.
These measurements continue to be important after other process steps have been
performed, such as lithography, etching, cleaning, dielectric and polysilicon depositions,
and metallization. Once devices have been fully fabricated, C-V profiling is often used to
characterize threshold voltages and other parameters during reliability and basic device
testing and to model device performance.
See also
Depletion region
Metal–oxide–semiconductor structure
Depletion width
Deep-level transient spectroscopy
[1] J. Hilibrand and R.D. Gold, "Determination of the Impurity Distribution in Junction Diodes From
Capacitance-Voltage Measurements", RCA Review, vol. 21, p. 245, June 1960
[2] Alain C. Diebold (Editor) (2001). Handbook of Silicon Semiconductor Metrology (http:/ / books. google. com/
books?id=9B7e7rNnZPcC& pg=PA59& dq=metrology+ "capacitance+ voltage+ "& as_brr=0&
sig=fsNG3ovzjcQQANssiT2kgOh50ug#PPA59,M1). CRC Press. pp. 59–60. ISBN 0824705068. .
[3] J.R. Brews and E.H. Nicollian (2002). MOS (Metal Oxide Semiconductor) Physics and Technology (http:/ /
books. google. com/ books?as_isbn=047143079X). Wiley. ISBN 047143079X. .
[4] Andrzej Jakubowski, Henryk M. Przewłocki (1991). Diagnostic Measurements in LSI/VLSI Integrated Circuits
Production (http:/ / books. google. com/ books?id=MfM3VtXhpRwC& pg=PA159& dq=conductance+ method&
sig=WOWGtIqp5bV9uUe9y0Ca8-2dgwA). World Scientific. p. 159. ISBN 9810202822. .
[5] Sheng S. Li and Sorin Cristoloveanu (1995). Electrical Characterization of Silicon-On-Insulator Materials and
Devices (http:/ / books. google. com/ books?id=AAr0_xwg9SgC& pg=PA163& dq=DLTS& as_brr=0&
sig=tMicHzXLMpo0U6ezA5Hu10VDRS8). Springer. Chapter 6, p. 163. ISBN 0792395484. .
In → semiconductor device fabrication, channel-stopper or channel-stop is an area in
semiconductor devices produced by → implantation or diffusion of ions, by growing or
patterning the silicon oxide, or other isolation methods in semiconductor material with the
primary function to limit the spread of the channel area or to prevent the formation of
parasitic channels (inversion layers).[1]
[1] " Smart Power ICs", by Bruno Murari, Franco Bertotti, Giovanni A. Vignola, Antonio Andreini, 2002, ISBN
3540432388, pp. 47, 47 (http:/ / books. google. com/ books?id=RARwgdmuHyQC& pg=PA120& dq="channel+
Alfred Y. Cho
Alfred Y.Cho
Alfred Y. Cho
United States
Notable awards
Electrical engineering
IEEE Medal of Honor
National Medal of Science
Alfred Yi Cho (Chinese: 卓以和; born in 1937) is the Adjunct Vice President of
Semiconductor Research at Alcatel-Lucent's Bell Labs. He is known as the "father of →
molecular beam epitaxy"; a technique he developed at that facility in the late 1960s. He is
also the co-inventor, with Federico Capasso of quantum cascade lasers at Bell Labs in 1994.
Cho was born in 1937 in Beijing. He went to Hong Kong in 1949 and had his secondary
education in Pui Ching Middle School there. Cho holds B.S., M.S. and Ph.D. degrees in
electrical engineering from the University of Illinois. He joined Bell Labs in 1968. He is a
member of the National Academy of Sciences and the National Academy of Engineering, as
well as a Fellow of the American Physical Society, the Institute of Electrical and Electronics
Engineers, and the American Academy of Arts and Sciences.
In June 2007 he was honoured with the U.S. National Medal of Technology, the highest
honour awarded by the President of the United States for technological innovation[1] .
Cho received the award for his contributions to the invention of molecular beam epitaxy
(MBE) and his work to commercialize the process.
He already has many awards to his name, including: the American Physical Society
International Prize for New Materials in 1982, the Solid State Science and Technology
Medal of the Electrochemical Society in 1987, the World Materials Congress Award of ASM
International in 1988, the Gaede-Langmuir Award of the American Vacuum Society in 1988,
the Industrial Research Institute Achievement Award of the Industrial Research Institute
Inc in 1988, the New Jersey Governor's Thomas Alva Edison Science Award in 1990, the
International Crystal Growth Award of the American Association for Crystal Growth in
1990, the National Medal of Science in 1993, the Von Hippel Award of the Materials
Research Society in 1994, the Elliott Cresson Medal of the Franklin Institute in 1995, the
Alfred Y. Cho
IEEE Medal of Honor in 1994, and the Computers & Communications Prize of the C&C
Foundation, Japan in 1995.
In 1985, Bell Labs became the first organization to be honoured with a U.S. Medal of
Technology, awarded for “contributions over decades to modern communications systems.”
Cho’s honour marks the eighth time Bell Labs and its scientists have received the award.
Cho is married and has one son and three daughters.
External links
IEEE History Center [2]
New Jersey Inventors Hall of Fame, 1997 Inductees [3]
Scientists Demo Hi-Power, Multi-Channel Semiconductor Laser
National Medal of Science [5]
• Bell Labs researchers build world's first high-performance, ultra-broadband
semiconductor laser [6]
[1] Nanotechnology Now - Press Release: "Alcatel-Lucent Bell Labs luminary Alfred Y. Cho awarded U.S. National
Medal Of Technology" (http:/ / www. nanotech-now. com/ news. cgi?story_id=23255)
http:/ / www. ieee. org/ organizations/ history_center/ legacies/ cho. html
http:/ / www. njinvent. njit. edu/ 1997/ inductees_1997/ alfred_y. _cho. html
http:/ / www. bell-labs. com/ news/ 1998/ november/ 25/ 1. html
http:/ / www. ece. uiuc. edu/ alumni/ e2ca2win/ Cho. html
http:/ / www. lucent. com/ press/ 0202/ 020221. bla. html
A cleanroom is an environment, typically used in
manufacturing or scientific research, that has a low
level of environmental pollutants such as dust, airborne
microbes, aerosol particles and chemical vapors. More
accurately, a cleanroom has a controlled level of
contamination that is specified by the number of
particles per cubic meter at a specified particle size. To
give perspective, the ambient air outside in a typical
urban environment might contain as many as
35,000,000 particles per cubic meter, 0.5 μm and larger
in diameter, corresponding to an ISO 9 cleanroom.
NASA's Glenn Research Center
Cleanrooms can be very large. Entire manufacturing facilities can be contained within a
cleanroom with factory floors covering thousands of square meters. They are used
manufacturing, biotechnology, the life sciences and
other fields that are very sensitive to environmental
The air entering a cleanroom from outside is filtered to
exclude dust, and the air inside is constantly
recirculated through high efficiency particulate air
(HEPA) and/or ultra low particulate air (ULPA) filters to
remove internally generated contaminants.
Staff enter and leave through airlocks (sometimes
including an air shower stage), and wear protective
clothing such as hats, face masks, gloves, boots and
Clean room from outside (Cardiff
generate minimal air contamination. There are even
specialised mops and buckets. Cleanroom furniture is
also designed to produce a minimum of particles and to
be easy to clean.
Common materials such as paper, pencils, and fabrics
made from natural fibers are often excluded; however,
alternatives are available. Cleanrooms are not sterile
(i.e., free of uncontrolled microbes)[1] and more
attention is given to airborne particles. Particle levels
are usually tested using a particle counter.
Some cleanrooms are kept at a positive pressure so that
if there are any leaks, air leaks out of the chamber
instead of unfiltered air coming in.
Entrance to a clean room with no air
shower (Cardiff University)
Some cleanroom HVAC systems control the humidity to
relatively low levels, such that extra precautions are
necessary to prevent electrostatic discharge (ESD)
problems. These ESD controls ("ionizers") are also used
in rooms where ESD sensitive products are produced or
Low-level cleanrooms may only require special shoes,
ones with completely smooth soles that do not track in
dust or dirt. However, shoe bottoms must not create
slipping hazards (safety always takes precedence).
Entering a cleanroom usually requires wearing a
cleanroom suit.
Cleanroom for Microelectronics
In cheaper cleanrooms, in which the standards of air contamination are less rigorous, the
entrance to the cleanroom may not have an air shower. There is an anteroom, in which the
special suits must be put on, but then a person can walk in directly to the room (as seen in
the photograph on the right).
Some manufacturing facilities do not use fully classified
cleanrooms, but use some cleanroom practices together to
maintain their cleanliness requirements.[2] [3]
Cleanroom cabin for
precision measuring tools
Cleanroom air flow principles
Air flow pattern for "Turbulent
Air flow pattern for "Laminar Flow
Cleanroom classifications
Cleanrooms are classified according to the number and size of particles permitted per
volume of air. Large numbers like "class 100" or "class 1000" refer to FED-STD-209E, and
denote the number of particles of size 0.5 µm or larger permitted per cubic foot of air. The
standard also allows interpolation, so it is possible to describe e.g. "class 2000".
Small numbers refer to ISO 14644-1 standards, which specify the decimal logarithm of the
number of particles 0.1 µm or larger permitted per cubic metre of air. So, for example, an
ISO class 5 cleanroom has at most 105 = 100,000 particles per m³.
Both FS 209E and ISO 14644-1 assume log-log relationships between particle size and
particle concentration. For that reason, there is no such thing as a "zero" particle
concentration. The table locations without entries are N/A ("not applicable") combinations
of particle sizes and cleanliness classes, and should not be read as zero.
Because 1 m³ is approximately 35 ft³, the two standards are mostly equivalent when
measuring 0.5 µm particles, although the testing standards differ. Ordinary room air is
approximately class 1,000,000 or ISO 9.[4]
US FED STD 209E Cleanroom Standards
maximum particles/ft³
≥0.1 µm
≥0.2 µm
≥0.3 µm
≥0.5 µm
≥5 µm
US FED STD 209E was officially cancelled by the General Services Administration of the US
Department of Commerce November 29, 2001,[5] [6] but is still widely used.
ISO 14644-1 cleanroom standards
maximum particles/m³
≥0.1 µm
≥0.2 µm
≥0.3 µm
≥0.5 µm
≥1 µm
≥5 µm
Class 1
Class 10
Class 100
Class 1000
Class 10,000
29,300 Class 100,000
Room air
BS 5295 cleanroom standards
maximum particles/m³
≥0.5 µm
≥1 µm
Class 1
Class 2
Class 3
Class 4
≥5 µm
≥10 µm
≥25 µm
BS 5295 Class 1 also requires that the greatest particle present in any sample does not
exceed 5 μm.[7]
See also
Data recovery lab
Secure environment
ISO 14644
ISO 14698
Contamination control
Pneumatic filter
→ Semiconductor device fabrication
External links
• Cleanroom Industry News Site [8]
• The Global Society For Contamination Control (GSFCC)
[1] (http:/ / www. nytimes. com/ 2007/ 10/ 09/ science/ 09clea. html?ref=science)
[2] Your Cleanroom Supplier :: Hutchins & Hutchins, Inc (http:/ / yourcleanroomsupplier. com/ news.
[3] Cleanroom Forum (http:/ / www. cleanroomforum. com)
[4] Cleanroom Classification / Particle Count / FS209E / ISO TC209 / (http:/ / www. ee. byu. edu/ cleanroom/
particlecount. phtml)
[5] Cancellation of FED-STD-209E - Institute of Environmental Sciences and Technology (http:/ / www. iest. org/
i4a/ pages/ index. cfm?pageID=3480)
http:/ / www. wbdg. org/ ccb/ FEDMIL/ notices. pdf, page 148
Market Venture Philippines Inc. web site (http:/ / www. mvent. com. ph/ references/ cleanroom. htm)
http:/ / www. cleanroom. net
http:/ / www. gsfcc. org
Coining, Inc.
Coining, Inc.
Coining, Inc. is a manufacturer of solder preform and brazen preforms used for joining
applications in microelectronics packaging and → semiconductor device fabrication. They
are ISO 9001:2000 Certified by Lloyd's Register. Measured by both sales volume and units
shipped, Coining is the world's largest manufacturer of solder and brazing preforms for
microelectronic packaging and assembly in the world[1] . The company was founded in 1965
and is headquartered in Saddle Brook, New Jersey, USA, with other operating facilities in
Armonk, NY; Penang, Malaysia; and Casablanca, Morocco.
In early 2009 via the acquisition of its parent company, Coining Inc. acquired
Semiconductor Packaging Materials, a competing manufacturer of preforms,
microstampings and other microelectronics interconnect materials, especially gold,
aluminum and copper → wire bonding[2] [3] .
[1] http:/ / www. coininginc. com
[2] http:/ / http:/ / www. sempck. com/ default. asp
[3] http:/ / www. tradingmarkets. com/ . site/ news/ Stock%20News/ 2190643/
Dark current spectroscopy
Dark Current Spectroscopy is a technique that is used to determine contaminants in
Deal-Grove model
Deal-Grove model
The Deal-Grove model mathematically describes the growth of an oxide layer on the
surface of a material. In particular, it is used to analyze → thermal oxidation of silicon in →
semiconductor device fabrication. The model was first published in 1965 by Bruce Deal and
Andrew Grove, of Fairchild Semiconductor.
Physical assumptions
The model assumes that oxidation reaction occurs at
the interface between the oxide and the substrate,
rather than between the oxide and the ambient gas.
Thus, it considers three phenomena that the oxidizing
species undergoes, in this order:
1. It diffuses from the bulk of the ambient gas to the
2. It diffuses through the existing oxide layer to the
oxide-substrate interface.
3. It reacts with the substrate.
The model assumes that each of these stages proceeds at a rate proportional to the
oxidant's concentration. In the first case, this means Henry's law; in the second, Fick's law
of diffusion; in the third, a first-order reaction with respect to the oxidant. It also assumes
steady state conditions, i.e. that transient effects do not appear.
Given these assumptions, the flux of oxidant through each of the three phases can be
expressed in terms of concentrations, material properties, and temperature. By setting the
three fluxes equal to each other, they may each be found. In turn, the growth rate may be
found readily from the oxidant reaction flux.
In practice, the ambient gas (stage 1) does not limit the reaction rate, so this part of the
equation is often dropped. This simplification yields a simple quadratic equation for the
oxide thickness. For oxide growing on an initially bare substrate, the thickness Xo at time t
is given by the following equation:
where the constants A and B encapsulate the properties of the reaction and the oxide layer,
If a wafer that already contains oxide is placed in an oxidizing ambient, this equation must
be modified by adding a corrective term τ, the time that would have been required to grow
the pre-existing oxide under current conditions. This term may be found using the equation
for t above.
Solving the quadratic equation for Xo yields:
Deal-Grove model
The discriminant of the above equation reveals two main modes of operation:
Because they appear in these equations, the quantities B and B/A are often called the
quadratic and linear reaction rate constants. They depend exponentially on temperature,
like this:
is the activation energy and is the Boltzmann Constant in eV.
differs from
one equation to the other. The following table lists the values of the four parameters for
single-crystal silicon under conditions typically used in industry (low → doping, atmospheric
pressure). The linear rate constant depends on the orientation of the crystal (usually
indicated by the Miller indices of the crystal plane facing the surface). The table gives
values for <100> and <111> silicon.
Linear rate constant
Parabolic rate constant
Wet (
Dry (
<100>: 9.7 × 107
<111>: 1.63 × 108
<100>: 3.71 × 106
<111>: 6.23 × 106
Validity for silicon
The Deal-Grove model works very well for single-crystal silicon under most conditions.
However, experimental data shows that very thin oxides (less than about 25 nanometres)
grow much more quickly in
than the model predicts. This phenomenon is not well
understood theoretically, but it can be modeled.
If the oxide grown in a particular oxidation step will significantly exceed 25 nm, a simple
adjustment accounts for the aberrant growth rate. The model yields accurate results for
thick oxides if, instead of assuming zero initial thickness (or any initial thickness less than
25 nm), we assume that 25 nm of oxide exists before oxidation begins. However, for oxides
near to or thinner than this threshold, more sophisticated models must be used.
Deal-Grove also fails for polycrystalline silicon ("poly-silicon"). First, the random orientation
of the crystal grains makes it difficult to choose a value for the linear rate constant. Second,
oxidant molecules diffuse rapidly along grain boundaries, so that poly-silicon oxidizes more
rapidly than single-crystal silicon.
Dopant atoms strain the silicon lattice, and make it easier for silicon atoms to bond with
incoming oxygen. This effect may be neglected in many cases, but heavily-doped silicon
oxidizes significantly faster. The pressure of the ambient gas also affects oxidation rate.
Deal-Grove model
• Jaeger, Richard C. (2002). "Thermal Oxidation of Silicon". Introduction to Microelectronic
Fabrication. Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.
• Deal, B. E.; A. S. Grove (December 1965). "General Relationship for the Thermal
Oxidation of Silicon". Journal of Applied Physics 36 (12): 3770–3778.
doi:10.1063/1.1713945 [1].
External links
Online Calculator including pressure effects
lelandstanfordjunior. com/ thermaloxide. html
http:/ / www.
[1] http:/ / dx. doi. org/ 10. 1063%2F1. 1713945
Device under test
Device under test (DUT), also known as unit under test (UUT), is a term commonly used
to refer to a manufactured product undergoing testing.
In semiconductor testing
In semiconductor testing, DUT refers to a specific die on a → wafer or the resulting
packaged part. Using a connection system, the part is connected to a piece of manual or
automatic test equipment. The ATE then applies power to the part, supplies stimulus
signals, then measures and evaluates the resulting outputs from the device. In this way, the
ATE determines whether the particular device under test is good or bad.
While in the form of a wafer, the ATE connects to the individual DUTs (dice) using a set of
microscopic needles. Once the chips are sawn apart and packaged, the ATE connects to the
DUTs (packages) using ZIF sockets (sometimes called contactors).
General electronic testing
The term DUT is also used more generally within electronics to refer to any electronic
assembly under test. For example, cell phones coming off of an assembly line may be given
a final test in the same way as the individual chips were earlier tested. Each cell phone
under test is, briefly, the DUT.
The DUT is often connected to the ATE using a bed of nails tester of pogo pins.
See also
• System Under Test
Doping (semiconductor)
Doping (semiconductor)
In semiconductor production, doping is the process of intentionally introducing impurities
into an extremely pure (also referred to as intrinsic) semiconductor to change its electrical
properties. The impurities are dependent upon the type of semiconductor. Lightly- and
moderately-doped semiconductors are referred to as extrinsic. A semiconductor doped to
such high levels that it acts more like a conductor than a semiconductor is referred to as
Semiconductor doping was originally developed by John Robert Woodyard working at
Sperry Gyroscope Company during World War II.[1] The demands of his work on radar
denied Woodyard the opportunity to pursue semiconductor doping research. However, after
the war ended, his patent proved the grounds of extensive litigation by Sperry Rand.[2]
Related work was performed at Bell Labs by Gordon K. Teal and Morgan Sparks.[3]
Some dopants are added as the (usually silicon) boule is grown, giving each → wafer an
almost uniform initial doping.[4] To define circuit elements, selected areas—typically
controlled by → photolithography[5] —are further doped by such processes as diffusion[6]
and → ion implantation, the latter method being more popular in large production runs
because of increased controllability.
The number of dopant atoms needed to create a difference in the ability of a semiconductor
to conduct is very small. When a comparatively small number of dopant atoms are added,
on the order of one per 100 million atoms, the doping is said to be low or light. When many
more dopant atoms are added, on the order of one per ten thousand atoms, the doping is
referred to as heavy or high. This is often shown as n+ for n-type doping or p+ for p-type
doping. (See the article on semiconductors for a more detailed description of the doping
Dopant elements
Group 4 semiconductors
For the group 4 semiconductors such as silicon, germanium, and silicon carbide, the most
common dopants are acceptors from group 3 or donors from group 5 elements. (The group
number refers to the Roman numerals of the columns in the periodic table of the elements.)
Boron, arsenic, phosphorus, and occasionally gallium are used to dope silicon. Boron is the
p-type dopant of choice for silicon integrated circuit production because it diffuses at a rate
that makes junction depths easily controllable. Phosphorus is typically used for bulk-doping
of silicon wafers, while arsenic is used to diffuse junctions, because it diffuses more slowly
than phosphorus and is thus more controllable.
By doping pure silicon with group 5 elements such as phosphorus, extra valence electrons
are added that become unbonded from individual atoms and allow the compound to be an
electrically conductive n-type semiconductor. Doping with group 3 elements, which are
missing the fourth valence electron, creates "broken bonds" (holes) in the silicon lattice
Doping (semiconductor)
that are free to move. The result is an electrically conductive p-type semiconductor. In this
context, a group 5 element is said to behave as an electron donor, and a group 3 element
as an acceptor.
In most cases many types of impurities will be present in the resultant doped
semiconductor. If an equal number of donors and acceptors are present in the
semiconductor, the extra core electrons provided by the former will be used to satisfy the
broken bonds due to the latter, so that doping produces no free carriers of either type. This
phenomenon is known as compensation, and occurs at the p-n junction in the vast majority
of semiconductor devices. Partial compensation, where donors outnumber acceptors or vice
versa, allows device makers to repeatedly reverse the type of a given portion of the material
by applying successively higher doses of dopants.
Although compensation can be used to increase or decrease the number of donors or
acceptors, the electron and hole mobility is always decreased by compensation because
mobility is affected by the sum of the donor and acceptor ions.
Doping in organic conductors
Conductive polymers can be doped by adding chemical reactants to oxidize, or sometimes
reduce, the system so that electrons are pushed into the conducting orbitals within the
already potentially conducting system. There are two primary methods of doping a
conductive polymer, both of which use an oxidation-reduction (i.e., redox) process.
1. Chemical doping involves exposing a polymer such as melanin, typically a thin film, to
an oxidant such as iodine or bromine. Alternatively, the polymer can be exposed to a
reductant; this method is far less common, and typically involves alkali metals.
2. Electrochemical doping involves suspending a polymer-coated, working electrode in
an electrolyte solution in which the polymer is insoluble along with separate counter and
reference electrodes. An electric potential difference is created between the electrodes
that causes a charge and the appropriate counter ion from the electrolyte to enter the
polymer in the form of electron addition (i.e., n-doping) or removal (i.e., p-doping).
N-doping is much less common because the Earth's atmosphere is oxygen-rich, thus
creating an oxidizing environment. An electron-rich, n-doped polymer will react
immediately with elemental oxygen to de-dope (i.e., reoxidize to the neutral state) the
polymer. Thus, chemical n-doping must be performed in an environment of inert gas (e.g.,
argon). Electrochemical n-doping is far more common in research, because it is easier to
exclude oxygen from a solvent in a sealed flask. However, it is unlikely that n-doped
conductive polymers are available commercially.
Doping (semiconductor)
Magnetic doping
Research on magnetic doping has shown that considerable alteration of certain properties
such as specific heat may be affected by small concentrations of an impurity; for example,
dopant impurities in semiconducting ferromagnetic alloys can generate different properties
as first predicted by White, Hogan, Suhl and Nakamura.[7] [8]
See also
• Extrinsic semiconductor
• Intrinsic semiconductor
• List of semiconductor materials
[1] US Patent No.2,530,110, filed, 1944, granted 1950
[2] <docId=hb4d5nb20m&doc.view=frames& | year=1985
| work=University of California: In Memoriam | title=John Robert Woodyard, Electrical Engineering: Berkeley |
accessdate=2007-08-12 }}
[3] Sparks, Morgan and Teal, Gordon K. “Method of Making P-N Junctions in Semiconductor Materials,” U. S.
Patent 2,631,356 (Filed June 15, 1950. Issued March 17, 1953)
[4] Levy, Roland Albert (1989). Microelectronic Materials and Processes (http:/ / books. google. com/
books?id=wZPRPU6ne7UC& pg=PA248& sig=8JXOn_Dc0fPFnyEEkWh53lKWCOk#PPA1,M1). pp. 6–7. ISBN
0792301544. . Retrieved 2008-02-23.
[5] Computer History Museum - The Silicon Engine | 1955 - Photolithography Techniques Are Used to Make
Silicon Devices (http:/ / www. computerhistory. org/ semiconductor/ timeline/ 1955-Photolithography. html)
[6] Computer History Museum - The Silicon Engine | 1954 - Diffusion Process Developed for Transistors (http:/ /
www. computerhistory. org/ semiconductor/ timeline/ 1954-Diffusion. html)
[7] C. Michael Hogan, (1969) Density of States of an Insulating Ferromagnetic Alloy Phys. Rev. 188, 870 - 874,
[Issue 2 – December 1969 (http:/ / prola. aps. org/ abstract/ PR/ v188/ i2/ p870_1)
[8] X. Y. Zhang and H. Suhl (1985) Phys. Rev. A 32, 2530 - 2533 (1985) [Issue 4 – October 1985 (http:/ / prola. aps.
org/ abstract/ PRA/ v32/ i4/ p2530_1. )
Electron beam induced current
Electron beam induced current
Electron beam induced current (EBIC) is a
semiconductor analysis technique performed in a
scanning electron microscope (SEM) or scanning
transmission electron microscope (STEM). It is used to
identify buried junctions or defects in semiconductors,
or to examine minority carrier properties. EBIC is
EBIC experimental schematic
similar to cathodoluminescence in that it depends on
the creation of electron–hole pairs in the semiconductor
sample by the microscope's electron beam. This technique is used in semiconductor failure
analysis and solid-state physics.
Physics of the Technique
If the semiconductor sample contains an internal
electric field, as will be present in the depletion region
at a p-n junction or schottky junction, the electron–hole
pairs will be separated by drift due to the electric field.
If the p- and n-sides (or semiconductor and schottky
contact, in the case of a schottky device) are connected
through a picoammeter, a current will flow.
SEM set up for EBIC
EBIC is best understood by analogy: in a solar cell, photons of light fall on the entire cell,
thus delivering energy and creating electron hole pairs, and cause a current to flow. In
EBIC, energetic electrons take the role of the photons, causing the EBIC current to flow.
However, because the electron beam of an SEM or STEM is very small, it is scanned across
the sample and variations in the induced EBIC are used to map the electronic activity of the
By using the signal from the picoammeter as the
imaging signal, an EBIC image is formed on the screen
of the SEM or STEM. When a semiconductor device is
imaged in cross-section, the depletion region will show
bright EBIC contrast. The shape of the contrast can be
treated mathematically to determine the minority
carrier properties of the semiconductor, such as
diffusion length and surface recombination velocity. In
plan-view, areas with good crystal quality will show
bright contrast, and areas containing defects will show
dark EBIC contrast.
Plan-view EBIC showing defects in a
As such, EBIC is a semiconductor analysis technique
useful for evaluating minority carrier properties and defect populations.
Electron beam induced current
EBIC has also been extended to the study of local
defects in insulators. For example, W.S. Lau (Lau Wai
Shing) developed "true oxide electron beam induced
current" in the 1990's. Thus, besides p-n junction or
Schottky junction, EBIC can also be applied to MOS
diodes. Local defects in semiconductor and local
defects in the insulator could be distinguished. There
exists a kind of defect which originates in the silicon
substrate and extends into the insulator on top of the
silicon substrate. (Please see references below.)
Cross-sectional EBIC of a p-n junction
Recently, EBIC has been applied to high-k dielectric used in advanced CMOS technology.
(Please see references below.)
• H. J. Leamy, "Charge Collection scanning electron microscopy," Journal of Applied
Physics, V53(6), 1982, P. R51 (Review Article)
• C. Donolato, "On the analysis of diffusion length measurements by SEM," Solid State
Electronics, V25(11), 1982, P.1077
• J.-M. Bonard and J.-D. Ganiere, "Quantitative analysis of electron-beam-induced current
profiles across p-n junctions in GaAs/Al0.4Ga0.6As heterostructures," Journal of Applied
Physics, V79(9), 1996, P.6987
• Cole, E. (2004). "Beam-Based Defect Localization Methods". Microelectronics Failure
Analysis. ASM International. pp. pp. 406-407. ISBN 0-87170-804-3.
• W. S. Lau, D. S. H. Chan, J. C. H. Phang, K. W. Chow, K. S. Pey, Y. P. Lim and B.
Cronquist, "True oxide electron beam induced current for low-voltage imaging of local
defects in very thin silicon dioxide films", Applied Physics Letters, vol. 63, no. 16 (18
October 1993), pp. 2240-2242.
• W. S. Lau, D. S. H. Chan, J. C. H. Phang, K. W. Chow, K. S. Pey, Y. P. Lim, V. Sane and B.
Cronquist, "Quantitative imaging of local defects in very thin silicon dioxide films at low
bias voltage by true oxide electron beam induced current", Journal of Applied Physics,
vol. 77, no. 2 (15 Janurar 1995), pp. 739-746.
• W. S. Lau, V. Sane, K. S. Pey and B. Cronquist, "Two types of local oxide/substrate
defects in very thin silicon dioxide films on silicon", Applied Physics Letters, vol. 67, no.
19 (6 November 1995), pp. 2854-2856.
• J. Chen, T. Sekikuchi, N. Fukuta, M. Takase, R. Hasunuma, K. Yamabe, M. Sato, Y. Nara,
K. Yamada and T. Chikyo, "Trap-related carrier transports in p-channel field effect
transistor with polycrystallin Si/HSiON gate stack", Japanese Journal of Applied Physics,
vol. 48 (2009), pp. 04C005-1 to 04C005-4. (Note: EBIC was performed on advanced
high-k gate stack even though it is not obvious by reading the title of the paper.)
Electron beam induced current
External links
• Tutorial: Practical guide to building your own EBIC apparatus
EBIC Systems
• [2] Ephemeron Labs EBIC System
• [3] Gatan EBIC Introduction
[1] http:/ / www. microscopy-analysis. com/ tutorials/
[2] http:/ / ephemeron-labs. com/ projects/
[3] http:/ / www. gatan. com/ files/ PDF/ products/ Introduction_to_EBIC. pdf
An epiwafer is a wafer of semiconducting material made by epitaxial growth (called →
epitaxy) for use in making microelectronic devices such as light-emitting diodes (LEDs).
Two methods of growing the epitaxial layer on existing silicon or other wafers are currently
used: metal organic chemical vapor deposition (MOCVD) and → molecular beam epitaxy
These wafers are typically newer types of semiconductors such as gallium nitride (GaN), or
some combination of the elements gallium, indium, aluminum, nitrogen, phosphorus or
Evaporation (deposition)
Evaporation (deposition)
Evaporation is a common method of thin film
deposition. The source material is evaporated in a
vacuum. The vacuum allows vapor particles to travel
directly to the target object (substrate), where they
condense back to a solid state. Evaporation is used
in → microfabrication, and to make macro-scale
products such as metallized plastic film.
Physical principle
Evaporation involves two basic processes: a hot
source material evaporates and condenses on the
substrate. It resembles the familiar process by
which liquid water appears on the lid of a boiling
pot. However, the gaseous environment and heat
source (see "Equipment" below) are different.
Evaporation takes place in a vacuum, i.e. vapors
other than the source material are almost entirely
removed before the process begins. In high vacuum
Evaporation machine used for metallization
at LAAS technological facility in Toulouse,
(with a long mean free path), evaporated particles
can travel directly to the deposition target without
colliding with the background gas. (By contrast, in
the boiling pot example, the water vapor pushes the air out of the pot before it can reach
the lid.) At a typical pressure of 10-4 Pa, an 0.4-nm particle has a mean free path of 60 m.
Hot objects in the evaporation chamber, such as heating filaments, produce unwanted
vapors that limit the quality of the vacuum.
Evaporated atoms that collide with foreign particles may react with them; for instance, if
aluminium is deposited in the presence of oxygen, it will form aluminium oxide. They also
reduce the amount of vapor that reaches the substrate, which makes the thickness difficult
to control.
Evaporated materials deposit nonuniformly if the substrate has a rough surface (as
integrated circuits often do). Because the evaporated material attacks the substrate mostly
from a single direction, protruding features block the evaporated material from some areas.
This phenomenon is called "shadowing" or "step coverage."
When evaporation is performed in poor vacuum or close to atmospheric pressure, the
resulting deposition is generally non-uniform and tends not to be a continuous or smooth
film. Rather, the deposition will appear fuzzy .
Evaporation (deposition)
Any evaporation system includes a vacuum pump. It also includes an energy source that
evaporates the material to be deposited. Many different energy sources exist:
• In the thermal method, the source material is placed in a crucible, which is radiatively
heated by an electric filament. Alternatively, the source material may be hung from the
filament itself (filament evaporation).
• → Molecular beam epitaxy is an advanced form of thermal evaporation.
• In the electron-beam method, the source is heated by an electron beam with an energy
up to 15 keV. See Electron beam evaporation.
• In flash evaporation, a fine wire of source material is fed continuously onto a hot ceramic
bar, and evaporates on contact.
• Resistive evaporation is accomplished by passing a large current through a resistive wire
or foil containing the material to be deposited.
Some systems mount the substrate on an out-of-plane planetary mechanism. The
mechanism rotates the substrate simultaneously around two axes, to reduce shadowing.
• Purity of the deposited film depends on the quality of the vacuum, and on the purity of
the source material.
• The thickness of the film will vary due to the geometry of the evaporation chamber.
Collisions with residual gases aggravate nonuniformity of thickness.
• Filament and resistive evaporation cannot deposit thick films, because the size of the
filament limits the amount of material that can be deposited. However, flash evaporation
and methods that use crucibles can deposit thick films.
• In order to deposit a material, the evaporation system must be able to melt it. This makes
refractory materials such as tungsten hard to deposit by methods that do not use
electron-beam heating.
• Electron-beam evaporation allows tight control of the evaporation rate. Thus, an
electron-beam system with multiple beams and multiple sources can deposit a chemical
compound or composite material of known composition.
• Step coverage
An important example of an evaporative process is the production of aluminized PET film
packaging film in a roll-to-roll web system. Often, the aluminum layer in this material is not
thick enough to be entirely opaque since a thinner layer can be deposited more cheaply
than a thick one. The main purpose of the aluminum is to isolate the product from the
external environment by creating a barrier to the passage of light, oxygen, or water vapor.
Evaporation is commonly used in → microfabrication to deposit metal films.
Evaporation (deposition)
Comparison to other deposition methods
• Alternatives to evaporation, such as → sputtering and → chemical vapor deposition, have
better step coverage. This may be an advantage or disadvantage, depending on the
desired result.
• Sputtering tends to deposit material more slowly than evaporation.
• Sputtering uses a plasma, which produces many high-speed atoms that bombard the
substrate and may damage it. Evaporated atoms have a Maxwellian energy distribution,
determined by the temperature of the source, which reduces the number of high-speed
atoms. However, electron beams tend to produce X-rays (Bremsstrahlung) and stray
electrons, each of which can also damage the substrate.
• Jaeger, Richard C. (2002). "Film Deposition". Introduction to Microelectronic Fabrication.
Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.
• Semiconductor Devices: Physics and Technology, by S.M. Sze, ISBN 0-471-33372-7, has
an especially detailed discussion of film deposition by evaporation.
External links
• Thin film evaporation reference - properties of common materials
• of Vacuum Coaters [2]
• [3] (Society of Vacuum Coaters)
[1] http:/ / www. ee. byu. edu/ cleanroom/ TFE_materials. phtml
[2] http:/ / www. svc. org/ Society
[3] http:/ / www. svc. org
Fabless semiconductor company
Fabless semiconductor company
A fabless semiconductor company specializes in the design and sale of hardware devices
implemented on semiconductor chips. It achieves an advantage by outsourcing the
fabrication of the devices to a specialized semiconductor manufacturer called a
semiconductor foundry which may have several → fabrication facilities, or "fabs". The credit
for pioneering the fabless concept is given to Bernie Vonderschmitt of Xilinx and Gordon A.
Campbell of Chips and Technologies. Founded in 1983, Altera was the first fabless
semiconductor company.
A fabless company concentrates its research and development resources on the end market
without investing capital resources to stay current in semiconductor process technology. In
other words, they are fab-less, and do not own a fab or fabrication facility - instead they rely
on pure-play semiconductor foundries to manufacture their semiconductor chips on their
In 1994, Jodi Shelton - along with a half a dozen CEOs of fabless companies - established
the Fabless Semiconductor Association (FSA) to promote the fabless business model
globally. Eventually, the FSA became the global voice for the fabless ecosystem, with over
500 corporate members in 25 countries. In December 2007, the FSA transitioned to the
GSA - the Global Semiconductor Alliance. [1]
The organizational transition reflected the role FSA had played as a global organization
that collaborated with other organizations to co-host international events. Additionally, the
GSA leadership is composed of regional leadership councils with executives from those
regions who serve as advisers to the GSA Board of Directors on global and regional issues.
Those leadership councils are the Asia-Pacific Leadership Council and the Europe, Middle
East and African (EMEA) Leadership Council. The transition also highlights GSA's
membership and mission expansion beyond fabless to include the entire semiconductor
supply chain.
Prior to the 1980s, the semiconductor industry was vertically integrated. Semiconductor
companies owned and operated their own silicon wafer fabrication facilities and developed
their own process technology for manufacturing their chips. These companies also carried
out the assembly and testing of their chips.
Meanwhile, with the help of private-equity funding, smaller companies began to form, with
experienced engineers exercising their entrepreneurial prowess by establishing their own
IC design companies focused on innovative chip solutions.
As with most technology-intensive industries, the silicon manufacturing process was and is
cost-prohibitive, especially for these small start-up companies. These companies relied on
using excess capacity from → Integrated Device Manufacturers (IDMs) to manufacture the
chips they were designing.
This was the birth of the fabless business model. Companies were manufacturing integrated
circuits (ICs) without the need to own an internal fabrication plant. Simultaneously, the
foundry industry was established by Dr. Morris Chang with the founding of Taiwan
Semiconductor Manufacturing Corporation (TSMC). The foundry industry would become
the cornerstone of the fabless model - providing a non-competitive manufacturing supply
Fabless semiconductor company
chain partner for these innovative and pioneering fabless companies.
During the 1990s, industry pundits acknowledged the financial success of fabless
companies, such as Nvidia, Broadcom, and Xilinx, and such companies as Cyrix produced
competitively-priced products, benefitting consumers and driving the global market for
computing devices. As of 2007, the fabless model is the preferred business model for the
semiconductor industry.
When FSA was established in 1994, there were only three fabless companies - Cirrus Logic,
Adaptec, and Xilinx - each with revenues in excess of $250 million. In 2007, GSA tracked 10
separate fabless companies that have each surpassed $1 billion in annual revenues.
The model has been further validated by the conversion of major IDMs to a completely
fabless model, including (for example) Conexant Systems, Semtech, and most recently, LSI
Logic. Today most major IDMs including Freescale, Infineon, Texas Instruments and
Cypress Semiconductor have adopted the practice of outsourcing chip manufacturing as a
significant manufacturing strategy.
Fabless sales leaders by year
The top 5 sales leaders for fabless companies:
Country of origin
$ USD)
Marvell Technology Group
The top 5 sales leaders for fabless companies:
Country of origin
$ USD)
Marvell Technology Group
Fabless semiconductor company
The top 4 sales leaders for fabless companies:
$ USD)
Country of origin
Marvell Technology Group
The top 5 sales leaders for fabless companies:
Country of origin
$ USD)
ATI Technologies
The top 5 sales leaders for fabless companies:
Country of origin
$ USD)
ATI Technologies
Fabless semiconductor company
The top 5 sales leaders for fabless companies:
Country of origin
$ USD)
ATI Technologies
See also
• Semiconductor sales leaders by year
• Semiconductor foundry sales leaders by year
• Semiconductor equipment sales leaders by year
[1] " About the Global Semiconductor Alliance (http:/ / www. gsaglobal. org/ association/ about. asp)". GSA. .
[2] iSuppli Corporation supplied rankings for 2008 & 2007 (http:/ / www. eetasia. com/ IMAGES/
EEOL_2008MAR25_STOR_MFG_NT_01. jpg)
[3] iSuppli Corporation supplied rankings for 2006 (http:/ / i. cmpnet. com/ eetimes/ eedesign/ 2007/
chart1_031507. gif)
[4] iSuppli Corporation supplied rankings for 2005 & 2004 (http:/ / i. cmpnet. com/ siliconstrategies/ 2006/ 03/
isupplitables. gif)
Key people
GmbH & Co. KG
Berlin, Germany
Gunter Kuerbis, CEO
Advanced rework and micro assembly equipment
http:/ / www. finetech. de
Finetech GmbH & Co. KG makes equipment for various kinds of rework and micro
assembly operations.
Company Background
Originally founded in 1992, FINETECH entered the industry by focusing on rework
equipment. Soon after, the company added → flip chip assembly and → die-attach
equipment to its repertoire of resources.
Manual, semi-automatic and automatic FINEPLACER systems are available, and have a
modular design for maximum process flexibility. Applications range from R&D and
prototype environments (high-accuracy, low-volume) to more fully-automated production
with higher volumes.
The core businesses of FINETECH are in the fields of precision component placement, flip
chip and optoelectronic bonding, and SMT rework. The company services customers in a
broad range of industries including aerospace, medical technology, consumer electronics,
semiconductor, optoelectronics, military and universities. FINETECH works with companies
from the start-up phase to large multi-user corporations. Worldwide, the company has more
than 1.500 installations.
Operating worldwide, FINETECH offers equipment and application solutions for both,
advanced rework challenges and micro assembly.
The product range includes different types of Fineplacer systems (manual, semi-automatic
and automatic rework stations or bonding and assembly platforms) and a wide range of
additional tools and modules. Depending of specific configurations, the Fineplacer systems
are suitable for R&D and prototype environments (high-accuracy, low-volume) as well as for
more fully-automated production with higher volumes / higher rework yields.
Major application solutions are provided for rework of small passives, BGA and CGA, QFN
and MLF or single solder balls.
Furthermore, Fineplacer systems are capable of applying different bonding (i.e. → wire
bonding/→ ball bonding and adhesion technologies for MEMS / MOEMS assembly, RFID
assembly and all kinds of optoelectronics assembly.
Headquarters and main production sites are located in
• Berlin, Germany, with an additional manufacturing facility in Dresden, Germany.
Sales and services facilities are located in
• Tempe, Arizona
• Shanghai, China
• Kuala Lumpur, Malaysia
FINETECH is a ISO 9001 certified company since 2004.
External links
• http:/ / www. finetech. de (official website)
Focused ion beam
Focused ion beam, also known as FIB,
is a technique used particularly in the
semiconductor and materials science
deposition, and ablation of materials. An
FIB setup is a scientific instrument that
microscope (SEM). However, while the
SEM uses a focused beam of electrons
to image the sample in the chamber, an
FIB setup instead uses a focused beam
of ions. FIB can also be incorporated in
a system with both electron and ion
beam columns, allowing the same
feature to be investigated using either
of the beams.
Photograph of a FIB workstation
Ion beam source
Most widespread are instruments using Liquid-metal ion sources, especially gallium ion
sources. Ion sources based on elemental gold and iridium are also available. In a Gallium
LMIS, gallium metal is placed in contact with a tungsten needle and heated. Gallium wets
the tungsten, and a huge electric field (greater than 108 volts per centimeter) causes
ionization and field emission of the gallium atoms.
Source ions are then accelerated to an energy of 5-50 keV (kiloelectronvolts), and focused
onto the sample by electrostatic lenses. LMIs produce high current density ion beams with
very small energy spread. A modern FIB can deliver tens of nanoampers of current to a
Focused ion beam
sample, or can image the sample with a spot size on the order of a few nanometers.
Focused ion beam (FIB) systems
have been produced commercially
for approximately twenty years,
primarily for large semiconductor
operate in a similar fashion to a
(SEM) except, rather than a beam
of electrons and as the name
implies, FIB systems use a finely
focused beam of ions (usually
gallium) that can be operated at
low beam currents for imaging or
high beam currents for site specific
sputtering or milling.
the principle of FIB
As the diagram on the right shows, the gallium (Ga+) primary ion beam hits the sample
surface and sputters a small amount of material, which leaves the surface as either
secondary ions (i+ or i-) or neutral atoms (n0). The primary beam also produces secondary
electrons (e-). As the primary beam rasters on the sample surface, the signal from the
sputtered ions or secondary electrons is collected to form an image.
At low primary beam currents, very little material is sputtered; modern FIB systems can
easily achieve 5 nm imaging resolution (world record: 2.5 nm with Cobra FIB from Orsay
Physics). At higher primary currents, a great deal of material can be removed by sputtering,
allowing precision milling of the specimen down to a sub micron scale.
If the sample is non-conductive, a low energy electron flood gun can be used to provide
charge neutralization. In this manner, by imaging with positive secondary ions using the
positive primary ion beam, even highly insulating samples may be imaged and milled
without a conducting surface coating, as would be required in a SEM.
Until recently, the overwhelming usage of FIB has been in the semiconductor industry.
Such applications as defect analysis, circuit modification, mask repair and transmission
electron microscope sample preparation of site specific locations on integrated circuits
have become commonplace procedures. The latest FIB systems have high resolution
imaging capability; this capability coupled with in situ sectioning has eliminated the need,
in many cases, to examine FIB sectioned specimens in the SEM. [1]
Why Ions ?
The most fundamental difference between FIB and focused electron beam techniques such
as SEM, STEM or EBID is the use of ions instead of electrons, and this has major
consequences for the interactions that occur at the sample surface. The most important
characteristics and the consequences for the sample interaction are :
ions are larger than electrons
Focused ion beam
• Because ions are much larger than electrons, they cannot easily penetrate within
individual atoms of the sample. Interaction mainly involves outer shell interaction
resulting in atomic ionization and breaking of chemical bonds of the substrate atoms.
• The penetration depth of the ions is much lower than the penetration of electrons of the
same energy.
• When the ion has come to a stop within the material, it is caught in the matrix of the
ions are heavier than electrons
• Because ions are far heavier than electrons, ions can gain a high momentum. For the
same energy, the momentum of the ion is about 370 times larger.
• For the same energy ions move a lot slower than electrons. However, they are still fast
compared to the image collection mode and in practice this has no real consequences.
• The magnetic lenses are less effective on ions than they would be on electrons with the
same energy. As a consequence the focused ion beam system is equipped with
electro-static lenses and not with magnetic lenses.
ions are positive and electrons are negative
• This difference has negligible consequences and is taken care of by the polarity of fields
to control the beam and accelerate the ions.
In summary, ions are positive, large, heavy and slow, whereas electrons are negative, small,
light and fast. The most important consequence of the properties listed above is that ion
beams will remove atoms from the substrate and because the beam position, dwell time and
size are so well controlled it can be applied to remove material locally in a highly controlled
manner, down to the nanometer scale. [2]
Block diagram and real FIB
Focused ion beam
Unlike an electron microscope, FIB is inherently
destructive to the specimen. When the high-energy
gallium ions strike the sample, they will sputter atoms
from the surface. Gallium atoms will also be →
implanted into the top few nanometers of the surface,
and the surface will be made amorphous.
Because of the sputtering capability, the FIB is used as
a micro-machining tool, to modify or machine materials
at the micro- and nanoscale. FIB micro machining has
become a broad field of its own, but nano machining
with FIB is a field that still needs developing. The
common smallest beam size is 2.5-6 nm.
McMaster University name and logo
"tattooed" in two sizes on a hair.
FIB tools are designed to etch or machine surfaces, an ideal FIB might machine away one
atom layer without any disruption of the atoms in the next layer, or any residual disruptions
above the surface. Yet currently because of the sputter the machining typically roughens
surfaces at the submicrometre length scales.[3] [4] An FIB can also be used to deposit
material via ion beam induced deposition. FIB-assisted → chemical vapor deposition occurs
when a gas, such as tungsten hexacarbonyl (W(CO)6) is introduced to the vacuum chamber
and allowed to chemisorb onto the sample. By scanning an area with the beam, the
precursor gas will be decomposed into volatile and non-volatile components; the
non-volatile component, such as tungsten, remains on the surface as a deposition. This is
useful, as the deposited metal can be used as a sacrificial layer, to protect the underlying
sample from the destructive sputtering of the beam. From nanometers to hundred of
micrometers in length, tungsten metal deposition allows to put metal lines right where
needed. Other materials such as platinum, cobalt, carbon, gold, etc., can also be locally
deposited.[3] [4] Gas assisted deposition and FIB etching process are shown below. [5]
Gas assisted deposition process
Focused ion beam
Gas assisted FIB etching process
FIB is often used in the → semiconductor industry to
patch or modify an existing semiconductor device.
For example, in an integrated circuit, the gallium
beam could be used to cut unwanted electrical
connections, and/or to deposit conductive material
in order to make a connection. The high level of
surface interaction is exploited in patterned doping
of semiconductors. FIB is also used for maskless
The FIB is also commonly used to prepare samples
for the transmission electron microscope. The TEM
requires very thin samples, typically ~100
nanometers. Other techniques, such as ion milling or
electropolishing can be used to prepare such thin
samples. However, the nanometer-scale resolution of
the FIB allows the exact thin region to be chosen.
This is vital, for example, in integrated circuit failure
analysis. If a particular transistor out of several
million on a chip is bad, the only tool capable of
preparing an electron microscope sample of that
single transistor is the FIB.[3] [4]
The drawbacks to FIB sample preparation are the
above-mentioned surface damage and implantation,
example of a 3D nanostructure that can be
SEM image of a thin TEM sample
milled by FIB.
Focused ion beam
which produce noticeable effects when using
techniques such as high-resolution "lattice imaging"
TEM or electron energy loss spectroscopy. This
damaged layer can be minimised by FIB milling with
lower voltages, or by further milling with a
low-voltage argon ion beam after completion of the
FIB process.[6]
Orsay Physics Canion 31 Plus UHV FIB
on a TOF-SIMS 6600 from Physical
FIB preparation can be used with cryogenically
frozen samples in a suitably equipped instrument,
allowing cross sectional analysis of samples
containing liquids or fats, such as biological
samples, pharmaceuticals, foams, inks, and food
products [7]
FIB is also used for SIMS analysis technique. The
ejected secondary ions are collected and analyzed
after the surface of the specimen has been sputtered
with a primary focused ion beam.
enhanced and selective etching
FIB Imaging
At lower beam currents, FIB imaging resolution begins to
rival the more familiar scanning electron microscope (SEM)
in terms of imaging topography, however the FIB's two
imaging modes, using secondary electrons and secondary
ions, both produced by the primary ion beam, offer many
advantages over SEM.
FIB secondary electron images show intense grain
orientation contrast. As a result, grain morphology can be
readily imaged without resorting to chemical etching. Grain
FIB secondary electron image
boundary contrast can also be enhanced through careful
selection of imaging parameters. FIB secondary ion images
also reveal chemical differences, and are especially useful in corrosion studies, as
secondary ion yields of metals can increase by three orders of magnitude in the presence of
oxygen, clearly revealing the presence of corrosion[8]
Focused ion beam
History of FIB technology
• 1975: The first FIB systems based on field emission
technology were developed by Levi-Setti[9] [10] and by
Orloff and Swanson[11] and used gas field ionization
sources (GFISs).
• 1978: The first FIB based on an LMIS was built by Seliger
et al. [12] .
FIB secondary ion image
Physic of LMIS
• 1600: Gilbert documented that fluid under high tension forms a cone.
• 1914: Zeleny observed and filmed cones and jets
• 1959: Feynman suggested the use of Ion Beams.
• 1964: Taylor produced exactly conical solution to equations of Electro Hydro Dynamics
• 1975: Krohn and Ringo produced first high brightness ion source : LMIS
Some pioneers of LMIS & FIB
Mahoney (1969)
Sudraud et al Paris XI Orsay (1974)
University of Oxford Mair (1980)
Culham UK,Roy Clampitt Prewett (1980)
Oregon Graduate Center L.Swanson (1980)
Helium ion microscope (HeIM)
The other ion source seen in commercially available instruments is a Helium ion source,
which is less inherently damaging to the sample than Ga ions. As helium ions can be
focused into a smaller probe size and provide a much smaller sample interaction than
electrons in the SEM, the He ion microscope can generate equal or higher resolution
images with good material contrast and a higher depth of focus. Commercial instruments
are capable of sub 1 nm resolution[14] [15] .
Focused ion beam
Wien Filter in Focused Ion Beam
Imaging and milling with Ga ions always result in
Ga incorporation near the sample surface. As the
sample surface is sputtered away at a rate
proportional to the sputtering yield and the ion
flux (ions per area per time), the Ga is implanted
further into the sample, and a steady-state profile
of Ga is reached. This implantation is often a
problem in the range of the semiconductor where
silicon can be amorphised by the gallium. In order
to get an alternative solution to Ga LMIsources,
mass-filtered columns have been developed, based
on a Wien filter technology. Such sources include
Au-Si, Au-Ge and Au-Si-Ge sources providing Si,
Cr, Fe, Co, Ni, Ge, In, Sn, Au, Pb and other
ExB Column from Orsay Physics
The principle of a Wien filter is based on the
equilibrium of the opposite forces induced by
perpendicular electrostatic and a magnetic fields
acting on accelerated particles. The proper mass
trajectory remains straight and passes through the
mass selection aperture while the other masses are
stopped. [16]
Mass selection in the FIB column
Besides allowing the use of sources others than
gallium, these columns can switch from different
species simply by adjusting the properties of the
Wien filter. Larger ions can be used to make rapid
milling before refining the contours with smaller
ones. The user also benefits from the possibility to
dope his sample with elements of suitable alloy
The latter property has found great interests in magnetic. Khizroev and Litvinov have
shown, with the help of magnetic force microscopy (MFM), that there is a critical doze of
ions that a magnetic material can be exposed to without experiencing a change in the
magnetic properties. Exploiting FIB from such an unconventional perspective is especially
favourable today when the future of so many novel technologies depends on the ability to
rapidly fabricate prototype nanoscale magnetic devices. [17]
Focused ion beam
Further reading
• Mackenzie, R A D (1990). Nanotechnology 1: 163. doi:10.1088/0957-4484/1/2/007
• J. Orloff (2009). Handbook of Charged Particle Optics. CRC Press. ISBN
External links
• Orsay Physics [19]
• Triple Beam Focused Ion Beam with SEM and EDX [20]
• Technology and Examples of FIB [21] at S3, INFM, Italy
[1] " Introduction : Focused Ion Beam Systems (http:/ / www. fibics. com/ fib/ tutorials/
introduction-focused-ion-beam-systems/ 4/ )". . Retrieved 2009-08-06.
[2] FEI Company (2006). Focused ion beam technology, capabilities and applications.
[3] J. Orloff, M. Utlaut and L. Swanson (2003). High Resolution Focused Ion Beams: FIB and Its Applications.
Springer Press. ISBN 0-306-47350-X.
[4] L.A. Giannuzzi and F.A. Stevens (2004). Introduction to Focused Ion Beams: Instrumentation, Theory,
Techniques and Practice. Springer Press. ISBN 978-0-387-23116-7.
[5] Koch, J.; Grun, K.; Ruff, M.; Wernhardt, R.; Wieck, A.D. (1999). Creation of nanoelectronic devices by focused
ion beam implantation.
[6] Principe, E L (2005). "A Three Beam Approach to TEM Preparation Using In-situ Low Voltage Argon Ion Final
Milling in a FIB-SEM Instrument". Microscopy and Microanalysis 11. doi: 10.1017/S1431927605502460 (http:/ /
dx. doi. org/ 10. 1017/ S1431927605502460).
[7] " Unique Imaging of Soft Materials Using Cryo-SDB (http:/ / www. quorumtech. com/ Applications/
Cryo_Apps_Library/ cryo-SDB. pdf)". . Retrieved 2009-06-06.
[8] " FIB: Chemical Contrast (http:/ / www. fibics. com/ MS_FIBApp_SII_SteelCorrosion. html)". . Retrieved
[9] Levi-Setti, R. (1974). "Proton scanning microscopy: feasibility and promise". Scanning Electron Microscopy:
[10] W. H. Escovitz, T. R. Fox and R. Levi-Setti (1975). "Scanning Transmission Ion Microscope with a Field Ion
Source". Proceedings of the National Academy of Sciences of the United States of America 72 (5): 1826. doi:
10.1073/pnas.72.5.1826 (http:/ / dx. doi. org/ 10. 1073/ pnas. 72. 5. 1826).
[11] Orloff, J. and Swanson, L., (1975). "Study of a field-ionization source for microprobe applications". J. Vac. Sci.
Tech. 12: 1209. doi: 10.1116/1.568497 (http:/ / dx. doi. org/ 10. 1116/ 1. 568497).
[12] Seliger, R., Ward, J.W., Wang, V. and Kubena, R.L. (1979). "A high-intensity scanning ion probe with
submicrometer spot size". Appl. Phys. Lett. 34: 310. doi: 10.1063/1.90786 (http:/ / dx. doi. org/ 10. 1063/ 1.
[13] C.A. Volkert and A.M. Minor, Guest Editors (2007). " Focused Ion Beam: Microscopy and Micromachining
(http:/ / www. nanolab. ucla. edu/ FIB/ pdf/ MRS_Bulletin_2007_FIB_machining. pdf)". MRS Bulletin 32: 389. .
[14] " Carl Zeiss press release (http:/ / www. smt. zeiss. com/ C1256A770030BCE0/ WebViewAllE/
F4BF4E46C9379912C1257508002B9F7C)". 2008-11-21. . Retrieved 2009-06-06.
[15] " The Southampton Nanofabrication Centre: Helium Ion Microscope (http:/ / www. southampton-nanofab.
com/ orion. php)". . Retrieved 2009-06-06.
[16] Orsay physics work on ExB mass filter Column, 1993
[17] Khizroev S.; Litvinov D. (2004). "Focused-ion-beam-based rapid prototyping of nanoscale magnetic devices".
Nanotechnology 15: R7. doi: 10.1088/0957-4484/15/3/R01 (http:/ / dx. doi. org/ 10. 1088/ 0957-4484/ 15/ 3/
[18] http:/ / dx. doi. org/ 10. 1088%2F0957-4484%2F1%2F2%2F007
[19] http:/ / www. orsayphysics. com
[20] http:/ / www. ocas. be/ EquipmentChemical
[21] http:/ / www. s3. infm. it/ fib_index. html
Gas immersion laser doping
Gas immersion laser doping
Gas Immersion Laser Doping is a method of doping a semiconductor material like
How it works
Example: Doping Silicon with Boron
A thin Silicon → wafer is immersed in Boron gas while a pulsed laser repeatedly melts and
cools the wafer. The Boron atoms in the gas diffuse into the molten parts of the Silicon and
stay there when the Silicon solidifies, thus producing a Silicon wafer with Boron impurities.
The resultant material is a P-type semiconductor.
See also
• Doping
• → Semiconductor Wafers
• Semiconductor
• P-type semiconductor
• N-type semiconductor
• http:/ / physicsweb. org/ articles/ news/ 10/ 11/ 19/ 1
Gate count
In microprocessor design, gate count refers to the number of transistor switches, or gates,
that are needed to implement a design. Even with today's process technology providing
what was formerly considered impossible numbers of gates on a single chip, gate counts
remain one of the most important overall factors in the end price of a chip. Designs with
fewer gates will typically cost less, and for this reason gate count remains a commonly used
metric in the industry.
The term can also refer to the number of persons entering an event (such as a sports event)
[1] or a library [2] during a specified period.
[1] http:/ / www. bizjournals. com/ buffalo/ stories/ 2002/ 03/ 11/ editorial4. html
[2] http:/ / www. niso. org/ emetrics/ current/ category7. 1. html
A hardmask is a material used in semiconductor processing as an etch mask in lieu of
polymer or other organic "soft" materials. The idea is that polymers tend to be etched easily
by oxygen, fluorine, chlorine or other reactive gases to the extent that a pattern defined
using polymeric mask is rapidly degraded during → plasma etching.
Health hazards in semiconductor
manufacturing occupations
Health hazards in semiconductor manufacturing occupations is an issue of dispute
past and present workers of semiconductor manufacturing have with their employers and
associates of their employers.
These are the issues confronting semiconductor manufacturing workers, companies and
their suppliers:
• Use of toxic materials expose workers to potential health hazards which include cancer,
miscarriages and birth defects.
• Health manifestations due to exposure to toxins may take decades to surface.
• Protective gear that had been issued to workers that had been designed to protect the
products and process from contamination by workers but not designed to protect
workers from contamination by the process, products and materials.
• The use of vast variety of toxic chemicals in semiconductor manufacturing makes it
difficult to evaluate or pin-point the possibilities of contamination. It would require
performing exhaustive epidemiological studies which would be too expensive for a highly
competitive industry.
• Studies reveals that as much as 38 percent of pregnant women working in the chip
industry's clean rooms had experienced miscarriages, which is well above general norms
- Journal of Occupational Medicine 1998.
The defence put up by semiconductor industry officials are
• The chemicals are tightly controlled.
• Procedures have been put in place which would make contamination impossible.
• There is comparatively extremely low rate of accidents in the semiconductor industry.
• Semiconductor industry has been ranked the top 5% for workplace health and safety
among U.S. companies since 1972.
Semiconductor industry officials state that privacy obligations make it difficult for them to
provide data for studies.
[1] [2] [3] [4] [5] [6]
A Scientific Advisory Committee funded by the Semiconductor Industry Association
concluded there was no evidence of increased cancer risk to cleanroom workers, although
it could not rule out the possibility that circumstances might exist that could result in
increased risk. [7] [8]
Health hazards in semiconductor manufacturing occupations
A comprehensive summary of the issues in SF Chronicle, December 3, 2000
Dirty Secrets of Chipmaking Industry, USA Today, Jan. 12, 1998
The Wall Street Journal, October 5, 1998 by Bill Richards
Annals Academy of Medicine, Singapore, Vol 23, No. 5, September 1994: Health Issues in the Global
Semiconductor Industry, by Joseph LaDou, MD
[5] International Journal of Occupational and Environmental Health, Vol. 4 No 1., Jan-Mar 1998: The International
Electronics Industry, by Joseph LaDou, MD, Timothy Rohm, PhD, CIH
[6] Clinical Principles of Environmental Health, Baltimore MD, Williams and Wilkins, 1992
[7] " SIA: Environment, Safety & Health (http:/ / www. sia-online. org/ iss_environment. cfm)". .
[8] " SIA press release (http:/ / www. sia-online. org/ downloads/ WHP_PR_040819. pdf)". .
Integrated device manufacturer
An integrated device manufacturer (IDM) is a semiconductor company which designs,
manufactures, and sells integrated circuit (IC) products. As a classification, IDM is often
used to differentiate between a company which handles semiconductor manufacturing
in-house, and a → fabless semiconductor company, which outsources production to a
third-party. Due to the dynamic nature of the → semiconductor industry, the term IDM has
become less accurate than when it was coined.
Fabless operations
The terms fabless (fabrication-less), → foundry, and IDM are now used to describe the role a
company has in a business relationship. For example, Motorola owns and operates
fabrication facilities (fab) where it manufactures many chip product lines, as a traditional
IDM would. Yet it is known to contract with merchant foundries for other products, as
would fabless companies.
Many electronic manufacturing companies engage in business that would qualify them as
an IDM: including but not limited to Cypress Semiconductor, Fujitsu, Hitachi, IBM, IDT,
Intel, LSI Corporation, Matsushita, Mitsubishi, Freescale, NEC, Philips, NXP, Samsung,
STMicroelectronics, Infineon, Renesas, Sony, National Semiconductor, Texas Instruments,
and Toshiba.
Ion Beam Mixing
Ion Beam Mixing
Ion Beam Mixing is a process for adhering two multilayers, especially a substrate and
deposited surface layer. The process involves bombarding layered samples with doses of ion
radiation in order to promote mixing at the interface, and generally serves as a means of
preparing electrical junctions, especially between non-equilibrium or metastable alloys and
intermetallic compounds.
The unique effects that stem from ion beam mixing are primarily a result of ballistic effects;
that is, impinging ions have high kinetic energies that are transferred to target atoms on
collision. Ion energies can be seen on the order of 1 keV to 200 keV. When accelerated,
such ion energies are sufficiently high to break intra- and especially inter-molecular bonds,
and initiate relocations within an atomic lattice. During this ballistic process, energies of
impinging ions displace atoms and electrons of the target material several lattice sites
away, resulting in relocations there and interface mixing at the boundary layer. (Note that
energies must be sufficiently high in order for the lattice rearrangements to be permanent
rather than manifesting as mere vibrational responses to the impinging radiation.) If
energies are kept sufficiently high in these nuclear collisions, then, compared to traditional
high-dose implantation processes, ballistic ion implantation produces higher intrafilm alloy
concentrations at lower doses of irradiation compared to conventional implantation
There are some important relationships to note concerning ion beam mixing of films. First,
the degree of mixing of a film scales with the ion mass, with the intensity of any given
incident ion beam, and with the amount of time the ion beam is left to impinge on a target.
The amount of mixing is proportional to the square roots of time, mass and ion dose. At
temperatures below 100 °C for most implanted materials, ion beam mixing is essentially
temperature independent, but, as temperature increases beyond that point, mixing rises
exponentially with temperature. This temperature dependence is a manifestation of
incident ion beams effectively imparting the target species dependent activation energy to
the barrier layer.[1]
Ballistic ion beam mixing can be classified into two basic sub types, recoil mixing and
cascade mixing, which happen simultaneously as a result of ion bombardment. In recoil
mixing, atoms are relocated by single collision events. Recoil mixing is predominately seen
at large angles as a result of soft collisions, with the number of atoms undergoing recoil
implantation varying linearly with ion dose. Recoil implantation, however, is not the
dominant process in ion beam mixing. Most relocated atoms are part of a collisional
cascade in which recoiled atoms vibrate, initiating a series of lower energy lattice
displacements, which is referred to as cascade mixing.[1]
Ion mixing (IM) is essentially similar in result to interdiffusion, and hence most models of
ion mixing involve an effective diffusion coefficient that is used to characterize thickness of
the reacted layer as a function of ion beam implantation over a period of time.[1]
Ion Beam Mixing
The diffusion model, though, doesn’t take into account the miscibility of substrate and
layer, so for immiscible or low miscibility systems it will overestimate the degree of mixing,
while for highly miscible systems, the model will underestimate the degree of mixing.
Thermodynamic effects are also not considered in this basic interdiffusion equation, but can
be modeled by equations that consider the enthalpies of mixing and the molar fractions of
the target species and one can thereby develop a thermodynamic effective diffusion
coefficient reflecting temperature effects (which become pronounced at high
temperatures). i9o08p79-[
Advantages and disadvantages
Advantages of ion beam mixing as a means of synthesis over traditional modes of
implantation include the process' ability to produce materials with high solute
concentrations using lower amounts of irradiation, and better control of band gap variation
and diffusion between layers.[1] [2] IM is also less cost-prohibitive than other modes of film
preparation on substrates, such as → chemical vapor deposition (CVD) and → molecular
beam epitaxy (MBE).
Disadvantages include the inability to completely direct and control lattice displacements
initiated in the process, which can result in an undesirable degree of disorder in ion mixed
samples, rendering them unsuitable for applications in which precise lattice orderings are
paramount. Ion beams can not be perfectly directed nor the collision cascade controlled
once IM effects propagate, which can result in leaking, electron diffraction, radiation
enhanced diffusion (RED), chemical migration and mismatch.[3] Additionally, all ion mixed
samples must be annealed.
See also
• List of coating techniques
External links
• Ion Beam Mixing at
[1] Nastasi, Michael (17–29 July 2004). " Ion Beam Mixing (http:/ / www. lanl. gov/ mst/ radeffects/ docs/ Nastasi.
Ion mixing. pdf)" (PDF). Radiation Effects in Solids. Erice, Sicily, Italy: Los Alamos National Laboratory
Materials Science and Technology Division.
[2] Abedrabbo, S.; Arafah, D.E., Gokce, O., Wielunski, L.S., et al. (May 2006). " Ion Beam Mixing for Processing of
Nanostructure Materials (http:/ / findarticles. com/ p/ articles/ mi_qa3776/ is_200605/ ai_n17176716)". Journal
of Electronic Materials. . Retrieved 2007-05-02.
[3] Abedrabbo, Sufian; Arafah, D.E., Salem, S. (May 2005). " Ion Beam Mixing of Silicon-Germanium Thin Films
(http:/ / findarticles. com/ p/ articles/ mi_qa3776/ is_200505/ ai_n13641484)". Journal of Electronic Materials. .
Retrieved 2007-05-02.
[4] http:/ / www. answers. com/ topic/ ion-beam-mixing
Ion beam
Ion beam
An ion beam is a type of particle beam consisting of ions. Ion beams have many uses in
electronics manufacturing (principally → ion implantation) and other industries. Today's ion
beam sources are typically derived from the mercury vapor thrusters developed by NASA in
the 1960s.
Ion beam etching or Sputtering
One type of ion beam source is the duoplasmatron. Ion beams can be used for sputtering or
ion beam etching and for ion beam analysis.
Ion beam application, etching, or sputtering, is a technique conceptually similar to
sandblasting, but using individual atoms in an ion beam to ablate a target. Reactive ion
etching is an important extension that uses chemical reactivity to enhance the physical
sputtering effect.
In a typical use in semiconductor manufacturing, a mask is used to selectively expose a
layer of photoresist on a → substrate such as a silicon dioxide or gallium arsenide wafer.
The wafer is developed, and for a positive photoresist, the exposed portions are removed in
a chemical process. The result is a pattern left on the surface areas of the wafer that had
been masked from exposure. The wafer is then placed in a vacuum chamber, and exposed
to the ion beam. The impact of the ions erodes the target, abrading away the areas not
covered by the photoresist. This method is frequently enhanced by bleeding a reactive gas
into the vacuum system, which is known as reactive ion etching.
→ Focused Ion Beam (FIB) instruments are also used in the design verification and/or
failure analysis of semiconductor devices. Engineering prototype devices may be modified
using the ion beam in order to rewire the electrical circuit. The technique may be
effectively used to avoid performing a new mask run for the purpose of testing design
changes. A device edit (FIB milling operation) is accomplished by focusing the ion beam on
selected regions of the device in order to mill through metal or polysilicon structures. In
addition to milling, it is also possible to use the ion beam to force the deposit of new
conductive lines on the surface of the device. This is accomplished by injecting chemicals
into the ion stream near the device surface. The interaction between the ions and the
chemicals result in chemical deposition on the surface. This process is typically referred to
as a FIB deposit operation.
Sputtering is also used in materials science to thin samples or specific regions of samples
for transmission electron microscope analysis, or for extending surface analytical
techniques such as secondary ion mass spectrometry or electron spectroscopy (XPS, AES)
so that they can depth profile them.
Ion beam
In Radiobiology a broad or focused ion beam is used to study mechanisms of iner- amd
intra- cellular communication, Signal transduction and DNA damage and repair.
High energy ion beams
High energy ion beams produced by particle accelerators are used in atomic physics,
nuclear physics and particle physics.
The use of ion beams as a particle beam weapon is theoretically possible, but has not been
demonstrated. See particle beam weapon for more information on this type of weapon.
The current ion beams today would barely cause a human to flinch or even notice a touch if
hit. The ions only stay in a beam shape if under ultra-high vacuum (UHV) conditions,
making its use as a weapon futile. However, if one is trying to destroy single cells, the ion
beam may be one's "weapon of choice."
In science fiction, weaponised ion beam generators are usually dubbed ion cannons.
See also
• Particle beam
• microbeam
Ion beam lithography
By analogy to E-beam lithography, → focused ion beam lithography scans an ion beam
across a surface to form a pattern. The ion beam may be used for directly sputtering the
surface, or may induce chemical reactions in the exposed top layer (resist). In the case of
direct sputtering, redeposition is a common occurrence, which will affect the final surface
profile. In the case of resist exposure, the slowing down of secondary electrons is the basis
for forming the final image, which therefore limit the resolution of acceptably printed
features to about 30 nm, even though the beam spot size can be smaller. The ion beam may
also either be focused through a (stencil) mask or directly on the surface without a mask.
The masked approach causes erosion of the openings by the ion beam through the inherent
sputterning process. But this approach has been found to be useful for transferring
high-fidelity patterns on non-planar surfaces[1] .
[1] Dhara Parikh, Barry Craver, Hatem N. Nounu, Fu-On Fong, and John C. Wolfe, "Nanoscale Pattern Definition
on Nonplanar Surfaces Using Ion Beam Proximity Lithography and Conformal Plasma-Deposited Resist",
Journal of microelectromechanical systems, vol. 17, no. 3, June 2008
Laser trimming
Laser trimming
Laser trimming is the manufacturing process of using a laser to adjust the operating
parameters of an electronic circuit.
One of the most common applications uses a laser is used to burn away small portions of
resistors, raising their resistance value. The burning operation can be conducted while the
circuit is being tested by automatic test equipment, leading to optimum final values for the
resistor(s) in the circuit.
The resistance value of a film resistor is defined by its geometric dimensions (length, width,
height) and the resistor material. A lateral cut in the resistor material by the laser narrows
or lengthens the current flow path and increases the resistance value. The same effect is
obtained whether the laser changes a thick-film or a thin-film resistor on a ceramic
substrate or an SMD-resistor on a SMD circuit. The SMD-resistor is produced with the
same technology and may be laser trimmed as well.
Trimmable chip capacitors are build up as multilayer plate capacitors. Vaporizing the top
layer with a laser decreases the capacitance by reducing the area of the top electrode.
Passive trim is the adjustment of a resistor to a given value. If the trimming adjusts the
whole circuit output such as output voltage, frequency, or switching threshold, this is called
active trim. During the trim process, the corresponding parameter is measured
continuously and compared to the programmed nominal value. The laser stops
automatically when the value reaches the nominal value.
Trimming LTCC resistances in a pressure chamber
One type of passive trimmer uses a pressure chamber to enable resistor trimming in a
single run. The → LTCC boards are contacted by test probes on the assembly side and
trimmed with a laser beam from the resistor side. This trimming method requires no
contact points between the resistances, because the fine pitch adapter contacts the
component on the opposite side of where the trimming occurs. Therefore, the LTCC can be
arranged more compactly and less expensively.
Laser trimming
Function mode:
• The LTCC is mounted in the
contact unit.
• From the opposite side a
rigid probe contacts the
• From the top side the
chamber is pressurized to 1
to 4 bars, with a controlled
exhaust port to achieve air
flow through the chamber.
• As the resistance material is
vaporized, the waste
particles are removed in the
air flow.
High speed R-Laser Trimmer with a pressure chamber
Advantages of this method:
• Trimming of unlimited number of printed resistors in one step without obstruction from
test probes.
• No contamination on board, adapter or in system.
• Density up to 280 points/cm².
Trimming potentiometers
Often designers use potentiometers, which are adjusted during end testing until the desired
function of the circuit is reached. In many applications, the end user of the product would
prefer not to have potentiometers, as they can drift, be mis-adjusted or develop noise.
Therefore manufacturers determine the needed resistance or capacitance values by
measurement and calculation methods and afterwards solder the suitable component into
the final PCB; this approach is called "Select on Test" (SOT) and is quite labor-intensive.
It is simpler to substitute the potentiometer or the SOT part with a trimmable chip
resistor or chip capacitor, and the potentiometer adjusting screwdriver is replaced by the
laser trimming. The achieved accuracy can be higher, the procedure can be automated and
the long term stability is better than with potentiometers and at least as good as with SOT
components. Often the laser for active trimming can be integrated in existing measurement
systems by the manufacturer.
Program from digital logic circuits
A similar approach can be used to program digital logic circuits. In this case, fuses are
blown by the laser, enabling or disabling various logic circuits. An example of this is the
IBM Power-4 processor chip where the chip contains five banks of cache memory but only
requires four banks for full operation. During testing, each cache bank is exercised. If a
defect is found in one bank, that bank can be disabled by blowing its programming fuse.
This built-in redundancy allows higher chip yields than would be possible if all cache banks
had to be perfect in every chip. If no bank is defective, a fuse can be blown arbitrarily,
leaving just four banks.
Laser trimming
External links
Laser trimmers with a pressure chamber [1]
System manufacturer laser trimmers [2]
Representative of GSI laser trimmers [3]
C-MAC MicroTechnology laser trimming on thick-film hybrids
http:/ / www. microcontact. ch
http:/ / www. ls-laser-systems. com
http:/ / www. epp-germany. com
http:/ / www. cmac. com/ services/ manufacture/ substrates/ Thick-filmHybrids. php
Lift-off (microtechnology)
Lift-off process in microstructuring technology is a method of creating structures
(patterning) of a target material on the surface of a substrate (ex. → wafer) using a
sacrificial material. It is an additive technique as opposed to more traditional subtracting
technique like → etching. The scale of the structures can vary from the nanoscale up to the
centimeter scale or further, but are typically of a micrometric dimensions.
Lift-off (microtechnology)
An inverse pattern is first created in the sacrificial
stencil layer (ex. photoresist), deposited on the surface
of the substrate. This is done by etching openings
through the layer so that the target material can reach
the surface of the substrate in those regions, where the
final pattern is to be created. The target material is
deposited over the whole area of the wafer, reaching
the surface of the substrate in the etched regions and
staying on the top of the sacrificial layer in the regions,
where it was not previously etched. When the sacrificial
layer is washed away (photoresist in a solvent), the
material on the top is lifted-off and washed together
with the sacrificial layer below. After the lift-off, the
target material remains only in the regions where it had
a direct contact with the substrate.
• Substrate is prepared
• Sacrificial layer is deposited and an inverse pattern is
created (ex. photoresist is exposed and developed.
Depending on the resist various methods can be
used, such as Extreme ultraviolet lithography - EUVL
or Electron beam lithography - EBL. The photoresist
is removed in the areas, where the target material is
to be located, creating an inverse pattern.)
Lift-off process steps: I. Preparation of
the substrate II. Deposition of the
sacrificial stencil layer III. Patterning
the sacrificial layer (ex. etching),
creating an inverse pattern IV.
Depostion of the target material V.
Washing out the sacrificial layer
together with the target material on its
surface VI. Final pattern Layers: 1)
Substrate 2) Sacrificial layer 3) Target
• Target material (usually a thin metal layer) is deposited (on the whole surface of the
wafer). This layer covers the remaining resist as well as parts of the wafer that were
cleaned of the resist in the previous developing step.
• The rest of the sacrificial material (ex. photoresist) is washed out together with parts of
the target material covering it, only the material that was in the "holes" having direct
contact with the underlying layer (substrate/wafer) stays
Lift-off is applied in cases where a direct etching of structural material would have
undesirable effects on the layer below.
There are 3 major problems with lift-off:
This is the worst problem for liftoff processes. If this problem occurs, unwanted parts
of the metal layer will remain on the wafer. This can be caused by different situations.
The resist below the parts that should have been lifted off could not have dissolved
properly. Also, it is possible that the metal has adhered so well to the parts that should
remain that it prevents lift-off.
Lift-off (microtechnology)
When the metal is deposited, and it covers the sidewalls of the resist, "ears" can be
formed. These are made of the metal along the sidewall which will be standing
upwards from the surface. Also, it is possible that these ears will fall over on the
surface, causing an unwanted shape on the substrate.
If the ears remain on the surface, the risk remains that these ears will go through different
layers put on top of the wafer and they might cause unwanted connections.
During the liftoff process it is possible that particles of metal will become reattached
to the surface, at a random location. It is very difficult to remove these particles after
the wafer has dried.
Lift-off process is used mostly to create metallic interconnections.
There are several types of lift-off processes, and what can be achieved depends highly on
the actual process being used. Very fine structures have been used using EBL, for instance.
The lift-off process can also involve multiple layers of different types of resist. This can for
instance be used to create shapes that will prevent side walls of the resist being covered in
the metal deposition stage.
External links
• http:/ / www. siliconfareast. com/ lift-off. htm
• https:/ / www. mems-exchange. org/ catalog/ lift_off/
• http:/ / matthieu. lagouge. free. fr/ microtechnology/ lift-off. html
Low temperature co-fired ceramic
Low temperature co-fired ceramic
Low temperature co-fired ceramic (LTCC) is a
well-established multi-layer technology which has been
in use for many years in the microelectronics packaging
industry. Each of the layers are processed in parallel
and only brought together in an accurately aligned
stack immediately prior to firing. This is the key
differentiator to serially produced multi-layer structures
such as thick film hybrid interconnect and components
such as ceramic capacitors. LTCC technology is
especially beneficial for RF and high-frequency applications. In RF and wireless
applications, LTCC technology is also used to produce multilayer hybrid integrated circuits,
which can include resistors, inductors, capacitors, and active components in the same
package. LTCC hybrids have a smaller initial ("non recurring") cost as compared with ICs,
making them an attractive alternative to ASICs for small scale integration devices.
This technology presents advantages compared to other packaging technologies such as
HTCC: the ceramic is generally fired below 1000°C due to a special composition of the
material. This permits the co-firing with highly conductive materials (silver, copper and
gold). LTCC also features the ability to embed passive elements, such as resistors,
capacitors and inductors into the ceramic package minimising the size of the completed
Printed resistances: In addition to embedded components, resistors may be added to the
top layer post firing. Using screen printing, a resistor paste is printed onto the LTCC
surface, from which resistances needed in the circuit are generated. When fired, these
resistors deviate from their design value (±25%) and therefore require adjustment to meet
the final tolerance . With → Laser trimming one can achieve these resistances with different
cut forms to the exact resistance value (±1%) desired. With this procedure, the need for
additional discrete resistors can be reduced, thereby allowing a further miniaturization of
the printed circuit boards.
External links
C-MAC MicroTechnology [1]
LTCC Technology [2]
Kyocera LTCC [3]
Sacraficial Carbon Paste and Tape for LTCC Micro Channels and Features
Low temperature co-fired ceramic
http:/ / www. cmac. com/ index. php
http:/ / www. ltcc-consulting. com
http:/ / global. kyocera. com/ prdct/ semicon/ semi/ ltcc/ index. html
http:/ / www. thickfilmtech. com/ othrprod. html
MOSIS (Metal Oxide Semiconductor Implementation Service) is probably the oldest (1981)
integrated circuit (IC) foundry service and one of the first Internet services other than
supercomputing services and basic infrastructure such as E-mail or FTP.
MOSIS is operated by the Information Sciences Institute at the University of Southern
California (USC). MOSIS merges multiple IC designs submitted by both companies and
universities onto multi-project wafers (MPW) to share the cost of fabrication among
multiple users.
MOSIS has prototyped more than 50,000 chip designs for businesses, government agencies
and universities. Between 1990 and 2003, some 66,539 students learned chip design in
MOSIS-associated programs and a total of 13,734 designs were fabricated.
Many of the early users of MOSIS were students using IC layout techniques from the
seminal book Introduction to VLSI Design (ISBN ) by Caltech professors Carver Mead [1]
and Lynn Conway [2].
Some early RISC processors such as SPARC and MIPS were run through MOSIS during
their early design and testing phases.
External links
[1] http:/ / web. mit. edu/ invent/ a-winners/ a-mead. html
[2] http:/ / www. ieee. org/ organizations/ history_center/ conway. html
[3] http:/ / www. mosis. com/
Metal-induced crystallization
Metal-induced crystallization
Metal-induced crystallization (MIC) is a method by which amorphous silicon, or a-Si, can
be turned into polycrystalline silicon at relatively low temperatures. In MIC an amorphous
Si film is deposited onto a substrate, usually glass or Si, and then capped with a metal, such
as aluminium. The structure is then annealed at temperatures between 150 °C and 400 °C
which causes the a-Si films to be transformed into polycrystalline silicon.
In a variant of this method, called Metal-induced lateral crystallization (MILC), metal is
only deposited on some area of the a-Si. Upon annealing, crystallization starts from the
portion of a-Si which is covered by metal and proceeds laterally. Unlike MIC process, where
metal contamination in the obtained polysilicon is relatively high, the laterally crystallized
silicon in MILC process contains very small amount of metal contamination. The
crystallization speed is low, but is adequate for applications such as fabrication of thin film
transistors. In this case, metal is deposited on the source/drain area of the transistor and
the channel is laterally crystallized.
It has been also shown that applying an electric field increases the speed of lateral
crystallization dramatically. Moreover, the crystallization proceeds unidirectionally.
Metalorganic chemical vapor
Metalorganic chemical vapor deposition (MOCVD) is a → chemical vapor deposition
process that uses metalorganic source gases. For instance, MOCVD may use tantalum
ethoxide (
), to create tantalum pentoxide (
), or Tetrakis Dimethyl
Amino Titanium(IV) (TDMAT) to create → titanium nitride (TiN). One may use Nickel
Carbonyl metal organic to deposit pure Nickel at low temperatures 140-250 C.
See also
• Metalorganic vapour phase epitaxy (MOVPE), a specific kind of MOCVD used to grow
crystalline substances.
Microfabrication or micromanufacturing are the terms to describe processes of
fabrication of miniature structures, of micrometre sizes and smaller. Historically the
earliest micromanufacturing was used for semiconductor devices in integrated circuit
fabrication and these processes have been covered by the term "→ semiconductor device
microelectromechanical systems (MEMS) and other nanotechnology, where the
technologies from IC fabrication are being re-used, adapted or extended have led to the
extension of the scope and techniques of microfabrication.[1]
Miniaturization of various devices presents challenges in many areas of science and
engineering: physics, chemistry, material science, computer science, ultra-precision
engineering, fabrication processes, and equipment design. It is also giving rise to various
kinds of interdisciplinary research.[1]
micromanufacturing are laser
technology, microlithography,
microfinishing (nanofinishing).
Fields of Use
• Fabrication of integrated
circuits (“microchips”) (see
Synthetic detail of a micromanufactured integrated circuit through
four layers of planarized copper interconnect, down to the polysilicon
(pink), wells (greyish) and substrate (green).
• Microelectromechanical
systems (MEMS), MOEMS, microfluidic devices (ink jet print heads)
• Laser diodes
• Flat Panel Displays (see AMLCD and Thin Film Transistor)
• Sensors (micro-sensors) (biosensors, nanosensors,)
• Nanotubes, fuel cells
Microfabrication technologies originate from the microelectronics industry, and the devices
are usually made on silicon wafers even though glass, plastics and many other → substrate
are in use. Micromachining, semiconductor processing, microelectronic fabrication,
semiconductor fabrication, MEMS fabrication and integrated circuit technology are terms
used instead of microfabrication, but microfabrication is the broad general term.
Traditional machining techniques such as electro-discharge machining, spark erosion
machining, and laser drilling have been scaled from the millimeter size range to
micrometer range, but they do not share the main idea of microelectronics-originated
microfabrication: replication and parallel fabrication of hundreds or millions of identical
structures. This parallelism is present in various imprint, casting and molding techniques
which have successfully been applied in the microregime. For example, injection moulding
of compact discs involves fabrication of micrometer-sized spots on the disc.
Microfabrication processes
Microfabrication is actually a collection of technologies which are utilized in making
microdevices. Some of them have very old origins, not connected to manufacturing, like
lithography or etching. Polishing was borrowed from optics manufacturing, and many of the
vacuum techniques come from 19th century physics research. Electroplating is also a 19th
century technique adapted to produce micrometre scale structures, as are various stamping
and embossing techniques.
To fabricate a microdevice, many processes must be performed, one after the other, many
times repeatedly. These processes typically include depositing a film, patterning the film
with the desired micro features, and removing (or etching) portions of the film. For
example, in memory chip fabrication there are some 30 lithography steps, 10 oxidation
steps, 20 etching steps, 10 doping steps, and many others are performed. The complexity of
microfabrication processes can be described by their mask count. This is the number of
different pattern layers that constitute the final device. Modern microprocessors are made
with 30 masks while a few masks suffice for a microfluidic device or a laser diode.
Microfabrication resembles multiple exposure photography, with many patterns aligned to
each other to create the final structure.
Microfabricated devices are not generally freestanding devices but are usually formed over
or in a thicker support → substrate. For electronic applications, semiconducting substrates
such as silicon wafers can be used. For optical devices or flat panel displays, transparent
substrates such as glass or quartz are common. The substrate enables easy handling of the
micro device through the many fabrication steps. Often many individual devices are made
together on one substrate and then singulated into separated devices toward the end of
Deposition or Growth
Microfabricated devices are typically constructed using one or more thin films (see Thin
film deposition). The purpose of these thin films depends on the type of device. Electronic
devices may have thin films which are conductors (metals), insulators (dielectrics) or
semiconductors. Optical devices may have films which are reflective, transparent, light
guiding or scattering. Films may also have a chemical or mechanical purpose as wells for
MEMS applications. Examples of deposition techniques include:
• → Thermal oxidation
• → sputtering
• evaporative deposition,
• → chemical vapor deposition (CVD)
• → epitaxy
It is often desirable to pattern a film into distinct features or to form openings (or vias) in
some of the layers. These features are on the micrometer or nanometer scale and it is the
patterning technology is what defines microfabrication. The patterning technique typically
uses a 'mask' to define portions of the film which will be removed. Examples of patterning
techniques include:
• → Photolithography
• Shadow Masking
Etching is the removal of some portion of the thin film or substrate. The substrate is
exposed to an etching (such as an acid or plasma) which chemically or physically attacks
the film until it is removed. Etching techniques include:
• Dry etching (→ Plasma etching) such as Reactive-ion etching (RIE) or Deep reactive-ion
• Wet etching or Chemical Etching
A wide variety of other processes for cleaning, planarizing, or modifying the chemical
properties of the microfabricated devices can also be performed. Some examples include:
→ Doping by either thermal diffusion or ion implantation
→ Chemical-mechanical planarization (CMP)
Wafer cleaning, also known as "surface preparation" (see below)
→ Wire bonding
Micro cutting / microfabrication
Micro cutting/milling is an alternative to lithographic techniques, by downscaling macro
processes such as cutting and forming, to tool sizes under 100 µm in diameter.
Cleanliness in wafer fabrication
Microfabrication is carried out in → cleanrooms, where air has been filtered of particle
contamination and temperature, humidity, vibrations and electrical disturbances are under
stringent control. Smoke, dust, bacteria and cells are micrometers in size, and their
presence will destroy the functionality of a microfabricated device.
Cleanrooms provide passive cleanliness but the wafers are also actively cleaned before
every critical step. RCA-1 clean in ammonia-peroxide solution removes organic
contamination and particles; RCA-2 cleaning in hydrogen chloride-peroxide mixture
removes metallic impurities. Sulfuric acid-peroxide mixture (a.k.a. Piranha) removes
organics. Hydrogen fluoride removes native oxide from silicon surface. These are all wet
cleaning steps in solutions. Dry cleaning methods include oxygen and argon plasma
treatments to remove unwanted surface layers, or hydrogen bake at elevated temperature
to remove native oxide before → epitaxy. Pre-gate cleaning is the most critical cleaning step
in CMOS fabrication: it ensures that the ca. 2 nm thick oxide of a MOS transistor can be
grown in an orderly fashion. Oxidation, and all high temperature steps are very sensitive to
contamination, and cleaning steps must precede high temperature steps.
Surface preparation is just a different viewpoint, all the steps are the same as described
above: it is about leaving the wafer surface in a controlled and well known state before you
start processing. Wafers are contaminated by previous process steps (e.g. metals
bombarded from chamber walls by energetic ions during → ion implantation), or they may
have gathered polymers from wafer boxes, and this might be different depending on wait
Wafer cleaning and surface preparation work a little bit like the machines in a bowling
alley: first they remove all unwanted bits and pieces, and then they reconstruct the desired
pattern so that the game can go on.
See also
Semiconductor fabrication
Integrated circuit
• Microfluidics
• 3D microfabrication
[1] Nitaigour Premchand Mahalik (2006) "Micromanufacturing and Nanotechnology", Springer, ISBN 3540253777
Journal of Microelectromechanical Systems (J.MEMS)
Sensors and Actuators A: Physical
Sensors and Actuators B: Chemical
Journal of Micromechanics and Microengineering
Lab on a Chip
IEEE Transactions of Electron Devices,
Journal of Vacuum Science and Technology A: Vacuum, Surfaces, Films
• Journal of Vacuum Science and Technology B: Microelectronics and Nanometer
Structures: Processing, Measurement, and Phenomena
Books about microfabrication
• (2004)Geschke, Klank & Telleman, eds.: Microsystem Engineering of Lab-on-a-chip
Devices, 1st ed, John Wiley & Sons. ISBN 3-527-30733-8.
• Introduction to Microfabrication (2004) by S. Franssila. ISBN 0470851066
• Fundamentals of Microfabrication (2nd ed, 2002) by M. Madou. ISBN 0849308267
• Micromachined Transducers Sourcebook by Gregory Kovacs (1998)
• Brodie & Murray: The Physics of Microfabrication (1982),
• D. Widmann, H. Mader, H. Friedrich: Tehnology of Integrated Circuits (2000),
• J. Plummer, M.Deal, P.Griffin: Silicon VLSI Technology (2000),
• G.S. May & S.S. Sze: Fundamentals of Semiconductor Processing (2003),
• P. van Zant: Microchip Fabrication (2000, 5th ed),
• R.C. Jaeger: Introduction to Microelectronic Fabrication (2001, 2nd ed),
• S. Wolf & R.N. Tauber: Silicon Processing for the VLSI Era, Vol 1: Process technology
(1999, 2nd ed),
• S.A. Campbell: The Science and Engineering of Microelectronic Fabrication (2001, 2nd
• T. Hattori: Ultraclean Surface Processing of Silicon Wafers : Secrets of VLSI
External links
• Videos and animations on microfabrication techniques and related applications (http:/ /
www. memsuniverse. com/ ?p=1156).
Multi-project wafer service
Multi-Project Chip (MPC) or Multi-Project Wafer (MPW) services integrate onto
microelectronics wafers a number of different integrated circuit designs from various teams
including designs from private firms, students and researchers from universities. Because
IC fabrication costs are extremely high, it makes sense to share mask and wafer resources
to produce designs in low quantities. Worldwide, several MPW services are available from
government-supported institutions or from private firms including MOSIS, CMP and
The first well known MPW service was → MOSIS (Metal Oxide Silicon Implementation
Service), established by DARPA as a technical and human infrastructure for VLSI. MOSIS
began in 1981 after Lynn Conway organized the first VLSI System Design Course at M.I.T.
in 1978. MOSIS primarily services commercial users now but continues to serve university
students and researchers.
With MOSIS, designs are submitted for fabrication using either open (i. e., non-proprietary)
VLSI layout design rules or vendor proprietary rules. Designs are pooled into common lots
and run through the fabrication process at foundries. The completed chips (packaged or
unpackaged) are returned to customers.
Many silicon fabrication facilities offer MPW runs or a company can produce its own MPW,
e.g. combine several of its own designs to form one wafer completely owned by the
company. In the latter case, it may be profitable to use most of the wafer for production
chips and a small portion for producing prototypes of next generation chips.
• The M.I.T. 1978 VLSI System Design Course
[1] http:/ / ai. eecs. umich. edu/ people/ conway/ VLSI/ MIT78/ MIT78. html
Negative bias temperature instability
Negative bias temperature instability
NBTI is one of the methods to accelerate subtle/degrading manufacturing defects that
would otherwise not be detectable during semiconductor circuits production testing.
Negative Bias Temperature Instability (NBTI) is a key reliability issue that is of
immediate concern in p-channel MOS devices stressed with negative gate voltages. NBTI
manifests as an increase in the threshold voltage and consequent decrease in drain current
and transconductance. The degradation exhibits power law dependence with time.
In the sub-micrometer devices nitrogen is incorporated into the gate oxide to address the
issues like higher leakage current and boron penetration. However, incorporating nitrogen
enhances NBTI. It seems possible that nitrogen-based gate stacks would be used even for
the 65 nm node. This is because the development of High-K gate stacks, which are widely
believed to be the eventual alternatives, is taking longer than expected.
It is widely believed that NBTI degradation is due to generation of interface traps, which
are unsaturated silicon dangling bonds. One of the most successful models that has been
able to explain NBTI phenomenon is the reaction diffusion model. This model proposes that
the generation of interface traps is because of a hole induced electro-chemical reaction at
the Si-SiO2 interface. In the initial times the degradation is reaction rate controlled,
however, with time the phenomenon becomes diffusion limited.
There is some level of recovery the moment the stress is removed. The amount the device
recovers depends on the length of stress, The longer the stress is, the less the recovery.
The degradation appears to be non-saturating, i.e., the level of non-recovering degradation
increases so long as the stress is applied. The measurement technique used to measure
NBTI has an impact on the amount of recovery seen. In order to overcome the recovery
during the electrical characterization, the on-the-fly technique has been suggested.
Contribution from bulk traps
Bulk traps can also contribute to Vt degradation especially in the thick oxides. The relative
contributions of interface and oxide traps on the Vt degradation is a matter of current
In the 2006 International Electron Devices Meeting, C. Shen and others presented a
ground-breaking paper on ultra-fast NBTI measurements (100ns delay), which provided
new reasons to believe that the Reaction-Diffusion model may not explain the NBTI
mechanism correctly. Shen prefers the hole-trapping mechanism, whereby a hole gets
trapped in a trap state, causing a shift in the threshold voltage.
Negative bias temperature instability
See also
• Hot carrier injection
• Electromigration
• → Device under test
• Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability: Road to
cross in deep submicron silicon semiconductor manufacturing”, Journal of applied
Physics, vol. 94, pp.1-18, July 2003.
• M. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation”,
Microelectronics Reliability, vol. 45, no. 1, pp. 71-81, Jan. 2005.
• C. Shen et al., "Characterization and Physical Origin of Fast Vth Transient in NBTI of
pMOSFETs with SiON Dielectric," IEDM Technical Digest, pp. 333-336, December 2006.
• D.K. Schroder, "Negative bias temperature instability: What do we understand?,"
Microelectronics Reliability, vol. 47, pp. 841-852, June 2007.
Ohmic contact
An ohmic contact is a region on a semiconductor device that has been prepared so that
the current-voltage (I-V) curve of the device is linear and symmetric. If the I-V
characteristic is non-linear and asymmetric, the contact can instead be termed a blocking
or Schottky contact. Typical ohmic contacts on semiconductors are → sputtered or →
evaporated metal pads that are patterned using → photolithography. Low-resistance, stable
contacts are critical for the performance and reliability of integrated circuits and their
preparation and characterization are major efforts in circuit fabrication.
The Fermi level (or strictly speaking, chemical potential) of any two solids in contact must
be equal in thermal equilibrium. The difference between the Fermi energy and the vacuum
level is termed the work function. A contact metal and a semiconductor can have different
work functions, denoted
respectively. If so, when the two materials are placed
in contact, electrons will flow from the one with the lower work function until the Fermi
levels equilibrate. As a result, the material with the lower work function will take on a slight
positive charge while that with the higher work function will become slightly negative. The
resulting electrostatic potential is termed the built-in potential designated by
. This
contact potential will occur between any two solids and is the underlying cause of
phenomena such as rectification in diodes. The built-in field is the cause of band-bending
in the semiconductor near the junction. Noticeable band-bending does not occur in most
metals since their very short screening length means that any electrical field extends only a
short distance beyond the interface.
Ohmic contact
An ohmic contact or Schottky barrier is
formed when a metal and a p-type
semiconductor are brought into
where in MKS units
is the net charge density and is the dielectric constant. The
geometry is one-dimensional since the interface is assumed to be planar. Integrating the
equation once, approximating the charge density as being constant over the depletion
width, we get
The constant of integration
due to the definition of the depletion width as the
length over which the interface is fully screened. Then
where the fact that
has been used to fix the remaining integration constant.
This equation for
describes the dashed blue curves in the right-hand panels of the
figures. The depletion width can then be determined by setting
which results in
For 0 < x < W,
is the net charge density of ionized donor or acceptors
in the completely depleted semiconductor and is the electronic charge. and
positive signs for n-type semiconductors and negative signs for p-type semiconductors
giving the positive curvature
for n-type and negative curvature for p-type as shown
in the figures.
Note from this crude derivation that the barrier height (dependent on electron affinity and
built-in field) and barrier thickness (dependent on built-in field, semiconductor dielectric
constant and doping density) can only be modified by changing the metal or changing the
doping density. In general an engineer will choose a contact metal to be conductive,
non-reactive, thermally stable, electrically stable and low-stress, and then will increase the
doping density below the contact to narrow the width of the barrier region. The highly
doped regions are termed
depending on the carrier type. Since the transmission
coefficient in tunneling depends exponentially on particle mass, semiconductors with lower
effective masses are more easily contacted. In addition, semiconductors with smaller
bandgaps more readily form ohmic contacts because their electron affinities (and thus
barrier heights) tend to be lower.
Ohmic contact
The simple theory presented above predicts that
, so naively metals whose
work functions are close to the semiconductor's electron affinity should most easily form
ohmic contacts. In fact, metals with high work functions form the best contacts to p-type
semiconductors while those with low work functions form the best contacts to n-type
semiconductors. Unfortunately experiments have shown that the predictive power of the
model doesn't extend much beyond this statement. Under realistic conditions, contact
metals may react with semiconductor surfaces to form a compound with new electronic
properties. A contamination layer at the interface may effectively widen the barrier. The
surface of the semiconductor may reconstruct leading to a new electronic state. The
dependence of contact resistance on the details of the interfacial chemistry is what makes
the reproducible fabrication of ohmic contacts such a manufacturing challenge.
Preparation and characterization of ohmic contacts
The fabrication of ohmic contacts is a much-studied part of materials engineering that
nonetheless remains something of an art. The reproducible, reliable fabrication of contacts
relies on extreme cleanliness of the semiconductor surface. Since a native oxide rapidly
forms on the surface of silicon, for example, the performance of a contact can depend
sensitively on the details of preparation.
The fundamental steps in contact fabrication are semiconductor surface cleaning, contact
metal deposition, patterning and annealing. Surface cleaning may be performed by
sputter-etching, chemical etching, reactive gas etching or ion milling. For example, the
native oxide of silicon may be removed with an HF dip, while GaAs is more typically cleaned
by a bromine-methanol dip. After cleaning, metals are deposited via → sputter deposition, →
evaporation or → chemical vapor deposition (CVD). Sputtering is a faster and more
convenient method of metal deposition than evaporation but the ion bombardment from the
plasma may induce surface states or even invert the charge carrier type at the surface. For
this reason the gentler but still rapid CVD is increasingly preferred. Patterning of contacts
is accomplished with standard photolithographic methods such as lift-off, where contact
metal is deposited through holes in a photoresist layer that is later dissolved away.
Post-deposition annealing of contacts is useful for relieving stress as well as for inducing
any desirable reactions between the metal and the semiconductor.
The measurement of contact resistance is most simply performed using a four-point probe
although for more accurate determination, use of the transmission line method is typical.
Technologically important kinds of contacts
Modern ohmic contacts to silicon such as titanium-tungsten disilicide are usually silicides
made by CVD. Contacts are often made by depositing the transition metal and forming the
silicide by annealing with the result that the silicide may be non-stoichiometric. Silicide
contacts can also be deposited by direct sputtering of the compound or by ion implantation
of the transition metal followed by annealing. Aluminum is another important contact metal
for silicon which can be used with either the n-type or p-type semiconductor. As with other
reactive metals, Al contributes to contact formation by consuming the oxygen in the native
oxide. Silicides have largely replaced Al in part because the more refractory materials are
less prone to diffuse into unintended areas especially during subsequent high-temperature
Ohmic contact
Formation of contacts to compound semiconductors is considerably more difficult than with
silicon. For example, GaAs surfaces tend to lose arsenic and the trend towards As loss can
be considerably exacerbated by the deposition of metal. In addition, the volatility of As
limits the amount of post-deposition annealing that GaAs devices will tolerate. One solution
for GaAs and other compound semiconductors is to deposit a low-bandgap alloy contact
layer as opposed to a heavily doped layer. For example, GaAs itself has a smaller bandgap
than AlGaAs and so a layer of GaAs near its surface can promote ohmic behavior. In general
the technology of ohmic contacts for III-V and II-VI semiconductors is much less developed
than for Si.
Contact materials
Al, Al-Si, TiSi2, → TiN, W, MoSi2, PtSi, CoSi2, WSi2
In, AuGa, AuSb
, PdGe, Ti/Pt/Au
, Pd/Au
InSnO2, Al
Mo, InSnO2
Transparent or semi-transparent contacts are necessary for active matrix LCD displays,
optoelectronic devices such as laser diodes and photovoltaics. The most popular choice is
indium tin oxide, a metal that is formed by reactive sputtering of an In-Sn target in an oxide
The RC time constant associated with contact resistance can limit the frequency response
of devices. The charging and discharging of the leads resistance is a major cause of power
dissipation in high clock rate digital electronics. Contact resistance causes power
dissipation via Joule heating in low frequency and analog circuits (for example, solar cells)
made from less common semiconductors. The establishment of a contact fabrication
methodology is a critical part of the technological development of any new semiconductor.
Electromigration and delamination at contacts are also a limitation on the lifetime of
electronic devices.
• Sze, S.M. (1981). Physics of Semiconductor Devices. John Wiley & Sons. ISBN
0-471-05661-8. Discussion of theory plus device implications.
• Zangwill, Andrew (1988). Physics at Surfaces. Cambridge University Press. ISBN
0-521-34752-1. Approaches contacts from point of view of surface states and
Ohmic contact
See also
• The American Vacuum Society
has an excellent short course
on this topic.
• Journal of the American Vacuum Society [6], Thin Solid Films [7] and Journal of the
Electrochemical Society [8] are journals that publish current research on ohmic contacts.
[1] http:/ / www. semiconfareast. com/ ohmic_table. htm
[2] http:/ / scitation. aip. org/ getabs/ servlet/ GetabsServlet?prog=normal&
id=JVTBD9000020000004001444000001& idtype=cvips& gifs=yes
[3] http:/ / scitation. aip. org/ getabs/ servlet/ GetabsServlet?prog=normal&
id=APPLAB000073000020002953000001& idtype=cvips& gifs=yes
http:/ / www. avs. org/
http:/ / www. avs. org/ course. instructor. static. popup. aspx?FileName=semicontacts
http:/ / www. avs. org/ literature. aspx
http:/ / www. elsevier. com/ locate/ issn/ 00406090
http:/ / www. electrochem. org/ publications/ jes/ journal. htm
Overlay Control
Silicon wafers are currently manufactured in a sequence of steps, each stage placing a
pattern of material on the wafer; in this way transistors, contacts, etc., all made of different
materials, are laid down. In order for the final device to function correctly, these separate
patterns must be aligned correctly - for example contacts, lines and transistors must all line
Overlay control is the term used to define the control of this pattern-to-pattern alignment.
It has always played an important role in → semiconductor manufacturing, helping to
monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind
can cause short circuits and connection failures, which in turn impact fab yield and profit
Overlay control has become even more critical now because the combination of increasing
pattern density and innovative techniques such as double patterning and 193nm immersion
lithography creates a novel set of pattern-based yield challenges at the 45nm technology
node and below. This combination causes error budgets to shrink below 30 percent of
design rules, where existing overlay metrology solutions cannot meet total measurement
uncertainty (TMU) requirements.
Overlay metrology solutions with both higher measurement accuracy/precision and process
robustness are key factors when addressing increasingly tighter overlay budgets. Higher
order overlay control and in-field metrology using smaller, micro-grating or other novel
targets are becoming essential for successful production ramps and higher yields at 45nm
and beyond.
Examples of the widely adopted overlay measurement tools worldwide are KLA-Tencor's
ARCHER [1], and the nanometrics [2] CALIPER series, overlay metrology platforms.
Overlay Control
[1] http:/ / www. kla-tencor. com/ archer
[2] http:/ / www. nanometrics. com
PROLITH (abbreviated from Positive Resist Optical LITHography) is a computer simulator
modeling the optical and chemical aspects of → photolithography. Chris Mack started
developing PROLITH after he began working in the field of photolithography at the NSA in
PROLITH was first developed on an IBM PC. The models implemented by the software were
based on the work done by Rick Dill at IBM and Andy Neureuther at UC Berkley, together
with Chris Mack's own contributions such as the Mack model.
Originally PROLITH was given away for free, while NSA was paying Chris Mack's salary.[1]
In 1990 he founded FINLE Technologies to commercialize PROLITH. The first
commercial version of the software, named PROLITH/2, was released in June of that year.
PROLITH was made easier to use and it grew to include many more aspects of lithography
FINLE Technologies was purchased in February 2000 by KLA-Tencor, which now markets
External links
• [3]
[1] " 30 Years of Lithography Simulation — Chris Mack's account of progress in lithography simulation and
PROLITH (http:/ / www. lithoguru. com/ scientist/ litho_papers/ 2005_Thirty_Years_of_Lithography_Simulation.
pdf)". .
[2] " Chris Mack's resume (http:/ / www. lithoguru. com/ scientist/ resume. html)". .
[3] http:/ / www. kla-tencor. com/ computational-lithography/ prolith. html
Package on package
Package on package
Package on Package (PoP) is an → integrated circuit packaging technique to allow
vertically combining discrete logic and memory ball grid array (BGA) packages. Two or
more packages are installed on top of one another, i.e. stacked, with a standard interface to
route signals between them. This allows higher density, for example in the mobile
telephone / PDA market.
Typical Configurations
There are two widely used configurations for PoP:
• Pure memory stacking (two or more memory only packages are stacked on top of each
• Logic package in the bottom, memory package on top. For example, the bottom could be
an application processor for a cell phone. The logic package goes on the bottom because
it requires many more BGA connections to the motherboard.
Typical Logic plus memory PoP stack, common to cellphone application processors or baseband modems from 2005
The most obvious benefit is motherboard space savings. PoP shares this trait with
stacked-die packages. However there are several key differences between stacked-die and
stacked-package products.
The main financial benefit of package on package is that the memory device is decoupled
from the logic device. Thus:
• The memory package can be tested separately from the logic package
• Only "known good" packages are used in final assembly (if the memory is bad only the
memory is thrown away and so on). Compare this to stacked-die packages where the
entire set is thrown away if either the memory or logic is bad.
• The end user (example cell phone maker or digital camera maker) controls the logistics.
This means they can source the memory as they see fit. This month the memory can be
from Samsung, next month it could be from Numonyx. The memory becomes a
commodity to be sourced from the lowest priced supplier. This particular point is also a
Package on package
benefit compared to PiP (package in package) which requires a specific memory device to
be designed in and sourced upstream of the end user.
• Because the construction is like Lego any mechanically mating top package can be used.
For a low-end phone a smaller memory configuration may be used on the top package.
For a high-end phone more memory could be used, with the same bottom package. This
simplifies inventory control by the OEM. For a stacked-die package or even PiP (package
in package), the exact memory configuration needs to be known weeks (or months) in
• Because the memory only comes into the mix at final assembly, there is no reason for
logic suppliers to source any memory. With a stacked-die device, the logic provider (such
as Qualcomm) would need to buy wafers of memory from a supplier such as Numonyx.
Electrically, PoP offers benefits by minimizing track length between, for example, a
controller and a memory. This results in better electrical performance of the devices, since
the shorter routing of interconnections between circuits results in faster signal propagation
and reduction in noise and cross-talk.
JEDEC Standardization
• JEDEC JC-11 committee deals with package outline drawing standards related to the
bottom PoP package. See documents MO-266A and JEDEC publication 95, Design Guide
• JEDEC JC-63 committee deals with top (memory) PoP package pinout standardization.
See JEDEC Standard No. 21-C, Page 3.12.2 – 1
Other Names
Package on package is also known by other names:
• PoP (which refers to the combined top and bottom packages)
• PSvfBGA [1] refers to the bottom package (Stands for Package Stackable Very thin Fine
pitch BGA)
• PSfcCSP refers to the bottom package (Stands for Package Stackable Flip Chip Chip
Scale Package)
External links
• 3D & Stacked-Die Packaging Technology Solutions. [2]
• Practical Components PoP Samples and Test Boards (daisy chains)
• Package-on-Package: The Story Behind This Industry Hit (Semiconductor International,
6/1/2007) [4]
• Package-on-package is killer app for handsets (EETimes Article July 2008) [5]
• SMT PoP Presentation Video [6]
• "POP" Goes the Future (Assembly Magazine, 9/30/2008) [7]
• The BeagleBoard [8] uses a PoP processor
• Killer app for cell handsets EETimes 10/20/2008 [9]
• TMV: An ‘Enabling’ Technology for Next-Gen PoP Requirements Semicon International
11/04/2008 [10]
• Paste Dipping Isn't So Bad After All 2/5/2009 [11]
• Vapor Phase vs. Convection Reflow in Package-on-Package Technology 7/21/2009
Package on package
• POP (Package On Package): An Ems Perspective On Assembly, Rework And Reliability
02/12/2009 [13]
[1] http:/ / www. amkor. com/ go/ packaging/ all-packages/ psvfbga/
[2] http:/ / www. amkor. com/ go/ packaging/ all-packages/ 3d-and-stacked-die-packaging-technology-solutions/
[3] http:/ / www. practicalcomponents. com/ amkor/ amkor-pop. htm
[4] http:/ / www. semiconductor. net/ article/ CA6445430. html
[5] http:/ / www. eetimes. com/ news/ semi/ rss/ showArticle. jhtml?articleID=209900383&
[6] http:/ / www. brightcove. tv/ title. jsp?title=1827939905
[7] http:/ / www. assemblymag. com/ CDA/ Articles/ Feature_Article/
[8] http:/ / beagleboard. org/
[9] http:/ / www. eetimes. com/ news/ design/ showArticle. jhtml?articleID=211201709
[10] http:/ / www. semiconductor. net/ article/ CA6611115. html?desc=topstory
[11] http:/ / blog. screamingcircuits. com/ 2009/ 02/ paste-dipping-isint-so-bad-after-all. html
[12] http:/ / smt. pennnet. com/ display_article/ 366357/ 35/ ARTCL/ none/ HMST/ 1/
[13] http:/ / smta. org/ knowledge/ proceedings_abstract. cfm?PROC_ID=2649
Phenol formaldehyde resin
The earliest commercial synthetic
resin is based on a Phenol
formaldehyde resin (PF) with the
commercial name Bakelite, and is
formaldehyde. Phenol is reactive
towards formaldehyde at the ortho
and para sites (sites 2, 4 and 6)
allowing up to 3 units of
formaldehyde to attach to the ring.
phenol. The hydroxymethyl group
is capable of reacting with either
another free ortho or para site, or
group. The first reaction forms a
methylene bridge, and the second
forms an ether bridge.
Example of a possible structure in a PF resin.
Phenol formaldehyde resins, as a group, are formed by a step-growth polymerization
reaction which may be either acid or base catalysed. The pathway the reaction follows
varies depending on the catalyst type used.
Phenol formaldehyde resin
Acid catalysed
Acid catalysed phenol formaldehyde resins are made with a molar ratio of formaldehyde to
phenol of less than one and are called novolacs. Owing to the molar ratio of formaldehyde
to phenol, they will not completely polymerize without the addition of a crosslinking agent.
Novolacs are commonly used as photoresists. See also → photolithography.
Base catalysed
Common cross-linker used for this resin is paraformaldehyde.
Base catalysed phenol formaldehyde resins are made with a formaldehyde to phenol ratio of
greater than one (usually around 1.5). Phenol, formaldehyde, water and catalyst are mixed
in the desired amount, depending on the resin to be formed, and are then heated. The first
part of the reaction, at around 70 °C, forms hydroxymethyl phenols. This results in a thick
reddish-brown goo, the resin.
The rate of the base catalysed reaction initially increases with pH, and reaches a maximum
at approx. pH = 10. The reactive species is the phenolic anion formed by deprotonation of
phenol. The negative charge is delocalised over the aromatic ring, activating sites 2, 4 and
6, which then react with the formaldehyde.
Formaldehyde in solution does not exist as the aldhehyde, but instead a dynamic
equilibrium is formed creating a range of methylene glycol oligomers, and the
concentration of the reactive form of formaldehyde depends on the exact conditions
(temperature, pH) under which the reaction occurs. Thus the reaction rate law describing
phenol and formaldehyde is not a simple one, and the chemical kinetics are highly complex.
Hydroxymethyl phenols will crosslink on heating to around 120 °C to form methylene and
methyl ether bridges. At this point the resin is starting to crosslink, to form the highly
extended 3-dimensional web of covalent bonds which is typical of polymerised phenolic
resins. It is this highly crosslinked nature of phenolics which gives them their hardness and
their good thermal stability and which makes them impervious to most chemical attack and
solvation. It is also the reason they are called thermosets.
Crosslinking and the phenol/formaldehyde ratio
Phenol can react with formaldehyde at any one of three possible sites, and formaldehyde
can react with up to two phenols. Thus the theoretical functionality of phenol is three and
the theoretical functionality of formaldehyde is two. The actual functionality that is found in
the polymer depends on the phenol:formaldehyde ratio.
By adding a small amount of acid catalyst to phenol (something miscible, such as
p-toluenesulfonic acid) and slowly adding formaldehyde, the formaldehyde will react
between two phenols to form a methylene bridge, creating a dimer. This dimer is the
substance bisphenol F, which is itself an important monomer in the production of epoxy
resins. At higher concentrations of these dimers, there is the possibility of generating
trimers, tetramers and higher oligomers. This is what occurs during the formation of
bakelite. The average molecule generated depends on the ratio of formaldehyde to phenol.
In bakelite this is usually around 0.8, and so, with 5 phenols for every 4 formaldehydes the
average molecule is a pentamer (with respect to phenol).
When the molar ratio of formaldehyde:phenol reaches one, in theory every phenol is linked
together via methylene bridges, generating one single molecule, and the system is entirely
Phenol formaldehyde resin
crosslinked. This is why bakelites (F:P <1) don't harden without the addition of a
crosslinking agent, and why resins with the formula F:P >1 will.
See also
• Phenolic resin
External links
• Safety data for phenol-formaldehyde resin
[1] http:/ / physchem. ox. ac. uk/ MSDS/ PH/ phenol_formaldehyde_resin. html
Phosphosilicate glass
Phosphosilicate glass, commonly referred to by the acronym PSG, is a → silicate glass
commonly used in semiconductor device fabrication for intermetal layers, i.e., insulating
layers deposited between succeedingly higher metal or conducting layers. Another common
species of phosphosilicate glass is → BPSG or → borophosphosilicate glass.
Soda-lime phosphosilicate glasses also form the basis for bioactive glasses (e.g. Bioglass), a
(hydroxy-carbonate-apatite) in physiological fluid.
See also
• → Wafer (electronics)
Planar process
Planar process
The planar process is a manufacturing process used in the semiconductor industry to
build individual components of a transistor, and in turn, connect those transistors together.
It is the primary process by which modern integrated circuits are built. The process was
developed[1] [2] by Jean Hoerni, one of the Traitorous Eight, while working at Fairchild
The key concept was to view a circuit in its two-dimensional projection (a plane), thus
allowing the use of photographic processing concepts such as film negatives to mask the
projection of light exposed chemicals. This allowed the use of a series of exposures on a
substrate (Silicon) to create silicon oxide (insulators) or doped regions (conductors).
Together with the use of metallization (to join together the integrated circuits), and the
concept of p-n junction isolation (from Kurt Lehovec), the researchers at Fairchild were
able to create circuits on a single silicon crystal slice (a wafer) from a monocrystalline
silicon boule.
The process involves the basic procedures of silicon dioxide (SiO2) oxidation, SiO2 etching
and heat diffusion. The final steps involves oxidizing the entire wafer with an SiO2 layer,
etching contact vias to the transistors, and depositing a covering metal layer over the oxide,
thus connecting the transistors without manually wiring them together.
• The Planar Process [3]
• Invention of the “Planar” Manufacturing Process
[1] US patent 3025589 (http:/ / v3. espacenet. com/ textdoc?DB=EPODOC& IDX=US3025589) Hoerni, J. A.:
"Method of Manufacturing Semiconductor Devices” filed May 1, 1959
[2] US patent 3064167 (http:/ / v3. espacenet. com/ textdoc?DB=EPODOC& IDX=US3064167) Hoerni, J. A.:
"Semiconductor device" filed May 15, 1960
[3] http:/ / nobelprize. org/ nobel_prizes/ physics/ articles/ lecuyer/ planar. html
[4] http:/ / www. computerhistory. org/ semiconductor/ timeline/
1959-invention-of-the-planar-manufacturing-process-24. html
Plasma cleaning
Plasma cleaning
Plasma cleaning involves the removal of impurities and contaminants from surfaces
through the use of an energetic plasma created from gaseous species. Gases such as argon
and oxygen, as well as mixtures such as air and hydrogen/nitrogen are used. Lower energy
plasmas are used for plasma cleaning versus plasma etching operations. The plasma is
created by using high radio-frequency to ionize a low pressure gas phase(usually
13.56Mhz). The pressures of the gaseous species are typically below 1 torr. The energetic,
ionic species react with species on the surface of the item to be cleaned, often producing
gaseous products which can be removed by a vacuum system. The energetic species also
clean the surface by collision with the surface, knocking off species from the surface. Very
high temperatures are involved in the process. Prolonged or higher power plasma cleaning
etches the surface, going beyond the 'cleaning' phase.
Plasma cleaning is a commonly used process in the semiconductor industry which has the
advantage of being solvent free, thus producing less waste.
Plasma etcher
A plasma etcher, or etching tool, is a tool used in the production of semiconductor
devices. Plasma etcher produces a plasma from a process gas, typically oxygen or a fluorine
bearing gas, using a high frequency electric field, typically 13.56 MHz. A silicon wafer is
placed in the plasma etcher, and the air is evacuated from the process chamber using a
system of vacuum pumps. Then a process gas is introduced at low pressure, and is excited
into a plasma through dielectric breakdown.
Plasma can be used to grow a silicon dioxide film on a silicon wafer (using an oxygen
plasma), or can be used to remove silicon dioxide by using a fluorine bearing gas. When
used in conjunction with → photolithography, silicon dioxide can be selectively applied or
removed to trace paths for circuits.
For the formation of integrated circuits it is necessary to structure various layers. This can
be done by a plasma etcher. Before etching, a photo → resist is deposited on the surface,
illuminated through a mask, and developed. The dry etch is then performed so that
structured etching is achieved. After the process, the remaining photo resist has to be
removed. This is also done in a special plasma etcher, called an Asher.
Dry etching allows a reproducible, uniform etching of all materials used in silicon and
III-V-semiconductor technology.
Plasma etchers are also used for delayering integrated circuits in failure analysis
Plasma etching
Plasma etching
Plasma etching is a form of plasma processing used to fabricate integrated circuits. It
involves a high-speed stream of glow discharge (plasma) of an appropriate gas mixture
being shot (in pulses) at a sample. The plasma source, known as etch species, can be either
charged (ions) or neutral (atoms and radicals). During the process, the plasma will generate
volatile etch products at room temperature from the chemical reactions between the
elements of the material etched and the reactive species generated by the plasma.
Eventually the atoms of the shot element embed themselves at or just below the surface of
the target, thus modifying the physical properties of the target.
Plasma generation
Plasma systems ionize a variety of source gases in a vacuum system by using RF
excitations. The frequency of operation of the RF power source is frequently 13.56 MHz,
chosen by the Federal Communications Commission (FCC) for industrial and scientific use.
Nevertheless, it can be used at lower frequencies (kilohertz) or higher (microwave).
The mode of operation of the plasma system will change if the operating pressure changes.
Also, it is different for different structures of the reaction chamber. In the simple case, the
electrode structure is symmetrical, and the sample is placed upon the grounded electrode.
Free radicals such as fluorine or chlorine are created in the plasma and react at the sample
Without the assistance of the plasma, much higher temperature would be required. The low
processing temperature is possible because the plasma generates atoms, molecular radicals
and positive ions that are more chemically reactive than the normal molecular gases from
which the species are created.
The key to develop successfully complex etching processes is to find the appropriate gas
etch chemistry that will form volatile products with the material to be etched. For some
difficult materials (magnetic materials for example), the volatility can only be obtained
when the wafer temperature is increased.
See also
• → Plasma etcher
External links
• Plasma Etch Fundamentals
Plasma-immersion ion implantation
Plasma-immersion ion implantation
Plasma-immersion ion implantation (PIII)[1] or pulsed-plasma doping (pulsed PIII) is a
surface modification technique of extracting the accelerated ions from the plasma by
applying a high voltage pulsed DC or pure DC power supply and targeting them into a
suitable substrate or electrode with a semiconductor → wafer placed over it, so as to
implant the it with suitable dopants. The electrode is a cathode for an electropositive
plasma, while it is an anode for an electronegative plasma. Plasma can be generated in a
suitably designed vacuum chamber with the help of various plasma sources such as
Electron Cyclotron Resonance plasma source which yields plasma with the highest ion
density and lowest contamination level, helicon plasma source, capacitively coupled plasma
source, inductively coupled plasma source, DC glow discharge and metal vapor arc(for
metallic species). The vacuum chamber can be of two types - diode and triode type[2]
depending upon whether the power supply is applied to the substrate as in the former case
or to the perforated grid as in the latter.
In a conventional immersion
type of PIII system, also called
the wafer is
kept at a negative potential
since the positively charged
ions of the electropositive
plasma are the ones who get
extracted and implanted. The
wafer sample to be treated is
placed on a sample holder in a
vacuum chamber. The sample
holder is connected to a high
voltage power supply and is
Conventional or diode type Plasma Immersion Ion Implanter
electrically insulated from the
chamber wall. By means of
pumping and gas feed systems, an atmosphere of a working gas at a suitable pressure is
When the substrate is biased to a negative voltage (few KV's), the resultant electric field
drives electrons away from the substrate in the time scale of the inverse electron plasma
frequency ωe-1 ( ~ l0-9 sec). Thus an ion matrix Debye sheath[2] [4] which is depleted of
electrons forms around it. The negatively biased substrate will accelerate the ions within a
time scale of the inverse ion plasma frequency ωi-1 ( ~ 10-6 sec). This ion movement lowers
the ion density in the bulk, which causes the sheath-plasma boundary to expand in order to
sustain the applied potential drop,in the process exposing more ions. The plasma sheath
expands until either a steady-state condition is reached, which is called Child Langmuir law
limit; or the high voltage is switched off as in the case of Pulsed DC biasing. Pulse biasing is
preferred over DC biasing because it creates less damage during the pulse ON time and
Plasma-immersion ion implantation
neutralization of unwanted charges accumulated on the wafer in the afterglow period (i.e.
after the pulse has ended). In case of pulsed biasing the TON time of the pulse is generally
kept at 20-40 µs, while the TOFF is kept at 0.5-2 ms i.e. a duty cycle of 1-8%. The power
supply used is in range of 500 V to hundreds of KV and the pressure in the range of 1-100
mTorr. This is the basic principle of the operation of immersion type PIII.
In case of a triode type configuration, a suitable perforated grid is placed in between the
substrate and the plasma and a pulsed DC bias is applied to this grid. Here the same theory
applies as previously discussed, but with a difference that the extracted ions from the grid
holes bombard the substrate, thus causing implantation. In this sense a triode type PIII
implanter is a crude version of → ion implantation because it does not contain plethora of
components like ion beam steering, beam focusing, additional grid accelerators etc.
Other sources
C.R. Viswanathan, "Plasma induced damage," Microelectronic Engineering, Vol. 49, No.
1-2, November 1999, pp. 65–81.
[1] Milton Ohring (2002). Materials Science of Thin Films (http:/ / books. google. com/ books?id=SOt_yFjV-xwC&
pg=PA267& dq="Plasma+ immersion+ ion+ implantation"& lr=& as_brr=0& ei=3JrISJnyN4H-sQPdsaTXDA&
sig=ACfU3U1xAKghXqGW8zNi3Nx2ECFiZ0vglw). Academic Press. ISBN 0125249756. .
[2] Michael A. Liberman and Allan J. Lichtenberg, Principles of plasma discharges and material processing, Ed.
New York: John Wiley and Sons, 1994.
[3] W. Ensinger, “Semiconductor processing by plasma immersion ion implantation”, Materials science &
engineering. A., Vol. 253, No. 1 - 2, 1998, pp. 258–268.
[4] André Anders et al., Handbook of Plasma Immersion Ion Implantation and Deposition, Ed. New York: John
Wiley and Sons, 2000.
Process design kit
Process design kit
A Process Design Kit is a set of files used within the → semiconductor industry to model
transistors for a certain technology for a certain foundry.
For example Cadence Virtuoso ships with 25 different PDK's.
Product engineering
Product engineering refers to the process of designing and developing a device,
assembly, or system such that it be produced as an item for sale through some production
manufacturing process. Product engineering usually entails activity dealing with issues of
cost, produce-ability, quality, performance, reliability, serviceability and user features.
These product characteristics are generally all sought in the attempt to make the resulting
product attractive to its intended market and a successful contributor to the business of the
organization that intends to offer the product to that market. It includes design,
development and transitioning to manufacturing of the product. The term encompasses
developing the concept of the product and the design and development of its mechanical,
electronics and software components. For example a product like a digital camera would
include defining the feature set, design of the optics, the mechanical and ergonomic design
of the packaging, developing the electronics that control the various component and
developing the software that allows the user to see the pictures, store it in memory,
download to a computer etc. After the initial design and development is done, transitioning
the product to manufacture it in volumes is considered part of Product Engineering
Product engineering is an engineering discipline that deals with both design and
manufacturing aspects of a product.
Sometimes "Product engineers" are also called "Industrial engineers". They are expected to
have employment growth of 20 percent over the projections decade, faster than the average
for all occupations [1] .
In the field of integrated circuits
Specifically in the field of electronics (i.e. integrated circuits), semiconductor companies
have product engineers to support the production of complex high volume products like
microprocessors, DRAM, digital signal processors or ASIC. Their role is emphasized since
the new generations of technology (90 nm, 65 nm), together with the arrival of new circuit
designs, that have increased side effects difficult to simulate and endanger the fast ramp-up
of the volume manufacturing in the fab.
Product engineering
Area of responsibility
• Product engineers define the yield roadmap and drive the fulfillment during ramp-up and
volume production,
• Identify and realize measures for yield improvement, test optimization and product cost
• Provide DFM Design for manufacturability methods,
• Define qualification plan and perform electrical characterization analysis.
Product engineers are the technical interface between the component development team
and the production side (Front End and Back End), especially after the development phase
and qualifications when the high volume production is running.
Product engineers improve the product quality and secure the product reliability by
balancing cost of test and test coverage that could impact the production fall-off. They
support failure analysis request from customers.
Knowledge and skills
The job requires the product engineer to have a very good working knowledge of:
Statistical methods and tools,
Manufacturing process,
Product reliability and qualification,
Physical analysis methods
Computer-aided design and simulation programs
Specific technology
Automatic test equipment and tools
Strong analytic work methodology and problem solving skills
project management skills
Shmoo plot
Wafer mapAn example of wafer map
Each chip of a wafer, identified on a diagram by its x and y coordinates, is represented by a
specific color or symbol depending on the results of a test. It can be helpful to detect a
process problem if a region differentiates itself from the rest of the wafer with a visual
signature (e.g. spot at the center, donut ring, strip, cluster...) [2] .
Failure analysis
To investigate the root cause of FE (Front-End) / BE (Back-End) yield detractors, or analyse
return from customers, it could be necessary to send the samples to a failure analysis
laboratory. The process in the lab is to verify the failure with a tester, to localize the fault
by Emission microscopy, liquid crystal thermography or E-Beam probing for examples.
Then the physical failure analysis can be conducted by different methods like: FIB (Focused
Ion Beam), SEM (Scanning electron microscope), AFM Atomic force microscope.
Sometimes a circuit correction is even feasible by FIB.
ATE Automatic test equipment
Product engineering
See also
• Electrical Engineering
• Electronic Engineering
• Mechanical Engineering
External links
• [3] Application note "Yield Learning Flow Provides Faster Production Ramp"
• [4] Tutorial about yield impact
[1] " Industrial engineers (http:/ / www. bls. gov/ oco/ ocos027. htm)". Occupational Outlook Handbook. .
Retrieved April 16 2008.
[2] Xavier Templet, "Solutions for efficient volume production of wireless system-on-chip", SAME2007 (http:/ /
www. same-conference. org), ISBN 2-9524014-2-x
[3] http:/ / www. semiconductor. net/ article/ CA6602542. html
[4] http:/ / www. infras. com/ Tutorial/ sld016. htm
Pulsed laser deposition
Pulsed laser deposition (PLD) is a thin film
deposition (specifically a → physical vapor
deposition, PVD) technique where a high power
pulsed laser beam is focused inside a vacuum
chamber to strike a target of the material that is to
be deposited. This material is vaporized from the
target (in a plasma plume) which deposits it as a
thin film on a substrate (such as a silicon wafer
facing the target). This process can occur in ultra
high vacuum or in the presence of a background
gas, such as oxygen which is commonly used when
depositing oxides to fully oxygenate the deposited
A plume ejected from a SrRuO3 target
during pulsed laser deposition.
While the basic-setup is simple relative to many
other deposition techniques, the physical phenomena of laser-target interaction and film
growth are quite complex (see Process below). When the laser pulse is absorbed by the
target, energy is first converted to electronic excitation and then into thermal, chemical and
mechanical energy resulting in evaporation, ablation, plasma formation and even exfoliation
. The ejected species expand into the surrounding vacuum in the form of a plume
Pulsed laser deposition
molecules, electrons, ions, clusters, particulates and
molten globules, before depositing on the typically
hot substrate.
One possible configuration of a PLD
deposition chamber.
The detailed mechanisms of PLD are very complex including the ablation process of the
target material by the laser irradiation, the development of a plasma plume with high
energetic ions, electrons as well as neutrals and the crystalline growth of the film itself on
the heated substrate. The process of PLD can generally be divided into four stages:
Laser ablation of the target material and creation of a plasma
Dynamic of the plasma
Deposition of the ablation material on the substrate
Nucleation and growth of the film on the substrate surface
Each of these steps is crucial for the crystallinity, uniformity and stoichiometry of the
resulting film.
Laser ablation of the target material and creation of a plasma
The ablation of the target material upon laser irradiation and the creation of plasma are
very complex processes. The removal of atoms from the bulk material is done by
vaporization of the bulk at the surface region in a state of non-equilibrium and is caused by
a Coulomb explosion. In this the incident laser pulse penetrates into the surface of the
material within the penetration depth. This dimension is dependent on the laser wavelength
and the index of refraction of the target material at the applied laser wavelength and is
typically in the region of 10 nm for most materials. The strong electrical field generated by
the laser light is sufficiently strong to remove the electrons from the bulk material of the
penetrated volume. This process occurs within 10 ps of a ns laser pulse and is caused by
non-linear processes such as multiphoton ionization which are enhanced by microscopic
cracks at the surface, voids, and nodules, which increase the electric field. The free
electrons oscillate within the electromagnetic field of the laser light and can collide with
the atoms of the bulk material thus transferring some of their energy to the lattice of the
target material with in the surface region. The surface of the target is then heated up and
the material is vaporized.
Pulsed laser deposition
Dynamic of the plasma
In the second stage the material expands in a plasma parallel to the normal vector of the
target surface towards the substrate due to Coulomb repulsion and recoil from the target
surface. The spatial distribution of the plume is dependent on the background pressure
inside the PLD chamber. The density of the plume can be described by a cos^n(x) law with
a shape similar to a Gaussian curve. The dependency of the plume shape on the pressure
can be described in three stages:
• The vacuum stage, where the plume is very narrow and forward directed; almost no
scattering occurs with the background gases.
• The intermediate region where a splitting of the high energetic ions from the less
energetic species can be observed. The Time-of-Flight (TOF) data can be fitted to a shock
wave model; however, other models could also be possible.
• High pressure region where we find a more diffusion-like expansion of the ablated
material. Naturally this scattering is also dependent on the mass of the background gas
and can influence the stoichiometry of the deposited film.
The most important consequence of increasing the background pressure is the slowing
down of the high energetic species in the expanding plasma plume. It has been shown that
particles with kinetic energies around 50 eV can resputter the film already deposited on the
substrate. This results in a lower deposition rate and can furthermore result in a change in
the stoichiometry of the film.
Deposition of the ablation material on the substrate
The third stage is important to determine the quality of the deposited films. The high
energetic species ablated from the target are bombarding the substrate surface and may
cause damage to the surface by sputtering off atoms from the surface but also by causing
defect formation in the deposited film. The sputtered species from the substrate and the
particles emitted from the target form a collision region, which serves as a source for
condensation of particles. When the condensation rate is high enough, a thermal
equilibrium can be reached and the film grows on the substrate surface at the expense of
the direct flow of ablation particles and the thermal equilibrium obtained.
Nucleation and growth of the film on the substrate surface
The nucleation process and growth kinetics of the film depend on several growth
parameters including:
• Laser Parameters - several factors such as the laser fluence [Joule/cm2], laser energy,
and ionization degree of the ablated material will affect the film quality, the
stoichiometry[2] , and the deposition flux. Generally, the nucleation density increases
when the deposition flux is increased.
• Surface Temperature - The surface temperature has a large affect on the nucleation
density. Generally, the nucleation density decreases as the temperature is increased[3] .
• Substrate Surface - The nucleation and growth can be affected by the surface
preparation (such as chemical etching[4] ), the miscut of the substrate, as well as the
roughness of the substrate.
• Background Pressure - Common in oxide deposition, an oxygen background is needed to
ensure stoichiometric transfer from the target to the film. If, for example, the oxygen
background is too low, the film will grow off stoichiometry which will affect the
Pulsed laser deposition
nucleation density and film quality[5] .
In PLD a large supersaturation occurs on the substrate during the pulse duration. The pulse
lasts around 10-40 microseconds[6] depending on the laser parameters. This high
supersaturation causes an very large nucleation density on the surface as compared to
Molecular Beam Epitaxy or Sputtering Deposition. This nucleation density increases the
smoothness of the deposited film.
In PLD, [depending on the deposition parameters above] three growth modes are possible:
• Step-flow Growth - All substrates have a miscut associated with the crystal. These
miscuts give rise to atomic steps on the surface. In step-flow growth, atoms land on the
surface and diffuse to a step edge before they have a chance to nucleated an surface
island. The growing surface is viewed as steps traveling across the surface. This growth
mode is obtained by deposition on a high miscut substrate, or depositing at elevated
• Layer-by-layer Growth - In this growth mode, islands nucleate on the surface until a
critical island density is reached. As more material is added, the islands continue to grow
until the islands begin to run into each other. This is know a coalescence. Once
coalescence is reached, the surface has a large density of pits. When additional material
is added to the surface the atoms diffuse into these pits to complete the layer. This
process is repeated for each subsequent layer.
• 3D growth - This mode is similar to the layer-by-layer growth, except that once an island
is formed an additional island will nucleate on top of the 1st island. Therefore the growth
does not persist in a layer by layer fashion, and the surface roughens each time material
is added.
Pulsed laser deposition is only one of many thin film deposition techniques. Other methods
include → molecular beam epitaxy (MBE), → chemical vapor deposition (CVD), → sputter
deposition (RF, Magnetron, and ion beam). The history of laser-assisted film growth started
soon after the technical realization of the first laser in 1960 by Maiman. Smith and Turner
utilized a ruby laser to deposit the first thin films in 1965, three years after Breech and
Cross studied the laser-vaporization and excitation of atoms from solid surfaces. However,
the deposited films were still inferior to those obtained by other techniques such as
chemical vapor deposition and molecular beam epitaxy. In the early 1980’s, a few research
groups (mainly in the former USSR) achieved remarkable results on manufacturing of thin
film structures utilizing laser technology. The breakthrough came in 1987 when Dijkkamp
and Venkatesan were able to laser deposit a thin film of YBa2Cu3O7, a high temperature
superconductive material, which was of more superior quality than films deposited with
alternative techniques. Since then, the technique of Pulsed Laser Deposition has been
utilized to fabricate high quality crystalline films. The deposition of ceramic oxides, nitride
films, metallic multilayers and various superlattices has been demonstrated. In the 1990’s
the development of new laser technology, such as lasers with high repetition rate and short
pulse durations, made PLD a very competitive tool for the growth of thin, well defined films
with complex stoichiometry.
Pulsed laser deposition
Technical aspects
There are many different arrangements to build a deposition chamber for PLD. The target
material which is evaporated by the laser is normally found as a rotating disc attached to a
support. However, it can also be sintered into a cylindrical rod with rotational motion and a
translational up and down movement along its axis. This special configuration allows not
only the utilization of a synchronized reactive gas pulse but also of a multicomponent target
rod with which films of different multilayers can be created.
Some factors that influence deposition thickness:
Target material
Pulse energy of laser
Distance from target to substrate
Type of gas and pressure in chamber (Oxygen, Argon, etc.)
External links
• Fundamentals of Pulsed laser deposition
Fundamentals of Pulsed laser deposition
[1] Pulsed Laser Deposition of Thin Films, edited by Douglas B. Chrisey and Graham K. Hubler, John Wiley &
Sons, 1994
[2] T. Ohnishi et al., Journal of Applied Physics 103 (2008). (http:/ / scitation. aip. org/ getabs/ servlet/
GetabsServlet?prog=normal& id=JAPIAU000103000010103703000001& idtype=cvips& gifs=yes)
[3] J. D. Ferguson et al., Mat. Res. Soc. Proc. 1034E, edited by J. F. Scott et al.(2007) (http:/ / www. mrs. org/
s_mrs/ sec_subscribe. asp?CID=11346& DID=207016& action=detail)
[4] G. Koster et al., Applied Physics Letters 73, 2920 (1998) , (http:/ / scitation. aip. org/ getabs/ servlet/
GetabsServlet?prog=normal& id=APPLAB000073000020002920000001& idtype=cvips& gifs=yes).
[5] A. Ohtomo, and H. Y. Hwang, Journal of Applied Physics 102 (2007) (http:/ / scitation. aip. org/ getabs/ servlet/
GetabsServlet?prog=normal& id=JAPIAU000102000008083704000001& idtype=cvips& gifs=yes)
[6] F.M. Granozio, Mat. Res. Soc. Proc. 967E, edited by V. Matias et al (2006) (http:/ / www. mrs. org/ s_mrs/
sec_subscribe. asp?CID=7886& DID=187056& action=detail)
[7] M. Lippmaa, Appl. Phys. Lett. 76, 2439 (2000) (http:/ / scitation. aip. org/ getabs/ servlet/
GetabsServlet?prog=normal& id=APPLAB000076000017002439000001& idtype=cvips& gifs=yes).
[8] http:/ / www. andor. com/ physics/ ?app=66
RCA clean
RCA clean
The RCA clean is a standard set of wafer cleaning steps which needs to be performed
before high temp processing steps (oxidation, diffusion, → CVD) of silicon wafers in
semiconductor manufacturing. Werner Kern developed the basic procedure in 1965 while
working for RCA, the Radio Corporation of America [1] It involves the following :
1. Removal of the organic contaminants (Organic Clean)
2. Removal of thin oxide layer (Oxide Strip)
3. Removal of ionic contamination (Ionic Clean)
The first step (called SC-1, where SC stands for Standard Clean) is performed with a 1:1:5
solution of NH4OH + H2O2 + H2O at 75 or 80 degrees (Celsius)[1] . This treatment results
in the formation of a thin silicon dioxide layer (about 10 Angstrom) on the silicon surface,
along with a certain degree of metallic contamination (notably Iron) that shall be removed
in subsequent steps.
The second step is a short immersion in a 1:50 solution of HF + H2O at 25 degrees Celsius,
in order to remove the thin oxide layer and some fraction of ionic contaminants[1] .
The third and last step (called SC-2) is performed with a 1:1:6 solution of HCl + H2O2 +
H2O at 75 or 80 degrees Celsius. This treatment effectively removes the remaining traces of
metallic (ionic) contaminants[1] .
In his book, "Handbook of Semiconductor Wafer Cleaning Technology" [2] , Werner Kern
writes that the first step in the ex situ cleaning process is ultrasonically degrease in
trichloroethylene, acetone and methanol.
RCA cleaning (also known as SC1/SC2 etching) submits silicon wafers to oxidation by
NH3:H2O2:H2O mixtures, oxide removal in diluted HF, further oxidation by HCl:H2O2:H2O
mixtures, and final etching in diluted HF.
External links
• RCA Clean, School of Electrical and Computer Engineering,Georgia Institute of
Technology [3]
See also
→ Wafer (electronics)
Silicon on Insulator
→ Chemical-Mechanical Polishing
Piranha solution
RCA clean
[1] RCA Clean, materials at Colorado School of Mines (http:/ / www. mines. edu/ fs_home/ cwolden/ chen435/
clean. htm)
[2] William Andrew Publishers, Applied Science Technology
[3] http:/ / www. ece. gatech. edu/ research/ labs/ vc/ processes/ rcaClean. html
Reliability (semiconductor)
Reliability of semiconductor devices can be summarized as follows:
1. Semiconductor devices are very sensitive to impurities and particles. Therefore, to
manufacture these devices it is necessary to manage many processes while accurately
controlling the level of impurities and particles. The finished product quality depends
upon the many layered relationship of each interacting substance in the semiconductor,
including metallization, chip material (list of semiconductor materials) and package.
2. The problems of micro-processes, and thin films and must be fully understood as they
apply to metallization and bonding → wire bonding. It is also necessary to analyze surface
phenomena from the aspect of thin films.
3. Due to the rapid advances in technology, many new devices are developed using new
materials and processes, and design calendar time is limited due to non-recurring
engineering constraints, plus time to market concerns. Consequently, it is not possible to
base new designs on the reliability of existing devices.
4. To achieve economy of scale, semiconductor products are manufactured in high volume.
Furthermore repair of finished semiconductor products is impractical. Therefore
incorporation of reliability at the design stage and reduction of variation in the
production stage have become essential.
5. Reliability of semiconductor devices may depend on assembly, use, and environmental
conditions. Stress factors effecting device reliability include gas, dust, contamination,
voltage, current density, temperature, humidity, mechanical stress, vibration, shock,
radiation, pressure, and intensity of magnetic and electrical fields.
Design factors affecting semiconductor reliability include: voltage derating, power derating,
current derating, metastability, logic timing margins (logic simulation), timing analysis,
temperature derating, and process control.
Methods of improvement
Reliability of semiconductors is kept high through several methods. Cleanrooms control
impurities, process control controls processing, and burn-in(short term operation at
extremes) and probe and test reduce escapes. Probe (→ wafer prober) tests the
semiconductor die, prior to packaging, via micro-probes connected to test equipment. →
Wafer testing tests the packaged device, often pre, and post burn-in for a set of parameters
that assure operation.
Reliability (semiconductor)
Failure mechanisms
Failure mechanisms of electronic semiconductor devices fall in the following categories
Material-interaction-induced mechanisms.
Stress-induced mechanisms.
Mechanically induced failure mechanisms.
Environmentally induced failure mechanisms.
Material-interaction-induced mechanisms
Field-effect transistor gate-metal sinking
→ Ohmic contact degradation
Channel degradation
Surface-state effects
5. Package molding contamination—impurities in packaging compounds cause electrical
Stress-induced failure mechanisms
1. Electromigration – electrically induced movement of the materials in the chip
2. Burnout – localized overstress
3. Hot Electron Trapping – due to overdrive in power RF circuits
4. Electrical Stress – Electrostatic discharge, High Electro-Magnetic Fields(HIRF),
Latch-up overvoltage, overcurrent
Mechanically induced failure mechanisms
1. Die fracture – due to mis-match of thermal expansion co-efficients
2. Die-attach voids – manufacturing defect—screenable ultra-sonically
Environmentally induced failure mechanisms
1. Humidity effects – moisture absorption by the package and circuit
2. Hydrogen effects – Hydrogen induced breakdown of portions of the circuit (Metal)
See also
• Failure analysis
• → Cleanroom
• Burn-in
Reliability (semiconductor)
http:/ / documentation. renesas. com/ eng/ products/ others/ rej27l0001_reliabilityhb. pdf
http:/ / parts. jpl. nasa. gov/ mmic/ 4. PDF
http:/ / www. enre. umd. edu/ publications/ rs& h. htm
https:/ / www. eurelnet. org/
• Giulio Di Giacomo (Dec 1, 1996), Reliability of Electronic Packages and Semiconductor
Devices, McGraw-Hill
• A. Christou and B.A. Unger (Dec 31, 1989), Semiconductor Device Reliability, NATO
Science Series E
• Michael Pecht, Riko Radojcic, and Gopal Rao (Dec 29, 1998), Guidebook for Managing
Silicon Chip Reliability (Electronic Packaging Series), CRC Press LLC
• MIL-HDBK-217F Reliability Prediction of Electronic Equipment
• MIL-HDBK-251 Reliability/Design Thermal Applications
• MIL-HDBK-H 108 Sampling Procedures and Tables for Life and Reliability Testing (Based
on Exponential Distribution)
• MIL-HDBK-338 Electronic Reliability Design Handbook
• MIL-HDBK-344 Environmental Stress Screening of Electronic Equipment
• MIL-STD-690C Failure Rate Sampling Plans and Procedures
• MIL-STD-721C Definition of Terms for Reliability and Maintainability
• MIL-STD-756B Reliability Modeling and Prediction
• MIL-HDBK-781 Reliability Test Methods, Plans and Environments for Engineering
Development, Qualification and Production
• MIL-STD-1543B Reliability Program Requirements for Space and Missile Systems
• MIL-STD-1629A Procedures for Performing a Failure Mode, Effects, and Criticality
• MIL-STD-1686B Electrostatic Discharge Control Program for Protection of Electrical and
Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive
• MIL-STD-2074 Failure Classification for Reliability Testing
• MIL-STD-2164 Environment Stress Screening Process for Electronic Equipment
In semiconductor fabrication, "resist" refers to both:
1. A thin layer used to transfer a circuit pattern to the semiconductor substrate which it is
deposited upon. A resist can be patterned via → lithography to form a
(sub)micrometer-scale, temporary mask that protects selected areas of the underlying
substrate during subsequent processing steps.
2. The material used to prepare said thin layer (typically a viscous solution). Resists are
generally proprietary mixtures of a polymer or its precursor and other small molecules
(e.g. photoacid generators) that have been specially formulated for a given lithography
technology. Resists used during → photolithography are called photoresists.
Semiconductor devices (as of 2005) are built by depositing and patterning many thin layers.
The patterning steps, or lithography, define the function of the device and the density of its
For example, in the interconnect layers of a modern microprocessor, a conductive material
(copper or aluminum) is inlaid in an electrically insulating matrix (typically fluorinated
silicon dioxide or another low-k dielectric). The metal patterns define multiple electrical
circuits that are used to connect the microchip's transistors to one another and ultimately
to external devices via the chip's pins.
The most common patterning method used by the semiconductor device industry is →
photolithography -- patterning using light. In this process, the substrate of interest is
coated with photosensitive resist and irradiated with short-wavelength light projected
through a photomask, which is a specially prepared stencil formed of opaque and
transparent regions - usually a quartz substrate with a patterned chromium layer. The
shadow of opaque regions in the photomask forms a submicrometer-scale pattern of dark
and illuminated regions in the resist layer -- the areal image. Chemical and physical
changes occur in the exposed areas of the resist layer. For example, chemical bonds may be
formed or destroyed, inducing a change in solubility. This latent image is then developed
for example by rinsing with an appropriate solvent. Selected regions of the resist remain,
which after a post-exposure bake step form a stable polymeric pattern on the substrate.
This pattern can be used as a stencil in the next process step. For example, areas of the
underlying substrate that are not protected by the resist pattern may be etched or doped.
Material may be selectively deposited on the substrate. After processing, the remaining
resist may be stripped. Sometimes (esp. during MEMS fabrication), the patterned resist
layer may be incorporated in the final product. Many photolithography and processing
cycles may be performed to create complex devices.
Resists may also be formulated to be sensitive to charged particles, such as the electron
beams produced in scanning electron microscopes. This is the basis of electron-beam
direct-write lithography.
A resist is not always necessary. Several materials may be deposited or patterned directly
using techniques like soft lithography, Dip-Pen Nanolithography, evaporation through a
shadow mask or stencil...
Typical process
1. Resist Deposition: The precursor solution is → spin-coated on a clean (semiconductor)
substrate, such as a silicon wafer, to form a very thin, uniform layer.
2. Soft Bake: The layer is baked at a low temperature to evaporate residual solvent.
3. Exposure: A latent image is formed in the resist e.g. (a) via exposure to ultraviolet light
through a photomask with opaque and transparent regions or (b) by direct writing using
a laser beam or electron beam.
4. Development: Areas of the resist that have (or have not) been exposed are removed by
rinsing with an appropriate solvent.
5. Post-Exposure Bake
6. Processing through the resist pattern: wet or dry etching, lift-off, doping...
7. Resist Stripping
See also
• → Photolithography
• Electron beam lithography
• Nanolithography
• Lift-off Resist (LOR)
• Bottom Anti-Reflection Coating (BARC)
External links
• MicroChem [1]
• Shipley (now Rohm and Haas Electronic Materials)
• Clariant [3]
[1] http:/ / microchem. com/
[2] http:/ / electronicmaterials. rohmhaas. com/
[3] http:/ / clariant. com
Rigid needle adapter
Rigid needle adapter
The concept of the Rigid
possible a contacting of finest
structures on printed and
assembled circuit carriers and
also direct contacting in
fine-pole connectors. For this
concept one need every time a
raster head and a rigid needle
adapter. The spring probes are
arranged in a compact grid in
the raster head so that up to
280 spring probes/ cm² can be
integrated. The rigid needles
Function mode of a Rigid Needle Adapter.
are moved to the desired
contact point by the spring
probes in the rigid needle adapter. Contacting pitch down to 150 µm can be tested by the
movement of the rigid needles.
The contacting stroke is effected in the needle adapter. Contacting forces of 0.4 N to 1.5 N
depending on the spring probe are exerted on the contacting point by the spring excursion
of approx. 2.5 mm.
Life cycle of rigid needle adapters
The contacting tip of the rigid needle becomes blunt in time through contacting. The
service life thus depends mainly on the material to be contacted. Under optimum conditions
up to 500,000 contactings and more can be achieved with the rigid needles. Spring pins
manufactured specifically for this application and the compact design mean that service
lives of far more than 1 million contact cycles are possible in practice.
Rigid needle adapter
Combination of spring probes and rigid needles
The rigid needle adapter is
manufactured to customer
requirements. Rigid needle
structures are called also MCA
(Micro Contacting Adapter).
The feasibility matrix shows
which spring pins can be
combined with which rigid
needles. The concept allows
not only the contacting of
assembled and bare PCBs but
also the direct contacting of
high-pole micro-connectors.
Possible constant current
(IC) and pulsed current (IP)
at 10ms:
Combination of spring probes and rigid needles.
• A: IC=0.3A / IP=0.9A
B: IC=0.6A / IP=1.8A
C: IC=1.0A / IP=3.0A
D: IC=2.0A / IP=6.0A
E: IC=3.0A / IP=9.0A
External links
Manufacturer of rigid needle adapter (fine-pitch): Microcontact AG
Manufacturer of rigid needle adapter: ATX
Manufacturer of spring probes: Ingun
Manufacturer of spring probes: Feinmetall
http:/ / www. microcontact. ch/
http:/ / www. atx-hardware. de/ schraegnadel-adapter/ schraegnadel-ada-text. htm/
http:/ / www. ingun. de/
http:/ / www. feinmetall. de/
The SECS/GEM interface is the semiconductor industry's standard for equipment-to-host
communications. In an automated fab, the interface can start and stop equipment
processing, collect measurement data, change variables and select recipes for products.
The SECS (SEMI Equipment Communications Standard)/GEM (Generic Equipment Model)
standards do all this in a defined way.
Developed by the SEMI (Semiconductor Equipment and Materials International)
organization[1] , the standards define a common set of equipment behaviour and
communications capabilities.
The Generic Model for Communications and Control Of Manufacturing Equipment (GEM)
standard is maintained and published by the non-profit organization Semiconductor
Equipment and Materials International (SEMI). Generally speaking, the SECS/GEM
standard defines messages, state machines and scenarios to enable factory software to
control and monitor manufacturing equipment. The GEM standard is formally designated
and referred to as SEMI standard E30, but frequently simply referred to as the GEM or
SECS/GEM standard. GEM intends "to produce economic benefits for both device
manufacturers and equipment suppliers..." by defining "... a common set of equipment
behavior and communications capabilities that provide the functionality and flexibility to
support the manufacturing automation programs of semiconductor device manufacturers"
[SEMI E30, 1.3]. GEM is a standard implementation of the SECS-II standard, SEMI
standard E5. Many equipment in semiconductor (front end and back end), surface mount
technology, electronics assembly, photovoltaic, flat panel display and other manufacturing
industries worldwide provide a GEM/SECS interface on the manufacturing equipment so
that the factory host software can communicate with the machine for monitoring and/or
controlling purposes. Because the GEM standard was written with very few
semiconductor-specific features, it can be applied to virtually any manufacturing equipment
in any industry.
All GEM compliant manufacturing equipment share a consistent interface and certain
consistent behavior. GEM equipment can communicate with a GEM capable host using
either TCP/IP (using the HSMS standard, SEMI E37) or RS-232 based protocol (using the
SECS-I standard, SEMI E4). Often both protocols are supported. Each equipment can be
monitored and controlled using a common set of SECS-II messages specified by GEM. When
an equipment has a GEM interface, it takes just minutes (or even seconds) for factory GEM
host software to establish communication and begin monitoring the machine's activity. This
means that equipment manufacturers can spend more time and money improving the
machine's quality by providing a common interface to all factories. It means that factories
can spend more time and money improving production and processes, rather than setting
up communication to the machines.
There are many additional SEMI standards and factory specifications that reference the
GEM standard its features. These additional standards are either industry-specific or
equipment-type specific. Following are a few examples.
• Semiconductor Front-End
• The semiconductor front-end industry defined a series of standards known as the
GEM300 standards that includes SEMI standards E40, E87, E90, E94 and E116 and
reference the E39 standard. Each standard provides additional features to the GEM
interface yet build upon the features in GEM E30 standard. 300 mm factories worldwide
use the underlying GEM standard's data collection features in order to monitor specific
equipment activity such as wafer movement and process job execution. The SECS/GEM
standard and the additional GEM 300 standards are required on nearly each and every
300mm wafer manufacturing tool in order to implement the manufacturing automation.
This industry has been the strongest supporter of the GEM and related SEMI standards.
• Semiconductor Back-End
• Numerous equipment in the Semiconductor Back-End industry implement the GEM
standard. Additional standards have been implemented such as SEMI E122 STANDARD
• Surface Mount Technology
• Many equipment in the Surface Mount Technology industry support the GEM standard,
including chip placement, solder paste, oven and inspection equipment. The GEM
standard has been used on these equipment for over 15 years.
• Photovoltaic
• In 2008, the Photovoltaic industry officially decided to adopt the SECS/GEM standard
and submitted a proposal for a new SEMI standard, ballot 4557, as a new PV industry
standard. Even prior to adopting the GEM standard, several photovoltaic equipment
suppliers already were capable of supporting the GEM standard. The new standard is
defines a framework that utilizes the SEMI E37 (HSMS), SEMI E5 (SECS-II), SEMI 30
(GEM), SEMI E148 and SEMI E10 standards.
External links
• SEMI - Semiconductor Equipment and Materials International
• More info on SECS/GEM standard [2]
[1] SEMI - Semiconductor Equipment and Materials International
[2] http:/ / www. cimetrix. com/ gemintro. cfm
Semiconductor Equipment and Materials International
Semiconductor Equipment and
Materials International
Semiconductor Equipment and Materials International (SEMI) is a trade organization
of manufacturers of equipment and materials used in the fabrication of semiconductor
devices such as integrated circuits, transistors, diodes, and thyristors. Among other
activities, SEMI acts as a clearinghouse for the generation of standards specific to the
industry and the generation of long-range plans for the industry.
See also Fabrication (semiconductor).
Official association boilerplate
SEMI is a global industry association serving companies that provide equipment, materials
and services used to manufacture semiconductors, displays, nano-scaled structures,
micro-electromechanical systems (MEMS) and related technologies. SEMI maintains offices
in Austin, Beijing, Brussels, Hsinchu, Moscow, San Jose (Calif.), Seoul, Shanghai,
Singapore, Tokyo and Washington, D.C. For more information, visit
Official company background
By 1970 the semiconductor industry had been building momentum for at least a decade. Yet
the companies supplying the equipment and materials that made possible the miniature
wonders known as “chips” were all but invisible. The newly emerging industry was tiny
then – only a few million dollars in global revenues – but a handful of visionary leaders
came together to create a forum to shine the spotlight on equipment and materials
suppliers. The resulting organization was called Semiconductor Equipment and Materials
Institute, but was best known as SEMI.
Challenges One of the early challenges facing the budding industry was marketplace
visibility. The new SEMI organization quickly answered the challenge with the introduction
of the first SEMICON exposition. Appealing for its festive energy at the county fairgrounds
in San Mateo, California, SEMICON was hugely successful.
SEMI standards
With the proceeds generated by the show, the SEMI founders realized a unique opportunity
to re-invest in their industry, and launched the SEMI Standards program. From its earliest
successes in standardizing silicon wafers to current efforts in factory automation and
software, the SEMI International Standards program has been helping to ensure open
markets and lower semiconductor manufacturing costs for over 30 years. SEMI Standards
have also facilitated the development of new industries, including the now pervasive
foundry manufacturing model.
Semiconductor Equipment and Materials International
In the mid-1980s, semiconductor manufacturing centers began to develop around the
globe. SEMI members and their customers were becoming more multi-national. True to its
visionary beginnings, SEMI was at the forefront of supporting truly global industry
development, despite then heightened trade friction. To ensure fair and open market access
around the globe, SEMI transformed itself. The “I” in SEMI – which formerly stood for
Institute – became “I” for International, and SEMI added support offices in the relevant
areas of semiconductor manufacturing activity.
Voice of the industry
Throughout the 1990s, as the semiconductor equipment and materials industry grew in size
and importance, it took on a greater role in developing the process solutions that have
made possible the electronics-based society we now enjoy. SEMI also evolved with our
industry, developing more of the products and services that its members value in an
industry association, such as technical conferences, educational events and market data
collection and analysis. As the voice of the industry, SEMI represents the collective
interests of its membership, and is an advocate for the industry in the areas of public policy,
environment, health and safety, workforce development and investor relations.
Today, the technologies created by SEMI members are applicable to a number of related
industries, such as flat panel display and micro-electromechanical systems (MEMS).
Accordingly, SEMI continues to add innovative programs in related technology areas.
SEMI, as the only truly global representative of the semiconductor, display, MEMS and
related industries, will continue to provide the valuable services that have made it the
association of choice for the microelectronics ecosystem.
External links
• — Official site
The term salicide refers to a technology used in the microelectronics industry used to form
electrical contacts between the semiconductor device and the supporting interconnect
structure. The salicide process involves the reaction of a thin metal film with silicon in the
active regions of the device, ultimately forming a metal silicide contact through a series of
annealing and/or → etch processes. The term "salicide" is a compaction of the phrase
self-aligned silicide. The description "self-aligned" suggests that the contact formation
does not require → lithographic patterning processes, as opposed to a non-aligned
technology such as polycide. The term salicide is also used to refer to the metal silicide
formed by the contact formation process, such as "titanium salicide", although this usage is
inconsistent with accepted naming conventions in chemistry.
Contact Formation
The salicide process begins with deposition of a thin transition metal layer over fully formed
and patterned semiconductor devices (e.g. transistors). The → wafer is heated, allowing the
transition metal to react with exposed silicon in the active regions of the semiconductor
device (e.g., source, drain, gate) forming a low-resistance transition metal silicide. The
transition metal does not react with the silicon oxide and or nitride insulators present on
the wafer. Following the reaction, any remaining transition metal is removed by chemical
etching, leaving silicide contacts in only the active regions of the device. A fully integrable
manufacturing process may be more complex, involving additional anneals, surface
treatments, or etch processes.
Typical transition metals used or considered for use in salicide technology include titanium,
cobalt, nickel, platinum, and tungsten. One key challenge in developing a salicide process is
controlling the specific phase (compound) formed by the metal-silicon reaction. Cobalt, for
example, may react with silicon to form Co2Si, CoSi, CoSi2, and other compounds.
However, only CoSi2 has a sufficiently low resistance to form an effective electrical contact.
For some compounds, the desired low-resistance phase is not thermodynamically stable,
such as C49-TiSi2, which is metastable with respect to the high resistance C54 phase.
Other considerations
Another challenge facing successful process integration include lateral growth, especially
underneath the gate, which will short circuit the device.
Semiconductor industry
Semiconductor industry
The semiconductor industry is the aggregate collection of companies engaged in the
design and fabrication of semiconductor devices. It formed around 1960, once the
fabrication of semiconductors became a viable business. It has since grown to be the $249
billion dollar industry it is today.[1]
Industry structure
The global semiconductor industry is dominated by Taiwan, South Korea, USA, and Japan.
Despite experiencing a downfall in the semiconductor market, Japan is still major leader in
the industry. The U.S. industry faces challenges to development by some forms of
government regulation. The U.S. government regulates exports and certain uses of some
types of semiconductors due to their potential dual use in military applications.
Based on KPMG report it will be a $260 billion market by 2009. A few major players in this
segment are Taiwan Semiconductor Manufacturing Company, United Microelectronics
Corporation, Intel, Toshiba, NEC, Sony, IBM, Samsung, Texas Instruments, ST
Microelectronics, NXP Semiconductors, Freescale, Infineon, ISSI etc.
This industry features a number of distinct characteristics that position it uniquely in the
economy and in the global competitive arena. These include:
• Very high intensity of research and development (up to 20% of annual revenues) and the
required level of capital expenditures in semiconductor plants or fabs (up to 25% of
annual revenues).
• The role of the industry as technology enabler. The semiconductor industry is widely
recognized as a key driver for economic growth in its role as a multiple lever and
technology enabler for the whole electronics value chain. In other words, from a
worldwide base semiconductor market of $213 billion in 2004, the industry enables the
generation of some $1,200 billion in electronic systems business and $5,000 billion in
services, representing close to 10% of world GDP.
• Maximal exposure to international competition.
• Continuous growth but in a cyclical pattern with high volatility. While the current 20 year
annual average growth of the semiconductor industry is on the order of 13%, this has
been accompanied by equally above-average market volatility, which can lead to
significant if not dramatic cyclical swings.
• The need for high degrees of flexibility and innovation in order to constantly adjust to the
rapid pace of change in the market. Many products embedding semiconductor devices
often have a very short life cycle. At the same time, the rate of constant
price-performance improvement in the semiconductor industry is staggering. As a
consequence, changes in the semiconductor market not only occur extremely rapidly but
also anticipate changes in industries evolving at a slower pace. Yet another consequence
of this rapid pace is that established market strongholds can be displaced all too quickly.
Semiconductor industry
See also
• Moore's Law
• → Semiconductor device fabrication
• Electronic Design Automation
[1] Semiconductor Industry Association Factsheet (http:/ / www. sia-online. org/ cs/ industry_resources/
Shallow trench isolation
(STI), also known as 'Box
Isolation Technique', is an
adjacent semiconductor device
components. STI is generally
technology nodes of 250
nanometers and smaller. Older
commonly use isolation based
on LOCOS.[1]
STI is created early during the
Scaling of isolation with transistor size. Isolation pitch is the sum
of the transistor width and the trench isolation distance. As the
isolation pitch shrinks, the narrow channel width effect becomes more
fabrication process, before transistors are formed. The key steps of the STI process involve
etching a pattern of trenches in the silicon, depositing one or more dielectric materials
(such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a
technique such as → chemical-mechanical planarization.[2]
Certain semiconductor fabrication technologies also include deep trench isolation, a related
feature often found in analog integrated circuits.
The effect of the trench edge has given rise to what has recently been termed the "reverse
narrow channel effect"[3] or "inverse narrow width effect".[4] Basically, due to the electric
field enhancement at the edge, it is easier to form a conducting channel (by inversion) at a
lower voltage. The threshold voltage is effectively reduced for a narrower transistor
width.[5] [6] The main concern for electronic devices is the resulting subthreshold leakage
current, which is substantially larger after the threshold voltage reduction.
Shallow trench isolation
Process flow
Stack deposition (oxide + protective nitride)
Lithography print
Dry etch
Trench fill with oxide
Chemical-mechanical polishing of the oxide
Removal of the protective nitride
Adjusting the oxide height to Si
External links
• Clarycon: Shallow trench isolation [7]
• N and K Technologies: Shallow trench isolation [8]
• Dow Corning: Spin on Dielectrics - Spin-on Shallow Trench Isolation
[1] Quirk, Michael & Julian Serda (2001). Semiconductor Manufacturing Technology: Instructor's Manual (http:/ /
smtbook. com/ instructor_guide. pdf), p. 25.
http:/ / smtbook. com/ features. htm
J-W. Jung et al., Jpn. J. Appl. Phys., 39, 2136-2140 (2000).
A. Chatterjee et al., IEDM 1996.
J. Pretet et al., Solid-State Electronics, 46, 1699-1707 (2002).
Y-H. Lee et al., Microelectronics Reliability, 41, 689-696 (2001).
http:/ / www. clarycon. com/ shallowtrenchisa. html
http:/ / sst. pennnet. com/ display_article/ 167270/ 5/ ARTCL/ none/ none/ 1/
[9] http:/ / www. dowcorning. com/ content/ etronics/ etronicsspin/ etronics_spin_stiov. asp
Silicate glass
Silicate glass
Silicate glasses are amorphous and have no crystalline structure. [1] Silicate glass is
useful for conducting x-ray crystallography because the x-rays will pass through the silicate
pipette holding the sample under examination without being reflected by crystals in the
glass itself; thus the resulting measurement is assured to be from the sample. Silicate
glasses have also been commonly used in the field of semiconductor device fabrication as
an insulator between active layers of the semiconductor device. Also, some airbags in cars
react SiO2 with harmful byproducts of nitrogen gas producing reactions to produce Silicate
glass to remove the harmful substances (K2O and Na2O) .
These materials have relatively low melting temperatures, and can be flowed by heating in
order to "planarize" the semiconductor layers. There will typically be contact holes or vias
etched into the glass layers using wet etching or → dry etching, and the silicate glasses can
then be reflowed by heating in order to make smoother tops to the contact holes or vias,
which makes the metal connections into the contact holes or vias more durable.
The silicate glasses are typically formed of → phosphosilicate glass (PSG) or →
borophosphosilicate glass (BPSG). The boron and/or phosphorus impurity levels used can
be adjusted to affect the silicate glass's melting point.
[1] MIT MIT Open Courseware; Introduction to Solid State Chemistry, Course 3.091 Lecture 18, 2004, timepoint
25 min0sec (http:/ / www. youtube. com/ watch?v=WF9ftfGEGYw& feature=SeriesPlayList&
Silicon on sapphire
Silicon on sapphire
Silicon on sapphire (SOS) is a hetero-epitaxial process for integrated circuit
manufacturing that consists of a thin layer (typically thinner than 0.6 micrometres) of
silicon grown on a sapphire (Al2O3) wafer. SOS is part of the Silicon on Insulator (SOI)
family of CMOS technologies. SOS is primarily used in aerospace and military applications
because of its inherent resistance to radiation. Typically, high-purity artificially grown
sapphire crystals are used. The silicon is usually deposited by the decomposition of silane
gas (SiH4) on heated sapphire substrates. The advantage of sapphire is that it is an
excellent electrical insulator, preventing stray currents caused by radiation from spreading
to nearby circuit elements. SOS has seen little commercial use to date because of
difficulties in fabricating the very small transistors used in modern high-density
applications. This drawback is because the SOS process results in the formation of
dislocations, twinning and stacking faults from crystal lattice disparities between the
sapphire and silicon. Additionally, there is some aluminium, a p-type dopant, contamination
from the substrate in the silicon closest to the interface.
Silicon on Sapphire Circuits and Systems
research groups as Yale e-Lab to fabricate a variety of
SOS circuits and system that benefit from the
technology and advance the state-of-the-art in:
• analog-to-digital converters (a nano-Watts prototype
was produced by Yale e-Lab)[2][3]
• monolithic digital isolation buffers [4]
• SOS-CMOS image sensor arrays (one of the first
standard CMOS image sensor arrays capable of
transducing light simultaneously from both sides of
the die was produced by Yale e-Lab)[5]
• patch-clamp amplifiers [6]
• energy harvesting devices [7]
A Silicon on Sapphire microchip
designed by e-Lab [1]
• three-dimensional (3D) integration with no galvanic connections
• charge pumps [8]
• temperature sensors [7]
Silicon on sapphire pressure and temperature sensors have been manufactured by
Sensotron and Sensonetics utilizing a patented process by Armen Sahagen
Silicon on sapphire
Substrate Analysis - SOS Structure
An example of an SOS product manufacturer is San
Semiconductor. The application of epitaxial growth of
silicon on sapphire substrates for fabricating MOS
devices involves a silicon purification process that
mitigates crystal defects which result from a mismatch
between sapphire and silicon lattices. The Peregrine
PE42612 SP4T switch is formed on an SOS substrate
where the final thickness of silicon is approximately
95nm. Silicon is recessed in regions outside the
polysilicon gate stack by poly oxidation and further
recessed by the sidewall spacer formation process to a
thickness of approximately 78nm.
See also
Silicon on Insulator
Radiation hardening
Semiconductor Insights
http:/ / www. eng. yale. edu/ elab/
http:/ / pantheon. yale. edu/ ~ec337/ pubs/ ADCTCASII2006. pdf
http:/ / pantheon. yale. edu/ ~ec337/ pubs/ 2c1cisosadc. pdf
http:/ / pantheon. yale. edu/ ~ec337/ pubs/ isoAICSP2006. pdf
http:/ / pantheon. yale. edu/ ~ec337/ pubs/ eletsSOSImgrRev1. pdf
http:/ / pantheon. yale. edu/ ~ec337/ pubs/ iscas06%20patchi06. pdf
[7] http:/ / pantheon. yale. edu/ ~ec337/ pubs/ harvestEL2006. pdf
[8] http:/ / pantheon. yale. edu/ ~ec337/ pubs/ el2005_isolationcp. pdf
TEM Cross-Section of epitaxially
grown silicon and sapphire substrate
taken by Semiconductor Insights
Smart Cut
Smart Cut
Smart Cut is a technological process that enables the
transfer of very fine layers of crystalline material onto a
mechanical support. The application of this technological
procedure is used mainly in silicon-on-insulator (SOI). The
role of SOI is to electronically insulate a fine layer of
monocrystalline silicon from the rest of the silicon wafer;
an ultra-thin silicon film is transferred to a mechanical
support, thereby introducing an intermediate, insulating
layer. Semiconductor manufacturers can then fabricate
integrated circuits on the top layer of the SOI wafers using
the same processes they would use on plain silicon wafers.
The wafers are then cut up and the chips packaged for
mounting on the cards that are integrated into electronic
systems such as personal computers. The Smart Cut
process was developed and is patented by SOITEC
corporation from France.
See also
• silicon-on-insulator
• Soitec
Smart Cut process
Spin coating
Spin coating
Spin coating is a procedure used to apply uniform thin
films to flat substrates. In short, an excess amount of a
solution is placed on the substrate, which is then
rotated at high speed in order to spread the fluid by
centrifugal force. A machine used for spin coating is
called a spin coater, or simply spinner.
Rotation is continued while the fluid spins off the edges
of the substrate, until the desired thickness of the film
is achieved. The applied solvent is usually volatile, and
simultaneously evaporates. So, the higher the angular
speed of spinning, the thinner the film. The thickness of
the film also depends on the concentration of the
solution and the solvent.
Spin coating is widely used in → microfabrication,
where it can be used to create thin films with
thicknesses below 10 nm. It is used intensively in →
photolithography, to deposit layers of photoresist about
1 micrometre thick. Photoresist is typically spun at 20
to 80 Hz for 30 to 60 seconds.
A spin coater (Laurell Technologies
model shown) used to apply
photoresist to the surface of a silicon
Stages of spin coating
Although different engineers count things
differently, there are four distinct stages to
the spin coating process.
• Deposition of the coating fluid onto the
wafer or substrate
This can be done by using a nozzle and
pouring the coating solution or by spraying
it onto the surface. A substantial excess of
compared to the amount that is required.
• Acceleration of the substrate up to its
final, desired, rotation speed
• Spinning of the substrate at a constant
rate; fluid viscous forces dominate the
fluid thinning behavior
EVG 120 fully automated photoresist coater-developer
under inactinic light at LAAS technological facility in
Toulouse, France.
• Spinning of the substrate at a constant rate; solvent evaporation dominates the coating
thinning behavior
Spin coating
Tutorial & experimental technique
Although many polymers with a wide range of weights may be spin-coated, one of the
easiest and most typical polymers to spin-coat is poly(methyl methacrylate), commonly
known as PMMA, with a moderate molecular weight (e.g. ~120,000), dissolved in a solvent
with some moderate polarity. The solvent 1,2,3-trichloropropane was once a traditional
solvent commonly used in spin-coating, but due to toxicity issues cyclohexanone is
generally preferred and produces coatings of comparable quality. More polar solvents such
as N,N-dimethylformamide (DMF) are also commonly used. Typically between 10 and 30%
(w/w) polymer is dissolved in the solvent. Both the choice of solvent and especially the
molecular weight of the polymer significantly affect the viscosity of the solution and thus
the thickness of the resultant coating.
For many applications the solution is doped with an active dye or compound. In nonlinear
optics, typical doping compounds include Disperse Red and DANS with concentrations up
to 30% w/w (dye/polymer). The active doping compound is typically referred to as the
"guest," while the inert polymer is known as the "host."
Many substrates may be coated, but in many research applications one-inch square glass
plates (for many applications often coated with a transparent electrode made of indium tin
oxide or ITO) cut from microscope slides are commonly coated for experimental purposes.
Prior to spin-coating, the polymer-solvent solution must be filtered to remove dust, typically
with a 0.45 micrometre filter. Although it is preferable to spin-coat in a clean-room
environment (Class 10 or 100), for many simple laboratory experiments, spin-coating may
be performed in a clean fume-hood. The glass plate is placed upon the spin-coating
apparatus, cleaned successively with acetone and then methanol using lint-free swabs, and
followed up with isopropanol, then coated liberally with the polymer-solvent solution by use
of syringe or eye-dropper. The plate is spun in at least two stages which may be
programmed into most any simple spin-coating apparatus. During the first stage, the plate
is spun at a low to moderate speed 500-1000 rpm for 5-10 seconds to evenly spread the
solution. The thickness of the coating is then determined and controlled during the second
stage by spinning the coating at a higher speed, between 1500-3000 rpm for anywhere
between a few seconds and a minute. These conditions will typically produce high quality
coatings of thickness between 2 and 10 micrometres.
Once spin-coating is complete, the plate is typically placed quickly onto a hot plate (heated
to somewhere around 100 ºC) for several seconds or minutes to initially evaporate solvent
and solidify the coating. The slide is than baked-out for several hours, or typically over
night, in an oven or vacuum oven, at a temperature high enough to sufficiently remove the
remaining solvent. Although it is not uncommon to place plates in a petri dish during one or
both bake-out steps to protect films from dust, condensation of solvent on the roof of the
dish may greatly affect the film smoothness and quality and thus the lid of the dish must be
set ajar to allow for the evaporating solvent to escape.
Many other polymers, such as polystyrene or more polar polymers such as polysulfones or
polyetherimides, may also be spin-coated. More polar polymers are typically dissolved in
N,N-dimethylformamide (DMF). Some polymers are more difficult to coat than others. Most
often poor quality, hazy, or "orange peel" coatings are the result of moisture absorption due
to environmental humidity. Although strict control over the laboratory environment is the
best way to improve coating quality, when this is difficult or infeasible one quick-fix to
significantly improve film quality is to gently spray a dry inert gas (such as nitrogen, or
Spin coating
preferably argon) over the sample during coating while heating the sample with an infrared
heat lamp (available at most any hardware store). The heat-lamp significantly reduces the
local humidity while simultaneously speeding the rate of solvent evaporation so that the
sample does not have a chance to absorb moisture.
• S. Middleman and A.K. Hochberg Process Engineering Analysis in Semiconductor Device
Fabrication, McGraw-Hill, p. 313 (1993)
• Dirk W. Schubert, Thomas Dunkel; Spin coating from a molecular point of view: its
concentration regimes, influence of molar mass and distribution; Materials Research
Innovations Vol. 7, p. 314 (2003)
External links
• http:/ / www. brewerscience. com/ research/ processing-theory/ spin-coater-theory/
• Norrman, K.; Ghanbari-Siahkali, A.; Larsen, N.B. (2005). "Studies of spin-coated polymer
films". Annual Reports Section "C" (Physical Chemistry) 101: 174–201.
doi:10.1039/b408857n [1].
[1] http:/ / dx. doi. org/ 10. 1039%2Fb408857n
Spreading Resistance Profiling
Spreading Resistance Profiling (SRP), also known as Spreading Resistance Analysis
(SRA), is a technique used to analyze resistivity vs. depth in silicon and germanium
semiconductors. Semiconductor devices depend on the distribution of carriers (electrons or
holes) within their structures to provide the desired performance. The carrier concentration
(which can vary by up to ten orders of magnitude) can be inferred from the resistivity
profile provided by SRP.
The fundamental relationship is usually attributed to James Clerk Maxwell (1831–1879). In
1962, Dickey[1] developed a practical 2-probe system using a pair of weighted osmium
In 1970, Solid State Measurements was founded to manufacture spreading resistance
profiling tools and in 1974, Solecon Labs was founded to provide spreading resistance
profiling services. In 1980, Dickey developed a practical method of determining p- or n-type
using the spreading resistance tool. Improvements have continued but have been
challenged by the ever shrinking dimensions of state-of-the-art digital devices. For shallow
structures (<1um deep), the data reduction is complex. Some of the contributors to the
data reduction are Dickey[2] ,[3] , Schumann and Gardner[4] , Choo et al. [5] , Berkowitz and
Lux[6] , Evans and Donovan[7] , Peissens et al. [8] , Hu[9] , Albers[10] , and Casel and Jorke [11]
Spreading Resistance Profiling
Theory of operation
If a voltage is applied between two probe tips providing electrical contact to an infinite
slab, the resistance encountered within the slab is
, where:
is the measured resistance in ohms,
(rho) is the resistivity of the slab in ohm-cm, and
is the radius of the contact area in cm.
Most of the resistance occurs very close to the electrical contact[12] allowing the local
resistivity to be determined. The probes produce a negligible probe to silicon resistance
(nearly → ohmic contact) over the entire resistivity range for both p-type and n-type (rich in
holes and rich in electrons respectively). Keeping the resistance of wiring and the
spreading resistance within the probe tips to a minimum, the measured resistance is almost
exclusively from
for silicon samples at least
resistivity standards,
thick. With the aid of calibration
can be determined at each probing by the probe pair.
Five millivolts is applied across the probe tips. The measured resistance can range from
1-ohm to one billion ohms. A “log R” amplifier or electrometer is used to measure the
tungsten carbide probe tips
placed about 20um apart.
Each tip is mounted on a
kinematic bearing to minimize
“scrubbing”. The probes are
lowered very gently onto a
beveled piece of silicon or
loading of the probe tips may
be as little as 2 g., the
pressure is in excess of one
million pounds per sq inch (or
~ 10G pascals) causing a
localized phase transformation
in the silicon to “beta-tin”
Figure 1 Illustration of the probing of a beveled piece of silicon.
producing a nearly → ohmic
(Typically, 60 to 100 or more measurements are made.)
. Between each
measurement, the probes are raised and indexed a pre-determined distance down the
bevel. Bevels are produced by mounting the sample on an angle block and grinding the
bevel with typically a 0.1- or 0.05-micrometre diamond paste. Bevel angles, chosen to fit the
depth of interest, can range from ~ 0.001 to 0.2 radians. Care must be used to produce a
smooth, flat bevel with minimum rounding of the bevel edge. (See Figure 1.)
Spreading Resistance Profiling
Detection limits
The instrument range is typically from one ohm to one billion ohms. This is adequate for the
entire resistivity range in single-crystal silicon.
Calibration standards
about 0.0006 ohm-cm
both (100) and (111)
perhaps above 40,000
have been produced by NIST. A set of 16 standards ranging from
to 200 ohm-cm have been produced for both n- and p-type and for
crystal orientations. For high resistivity (above 200 ohm-cm and
ohm-cm) the resistivity value must extrapolated from the calibration
The tool is used primarily for determining doping structures in silicon semiconductors.
Deep and shallow profiles are shown in Figure 2.
Figure 2 The shallow profile on the left, the deep profile on the right. Carrier concentration is plotted against depth.
Regions with a net electron concentration are denoted as “n” (or n-type). Regions with a net hole concentration are
denoted as “p”.
Alternative processes
Secondary ion mass spectrometry (SIMS) is also very useful for dopant profiling. SIMS can
provide the atomic concentration over 3 decades or in some cases, 4 decades of dynamic
range. SRP can determine the carrier concentration (electrically active dopant) in more
than 8 or 9 decades of dynamic range. Often, the techniques are complimentary although
sometimes competitive. The equipment for SIMS tends to be considerably more expensive
to manufacture and operate. While spreading resistance is limited to silicon, germanium
and a few other semiconductors, SIMS can profile the atomic concentration of almost
anything in anything. SIMS has greater spatial resolution useful for ultra-shallow profiles
Spreading Resistance Profiling
(< 0.1-micrometre) but SRP is more convenient for deeper structures.
R. G. Mazur and D. H. Dickey, A Spreading Resistance Technique for Resistivity
Measurements on Silicon , J. Electrochem. Soc., 113, 255 (1966)
D. H. Dickey, History and Status of the Data Reduction Problem in SRA, Proceedings of the
Third International Conference on Solid State and Integrated Circuit Technology, Ellwanger
et al., Eds., Publishing House of Electronics Industry
External links
Solid State Measurements [14]
Solecon Labs [15]
Tutorial on SRA process [16]
Additional technical notes [17]
[1] D. H. Dickey, The Electrochem. Soc., Electron. Div Ext. Abstr. 12, 151 (1963)
[2] D. H. Dickey and J. R. Ehrstein, NBS Special Publication 400-48, (1979)
[3] D. H. Dickey, ASTM Subcommittee F1.06 Meeting, Denver, June 1984
[4] P. A. Schumann and E. E. Gardner, J. Electrochem. Soc. 116, 87 (1969)
[5] S. C. Choo, M. S. Leong, and K.L. Hong, L. Li and L. S. Tan, Solid State Electronics, 21, 796 (1978)
[6] H. L. Berkowitz and R. A. Lux, J. Electrochem Soc. 128, 1137 (1981)
[7] R. A. Evans and R. P. Donovan, Solid St. Electron. 10, 155 (1967)
[8] R. Peissens, W. B. Vandervorst, and H. E. Maes, J. Electrochemical Soc. 130, 468 (1983).
[9] S. M. Hu, J. Appl. Phys. 53, 1499 (1982)
[10] J. H. Albers, Emerging Semiconductor Technology, ASTM ATP 960, D. C. Gupta and P. H. Langer, Eds., Am.
Soc. for Testing and Materials (1986).
[11] A. Casel and H. Jorke, Appl. Phys. Lett., 50, 989 (1987)
[12] R. Holm, Electric Contacts, Almquist and Wiksels, Upsalla (1946)
[13] J. C. Jamieson, Crystal Structures at High Pressures of Metallic Modification of Silicon and Germanium,
Science, 139 (1963)
http:/ / www. ssm-inc. com
http:/ / www. solecon. com
http:/ / www. solecon. com/ pdf/ determination_of_diffusion_characteristics_using_2_and_4pp. pdf
http:/ / www. solecon. com/ sra. htm
Sputter deposition
Sputter deposition
Sputter deposition is a → physical vapor deposition (PVD) method of depositing thin films
by sputtering, that is ejecting, material from a "target," that is source, which then deposits
onto a "substrate," such as a silicon wafer. Resputtering is re-emission of the deposited
material during the deposition process by ion or atom bombardment.
Sputtered atoms ejected from the
target have a wide energy
distribution, typically up to tens of
eV (100,000 K). The sputtered ions
(typically only about 1% of the
ejected particles is ionized) can
ballistically fly from the target in
energetically on the substrates or
pressures, they collide with the
gas atoms that act as a moderator and move diffusively, reaching the substrates or vacuum
chamber wall and condensing after undergoing a random walk. The entire range from
high-energy ballistic impact to low-energy thermalized motion is accessible by changing the
background gas pressure. The sputtering gas is often an inert gas such as argon. For
efficient momentum transfer, the atomic weight of the sputtering gas should be close to the
atomic weight of the target, so for sputtering light elements neon is preferable, while for
heavy elements krypton or xenon are used. Reactive gases can also be used to sputter
compounds. The compound can be formed on the target surface, in-flight or on the
substrate depending on the process parameters. The availability of many parameters that
control sputter deposition make it a complex process, but also allow experts a large degree
of control over the growth and microstructure of the film.
Sputtering is used extensively in the semiconductor industry to deposit thin films of various
materials in integrated circuit processing. Thin antireflection coatings on glass for optical
applications are also deposited by sputtering. Because of the low substrate temperatures
used, sputtering is an ideal method to deposit contact metals for thin-film transistors.
Perhaps the most familiar products of sputtering are low-emissivity coatings on glass, used
in double-pane window assemblies. The coating is a multilayer containing silver and metal
oxides such as zinc oxide, tin oxide, or titanium dioxide. Sputtering is also used to metalize
plastics such as potato chip bags. A large industry has developed around tool bit coating
using sputtered nitrides, such as → titanium nitride, creating the familiar gold colored hard
coat. Sputtering is also used as the process to deposit the metal (aluminium) layer during
the fabrication of CD and DVD discs.
Hard disk surfaces use sputtered CrOx and other materials. Sputtering is one of the main
processes of manufacturing optical waveguides.
Sputter deposition
Comparison with other deposition methods
An important advantage of sputter deposition is that even the highest melting point
materials are easily sputtered while evaporation of these materials in a resistance
evaporator or Knudsen cell is problematic or impossible. Sputter deposited films have a
composition close to that of the source material. The difference is due to different elements
spreading differently because of their different mass (light elements are deflected more
easily by the gas) but this difference is constant. Sputtered films typically have a better
adhesion on the substrate than evaporated films. A target contains a large amount of
material and is maintenance free making the technique suited for ultrahigh vacuum
applications. Sputtering sources contain no hot parts (to avoid heating they are typically
water cooled) and are compatible with reactive gases such as oxygen. Sputtering can be
performed top-down while evaporation must be performed bottom-up. Advanced processes
such as epitaxial growth are possible.
Some disadvantages of the sputtering process are that the process is more difficult to
combine with a lift-off process for structuring the film. This is because the diffuse transport,
characteristic of sputtering, makes a full shadow impossible. Thus, one cannot fully restrict
where the atoms go, which can lead to contamination problems. Also, active control for
layer-by-layer growth is difficult compared to pulsed laser deposition and inert sputtering
gases are built into the growing film as impurities.
Types of sputter deposition
Sputtering sources are usually magnetrons that utilize
strong electric and magnetic fields to trap electrons
close to the surface of the magnetron, which is known
as the target. The electrons follow helical paths around
the magnetic field lines undergoing more ionizing
collisions with gaseous neutrals near the target surface
than would otherwise occur. The sputter gas is inert,
A typical ring-geometry sputter target,
typically argon. The extra argon ions created as a result
gold showing the cathode made of
of these collisions leads to a higher deposition rate. It
the material to be deposited, the anode
also means that the plasma can be sustained at a lower
counter-electrode and an outer ring
pressure. The sputtered atoms are neutrally charged
meant to prevent sputtering of the
hearth that holds the target.
and so are unaffected by the magnetic trap. Charge
build-up on insulating targets can be avoided with the
use of RF sputtering where the sign of the anode-cathode bias is varied at a high rate. RF
sputtering works well to produce highly insulating oxide films but only with the added
expense of RF power supplies and impedance matching networks. Stray magnetic fields
leaking from ferromagnetic targets also disturb the sputtering process. Specially designed
sputter guns with unusually strong permanent magnets must often be used in
Sputter deposition
Ion-beam sputtering
Ion-beam sputtering (IBS) is a method in which the
target is external to the ion source. A source can work
without any magnetic field like in a hot filament
ionization gauge . In a Kaufman source, ions are
generated by collisions with electrons that are confined
by a magnetic field as in a magnetron. They are then
accelerated by the electric field emanating from a grid
toward a target. As the ions leave the source they are
neutralized by electrons from a second external
filament.[1] IBS has an advantage in that the energy and
flux of ions can be controlled independently. Since the
flux that strikes the target is composed of neutral
atoms, either insulating or conducting targets can be
sputtered. IBS has found application in the manufacture
A magnetron sputter gun showing the
of thin-film heads for disk drives. A pressure gradient
target-mounting surface, the vacuum
feedthrough, the power connector and
between the ion source and the sample chamber is
the water lines. This design uses a disc
generated by placing the gas inlet at the source and
target as opposed to the ring geometry
shooting through a tube in into the sample chamber.
illustrated above.
This saves gas and reduces contamination in UHV
applications. The principal drawback of IBS is the large
amount of maintenance required to keep the ion source operating.
Reactive sputtering
In reactive sputtering, the deposited film is formed by chemical reaction between the target
material and a gas which is introduced into the vacuum chamber. Oxide and nitride films
are often fabricated using reactive sputtering. The composition of the film can be controlled
by varying the relative pressures of the inert and reactive gases. Film stoichiometry is an
important parameter for optimizing functional properties like the stress in SiNx and the
index of refraction of SiOx. The transparent indium tin oxide conductor that is used in
optoelectronics and solar cells is made by reactive sputtering.
Ion-assisted deposition
In ion-assisted deposition (IAD), the substrate is exposed to a secondary ion beam operating
at a lower power than the sputter gun. Usually a Kaufman source like that used in IBS
supplies the secondary beam. IAD can be used to deposit carbon in diamond-like form on a
substrate. Any carbon atoms landing on the substrate which fail to bond properly in the
diamond crystal lattice will be knocked off by the secondary beam. NASA used this
technique to experiment with depositing diamond films on turbine blades in the 1980s. IAS
is used in other important industrial applications such as creating tetrahedral amorphous
carbon surface coatings on hard disk platters and hard transition metal nitride coatings on
medical implants.
Sputter deposition
generation of a high density
generated in a side chamber
opening into the main process
target and the substrate to be
coated. As the plasma is
generated remotely, and not
from the target itself (as in
Comparison of target utilization via HiTUS process - 95%
sputtering), the ion current to
the target is independent of the voltage applied to the target.
High Power Impulse Magnetron Sputtering (HIPIMS)
HIPIMS is a method for physical vapor deposition of thin films which is based on magnetron
sputter deposition. HIPIMS utilizes extremely high power densities of the order of kWcm−2
in short pulses (impulses) of tens of microseconds at low duty cycle of < 10%.
Gas flow sputtering
The process makes use of the hollow cathode effect, by which also hollow cathode lamp are
operated. In gas flow sputtering a working gas like argon is led through an opening in a
metal subjected to a negative electrical potential [2] [3] . Enhanced plasma densities occur in
the hollow cathode, if the pressure in the chamber p and a characteristic dimension L of the
hollow cathode obey the Paschen relation 0.5 Pa·m < p·L < 5 Pa·m. This causes a high flux
of ions on the surrounding surfaces and a large sputter effect. The hollow-cathode based
gas flow sputtering may thus be associated with large deposition rates up to values of a few
µm/min [4] .
Structure and morphology
In 1974 J. A. Thornton from Telic Corp. applied the structure zone model for the description
of thin film morphologies to sputter deposition. In a study on metallic layers prepared by
DC sputtering [5] , he extended the structure zone concept initially introduced by Movchan
and Demchishin for evaporated films [6] . Thornton introduced a further structure zone T,
which was observed at low argon pressures and characterized by densely packed fibrous
grains. The most important point of this extension was to emphasize the pressure p as a
decisive process parameter. In particular, if hyperthermal techniques like sputtering etc.
are used for the sublimation of source atoms, the pressure governs via the mean free path
the energy distribution with which they impinge on the surface of the growing film. Next to
the deposition temperature Td the chamber pressure or mean free path should thus always
be specified when considering a deposition process.
Sputter deposition
Since sputter deposition belongs to the group of plasma-assisted processes, next to neutral
atoms also charged species (like argon ions) hit the surface of the growing film, and this
component may exert a large effect. Denoting the fluxes of the arriving ions and atoms by Ji
and Ja, it turned out that the Ji/Ja ratio decides the microstructure and morphology of the
deposited film [7] . The effect of ion bombardment may quantitatively be derived from
structural parameters like preferred orientation of crystallites or texture and from the state
of residual stress. It has been shown recently [8] that textures and residual stresses may
arise in gas-flow sputtered Ti layers that compare to those obtained in macroscopic Ti work
pieces subjected to a severe plastic deformation by shot peening.
Further reading
• Magnetron sputtering theory [9]
• Sputtering Basics - animated film of a sputtering process [10]
• The Foundations of Vacuum Coating Technology by D. Mattox
• William D. Westwood (2003). Sputter Deposition, AVS Education Committee Book Series,
Vol. 2. ISBN 0-7354-0105-5.
External links
• SVS Vacuum Coating Technologies GmbH (Sputtering Systems & first routine industrial
application of HIPIMS technology) [12]
• Carnegie Mellon Nanofabrication Facility (14 Sputtering Systems & Over 200 Sputtering
Targets) [13]
• NNIN at Penn State [14]
• Sputter Animation [1]
• Ion beam sputter system contaminants [15]
[1] " What is a Kaufman Ion Source? (http:/ / www. ionbeam. co. uk/ kaufmanionsource. asp)". . Retrieved
[2] K. Ishii (1989). "High-rate low kinetic energy gas-flow-sputtering system". J. Vac. Sci. Technol. A 7: 256-258.
doi: 10.1116/1.576129 (http:/ / dx. doi. org/ 10. 1116/ 1. 576129).
[3] T. Jung and A. Westphal (1991). "Zirconia thin film deposition on silicon by reactive gas flow sputtering: the
influence of low energy particle bombardment". Mat. Sc. Eng. A 140: 528-533. doi:
10.1016/0921-5093(91)90474-2 (http:/ / dx. doi. org/ 10. 1016/ 0921-5093(91)90474-2).
[4] K. Ortner, M. Birkholz and T. Jung (2003). "Neue Entwicklungen beim Hohlkatoden-Gasflusssputtern". Vac.
Praxis 15: 236-239. doi: 10.1002/vipr.200300196 (http:/ / dx. doi. org/ 10. 1002/ vipr. 200300196).
[5] J.A. Thornton (1974). "Influence of apparatus geometry and deposition conditions on the structure and
topography of thick sputtered coatings". J. Vac. Sci. Tech. 11: 666-670. doi: 10.1116/1.1312732 (http:/ / dx. doi.
org/ 10. 1116/ 1. 1312732).
[6] B. A. Movchan and A. V. Demchishin (1969). "Study of the structure and properties of thick vacuum
condensates of nickel, titanium, tungsten, aluminium oxide and zirconium dioxide". Phys. Met. Metallogr. 28:
[7] H. Windischman (1992). "Intrinsic stress in sputter-deposited thin film". Crit. Rev. Sol. St. Mat. Sci. 17: 547.
doi: 10.1080/10408439208244586 (http:/ / dx. doi. org/ 10. 1080/ 10408439208244586).
[8] M. Birkholz, C. Genzel, and T. Jung (2004). " X-ray diffraction study of residual stress and preferred orientation
in thin titanium films subjected to a high ion flux during deposition (http:/ / www. mariobirkholz. de/ JAP2004.
pdf)". J. Appl. Phys. 96: 7202-7211. doi: 10.1063/1.1814413 (http:/ / dx. doi. org/ 10. 1063/ 1. 1814413). .
[9] http:/ / uk. geocities. com/ pvd_coatings/ theory. htm
[10] http:/ / www. heraeus-targets. com/ en/ technology/ _sputteringbasics/ sputtering. aspx
[11] http:/ / www. svc. org/ H/ HISTORYA. PDF
Sputter deposition
http:/ / svs-vct. com/
http:/ / www. nanofab. ece. cmu. edu
http:/ / www. mri. psu. edu/ facilities/ nnin/
http:/ / mywebsite. bigpond. com/ npajkic/ aerospace_materials/ ion_beam_sputter_system_contaminants. pdf
Substrate mapping
Substrate mapping, also known as 'wafer mapping' is a process in which the performance
of → semiconductor devices on a substrate is represented by a map showing the
performance as a colour-coded grid. The map is a convenient representation of the
variation in performance across the substrate, since the distribution of those variations may
be a clue as to their cause.
The concept also includes the package of data generated by modern → wafer testing
equipment which can be transmitted to equipment used for subsequent 'back-end'
manufacturing operations.
The initial process supported by substrate maps was
inkless binning.
Each tested die is assigned a bin value, depending on
the result of the test. For example, a pass die is
assigned a bin value of 1 for a good bin, bin 10 for an
open circuit, and bin 11 for a short circuit. In the very
early days of wafer test, the dies were put in different
bins or buckets, depending on the test results.
Physical binning may no longer be used, but the
analogy is still good. The next step in the process was
to mark the failing dies with ink, so that during
assembly only uninked dies were used for → die
attachment and final assembly. The inking step may be
skipped if the assembly equipment is able to access the
information in the maps generated by the test
Where the substrate map applies to an entire wafer, the
term 'wafer map' would be used, 'substrate map' is a
more general term, applied to mapping in other areas
of the semiconductors process: frames, trays and strips.
A wafer map: different bins are
represented by different colours
A strip map: this strip map represents
five panels on one strip. The lowerleft
square around the die on each panel
represents a reference die, which is
used to align between wafer testing
and die attachment
Substrate mapping
As with many items in the Semiconductor process area, also for this process step there are
standards available. The latest and most potential standard is the E142 standard, provided
by the SEMI organization [14]. This standard has been approved via ballots for release in
It supports many possible substrate maps, including the ones named above. While the old
standards could only support standard bin maps, representing bin information, this
standard also support transfermaps, which can help in tracing back dies on strips to the
locations they come from of the wafer for example.
External links
• SEMI organization
[1] http:/ / www. semi. org/
: organization which is working on semiconductor process
IUPAC name
Other names
titanium(IV)dimethylamide, TDMAT, tetrakis
CAS number
RTECS number
Molecular formula
Molar mass
224.19 g/mol
yellow liquid
0.947 g/cm³
Boiling point
50 °C at 0.05mmHg
Solubility in water
reacts with water
EU classification
16 - 26 - 36/37/39 - 43 - 45
NFPA 704
Except where noted otherwise, data are given for materials in their standard state (at 25 °C, 100 kPa)
Infobox references
Tetrakis(dimethylamido)titanium (TDMAT) is a chemical compound. The compound is
generally classified as a metalorganic species, meaning that its properties are strongly
influenced by the organic ligands but the compound lacks metal-carbon bonds. It is used in
→ chemical vapor deposition to prepare a → titanium nitride (TiN) surfaces. The prefix
"tetrakis" refers the the presence of four of the same ligand, in this case dimethylamides.
Preparation and properties
Tetrakis(dimethylamino)titanium is a conventional Ti(IV) compound in the sense that it is
tetrahedral and diamagnetic. Unlike the many alkoxides, the diorganoamides of titanium
are monomeric and thus at least somewhat volatile. It is prepared from titanium
tetrachloride (which is also tetrahedral, diamagnetic, and volatile) by treatment with
lithium dimethylamide:[2]
TiCl4 + 4 LiNMe2 → Ti(NMe2)4 + 4 LiCl
Like many amido complexes, TDMAT is quite sensitive toward water, and its handling
requires air-free techniques. The ultimate product of its hydrolysis is titanium dioxide:
Ti(NMe2)4 + 2 H2O → TiO2 + 4 HNMe2
In a related reaction, the compound undergoes exchange with other amines, evolving
See also
• → Metalorganic chemical vapor deposition (MOCVD), general process which includes
using TDMAT but also uses many other gases to layer other substances.
[1] http:/ / www. commonchemistry. org/ ChemicalDetail. aspx?ref=3275-24-9
[2] D. C. Bradley and I. M. Thomas, “Part I. Metallo-orgunic Compounds containing Metul-Nitrogen bonds. Some
Dialkylamino-derivatives of Titanium and Zirconium” J. Chem. Soc. 1960, 3857-3861. doi:
10.1039/JR9600003857 (http:/ / dx. doi. org/ 10. 1039/ JR9600003857).
Three-dimensional integrated circuit
Three-dimensional integrated circuit
In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip
with two or more layers of active electronic components, integrated both vertically and
horizontally into a single circuit. The → semiconductor industry is hotly pursuing this
promising technology in many different forms, but it is not yet widely used; consequently,
the definition is still somewhat fluid.
3D ICs vs. 3D packaging
3D → packaging saves space by stacking separate chips in a single package. This
packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the
chips into a single circuit. The chips in the package communicate with off-chip signaling,
much as if they were mounted in separate packages on a normal circuit board. In contrast,
a 3D IC is a single chip. All components on the layers communicate with on-chip signaling,
whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D
package that an SoC bears to a circuit board.
Manufacturing technologies
As of 2008 there are four ways to build a 3D IC:
Monolithic – Electronic components and their connections (wiring) are built in layers on a
single → semiconductor wafer, which is then → diced into 3D ICs. There is only one
substrate, hence no need for aligning, thinning, bonding, or → through-silicon vias.
Applications of this method are currently limited because creating normal transistors
requires enough heat to destroy any existing wiring.
Wafer-on-Wafer – Electronic components are built on two or more → semiconductor
wafers, which are then aligned, bonded, and → diced into 3D ICs. Each wafer may be
thinned before or after bonding. Vertical connections are either built into the wafers before
bonding or else created in the stack after bonding. These “→ through-silicon vias” (TSVs)
pass through the silicon substrate(s) between active layers and/or between an active layer
and an external bond pad.
Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer
is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. As
in the wafer-on-wafer method, thinning and TSV creation are performed either before or
after bonding. Additional dies may be added to the stacks before dicing.
Die-on-Die – Electronic components are built on multiple dies, which are then aligned and
bonded. Thinning and TSV creation may be done before or after bonding.
Three-dimensional integrated circuit
3D ICs offer many significant benefits, including:
Footprint – More functionality fits into a small space. This extends Moore’s Law and
enables a new generation of tiny but powerful devices.
Speed – The average wire length becomes much shorter. Because propagation delay is
proportional to the square of the wire length, overall performance increases.
Power – Keeping a signal on-chip reduces its power consumption by ten to a hundred
times.[1] Shorter wires also reduce power consumption by producing less parasitic
capacitance. Reducing the power budget leads to less heat generation, extended battery
life, and lower cost of operation.
Design – The vertical dimension adds a higher order of connectivity and opens a world of
new design possibilities.
Heterogeneous integration – Circuit layers can be built with different processes, or even
on different types of wafers. This means that components can be optimized to a much
greater degree than if they were built together on a single wafer. Even more interesting,
components with completely incompatible manufacturing could be combined in a single
device[2] .
Circuit security - The stacked structure hinders attempts to reverse engineer the
circuitry. Sensitive circuits may also be divided among the layers in such a way as to
obscure the function of each layer.[3]
Bandwidth - 3D integration allows large numbers of vertical vias between the layers. This
allows construction of wide bandwidth buses between functional blocks in different layers.
A typical example would be a processor+memory 3D stack, with the cache memory stacked
on top of the processor. This arrangement allows a bus much wider than the typical 128 or
256 bits between the cache and processor. Wide buses in turn alleviate the memory wall
Because this technology is new it carries new challenges, including:
Yield – Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be
commercially viable, defects must be avoided or repaired[5] .
Heat – Thermal buildup within the stack must be prevented or dissipated.
Design complexity – Taking full advantage of 3D requires intricate and elegant multi-level
designs. Chip designers will need new CAD tools to address the 3D paradigm.[6]
Three-dimensional integrated circuit
Further reading
• Philip Garrou, Christopher Bower, Peter Ramm: Handbook of 3D Integration, Technology
and Applications of 3D Integrated Circuits 2nd Edition. Wiley-VCH, Weinheim 2008,
ISBN: 978-3527-32034-9.
External links
Early products
• 2001, Monolithic write-once memory: “Matrix preps 64-Mbyte write-once memory” EE
Times [7]
• 2004, Wafer-to-wafer RAM: “MagnaChip, Tezzaron form partnership for 3D chips” EE
Times [8]
• 2007, Die-to-wafer focal plane array: “Ziptronix, Raytheon Prove 3-D Integration of 0.5
µm CMOS Device” Semiconductor International [9]
3D-IC Alliance [10]
EMC3D [11]
RTI “TechVenture” Forum
IMEC [14]
Selected press references
• 2003, EE Design: “Three-dimensional SoCs perform for future” [15]
• 2004, EDN: “3D Interconnect Technology Coming to Light” [16]
• 2005, Semiconductor International: “Three-Dimensional ICs Solve the Interconnect
Paradox” [17]
• 2006, Solid State Technology: “Mapping progress in 3D IC integration” [18]
• 2007, Nikkei Electronics Asia: “Vertical Stacking to Redefine Chip Design” [19]
• 2008, Semiconductor International: “How Might 3-D ICs Come Together?”
• 2009, Advanced Packaging: “Signs of 3D Maturity” [21]
[1] William J. Dally, “Future Directions for On-Chip Interconnection Networks” page 17, http:/ / www. ece.
ucdavis. edu/ ~ocin06/ talks/ dally. pdf Computer Systems Laboratory Stanford University, 2006
[2] James J-Q Lu, Ken Rose, & Susan Vitkavage “3D Integration: Why, What, Who, When?” http:/ / www.
future-fab. com/ documents. asp?d_ID=4396 Future Fab Intl. Volume 23, 2007
[3] "3D-ICs and Integrated Circuit Security" http:/ / www. tezzaron. com/ about/ papers/
3D-ICs_and_Integrated_Circuit_Security. pdf Tezzaron Semiconductor, 2008
[4] "Predicting the Performance of a 3D Processor-Memory Chip Stack" Jacob, P., McDonald, J.F. et al.Design &
Test of Computers, IEEE Volume 22, Issue 6, Nov.-Dec. 2005 Page(s):540 - 547
[5] Robert Patti, "Impact of Wafer-Level 3D Stacking on the Yield of ICs" http:/ / www. future-fab. com/
documents. asp?d_ID=4415 Future Fab Intl. Volume 23, 2007
[6] "EDA's big three unready for 3D chip packaging" http:/ / www. eetasia. com/
ART_8800485666_480300_NT_fcb98510. HTM EE Times Asia October 25, 2007
[7] http:/ / www. eetimes. com/ story/ OEG20011219S0041
[8] http:/ / www. eetimes. com/ news/ semi/ showArticle. jhtml?articleID=53700960
[9] http:/ / www. semiconductor. net/ article/ CA6431663. html
Three-dimensional integrated circuit
http:/ / www. 3d-ic. org/
http:/ / www. emc3d. org/
http:/ / techventure. rti. org/
http:/ / www. sematech. org/ corporate/ news/ releases/ 20070321. htm
http:/ / www. imec. be/
http:/ / www. eedesign. com/ article/ showArticle. jhtml?articleId=17408808
http:/ / www. edn. com/ article/ CA410764. html
http:/ / www. semiconductor. net/ article/ CA604503. html
http:/ / sst. pennnet. com/ Articles/ Article_Display. cfm?ARTICLE_ID=254615
http:/ / techon. nikkeibp. co. jp/ article/ HONSHI/ 20070328/ 129633/
http:/ / www. semiconductor. net/ article/ 202251-How_Might_3_D_ICs_Come_Together_. php
http:/ / ap. pennnet. com/ display_article/ 355057/ 36/ ARTCL/ none/ none/ 1/ Thoughts-on-the-News/
Through-silicon via
In electronic engineering, a through-silicon via (abbreviated TSV) is a vertical electrical
connection (via) passing completely through a silicon wafer or die. TSV technology is
important in creating 3D packages and 3D integrated circuits.
TSV technology in 3D packages
A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips
(integrated circuits) stacked vertically so that they occupy less space. In most 3D packages,
the stacked chips are wired together along their edges; this edge wiring slightly increases
the length and width of the package and usually requires an extra “interposer” layer
between the chips. In some new 3D packages, through-silicon vias replace edge wiring by
creating vertical connections through the body of the chips. The resulting package has no
added length or width. Because no interposer is required, a TSV 3D package can also be
flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as
TSS (Through-Silicon Stacking or Thru-Silicon Stacking).
TSV technology in 3D ICs
A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers
and/or dies and interconnecting them vertically so that they behave as a single device. By
using TSV technology, 3D ICs can pack a great deal of functionality into a small “footprint.”
In addition, critical electrical paths through the device can be drastically shortened, leading
to faster operation.
Titanium nitride
Titanium nitride
Titanium nitride
IUPAC name
CAS number
Molecular formula
Molar mass
61.874 g/mol
Coating of golden color
5.40 g/cm
Melting point
2930 °C
Solubility in water
Crystal structure
Cubic, cF8
Space group
Fm3m, No. 225
Except where noted otherwise, data are given for materials in their standard state (at 25 °C, 100 kPa)
Infobox references
Titanium nitride (TiN) (sometimes known as “Tinite” or “TiNite” or “TiNi”) is an
extremely hard ceramic material, often used as a coating on titanium alloys, steel, carbide,
and aluminium components to improve the substrate's surface properties.
Applied as a thin coating, TiN is used to harden and protect cutting and sliding surfaces, for
decorative purposes (due to its gold appearance), and as a non-toxic exterior for medical
Titanium nitride
Summary of characteristics[2]
Vickers hardness 18-21 GPa
Modulus of elasticity 251 GPa
Thermal conductivity 19.2 W/(m·°C)
Thermal expansion coefficient 9.35 µm/°C
Electrical resistivity 20 µOhm·cm
Superconducting transition temperature 5.6 K
Magnetic susceptibility +38x10-6 emu/mol
TiN will oxidize at 800 °C at normal atmosphere. It is chemically stable at room
temperature and is attacked by hot concentrated acids.[2]
TiN has excellent infrared (IR) reflectivity properties, reflecting in a spectrum similar to
elemental gold (Au). Depending on the substrate material and surface finish, TiN will have a
coefficient of friction ranging from 0.4 to 0.9 versus itself (non-lubricated). Typical
formation has a crystal structure of NaCl-type with a roughly 1:1 stoichiometry; however
TiNx compounds with x ranging from 0.6 to 1.2 are thermodynamically stable.[4]
The most common use for TiN coating is for edge retention
and corrosion resistance on machine tooling, such as drill
bits and milling cutters, often improving their lifetime by a
factor of three or more.
Because of TiN's metallic gold color, it is used to coat
costume jewelry and automotive trim for decorative
purposes. TiN is also widely used as a top-layer coating,
usually with nickel (Ni) or chromium (Cr) plated substrates,
on consumer plumbing fixtures and door hardware. TiN is
non-toxic, meets FDA guidelines and has seen use in medical
devices such as scalpel blades and orthopedic bone saw
blades where sharpness and edge retention are important[5]
and medical implants, as well as aerospace and military
Such coatings have also been used in implanted prostheses
(especially hip replacement implants). Such films are usually
applied by either reactive growth (for example, annealing a
piece of titanium in nitrogen) or → physical vapor deposition
(PVD), with a depth of about 3 micrometers. Its high Young's
modulus (600 gigapascals)[6] relative to titanium alloys (100
GPa) means that thick coatings tend to flake away, making
them much less durable than thin ones.
TiN coated drill bit
As a coating it is also used to protect the sliding surfaces of
suspension forks of bicycles and motorcycles as well as the shock shafts of radio controlled
Titanium nitride
Though less visible, thin films of TiN are also used in the semiconductor
industry. In copper-based chips, such films find use as a conductive
barrier between a silicon device and the metal contacts used to operate it.
While the film blocks diffusion of metal into the silicon, it is conductive
enough (30–70 μΩ·cm) to allow a good electrical connection. In this
context, TiN is classified as a "→ barrier metal", even though it is clearly a
ceramic from the perspective of chemistry or mechanical behavior. Recent
chip design in the 45 nm technology and beyond also makes use of TiN as
a metal material for improved transistor performance. In combination
with gate dielectrics (e.g. HfSiO) that have a higher permittivity compared
to standard SiO2 the gate length can be scaled down with low leakage,
higher drive current and same or better threshold voltage.[7]
Led by Argonne senior scientist Valerii Vinokur and Russian scientist
Tatyana Baturina, an international team of scientists from Argonne,
Germany, Russia and Belgium fashioned a thin film of titanium nitride
which they then chilled to near absolute zero. This converts the material
to a superinsulator, with resistance suddenly increased by a factor of
Dark gray TiCN
coating on a
The most common methods of TiN thin film creation are → physical vapor deposition (PVD,
usually → sputter deposition, cathodic arc deposition or electron beam heating) and →
chemical vapor deposition (CVD). In both methods, pure titanium is sublimated and reacted
with nitrogen in a high-energy, vacuum environment. PVD is preferred for steel parts
because the deposition temperatures lie beyond the austenitizing temperature of steel. PVD
applied TiN is also for a variety of higher melting point materials such as stainless steels,
titanium and titanium alloys.[9]
Bulk ceramic objects can be fabricated by packing powdered metallic titanium into the
desired shape, compressing it to the proper density, then igniting it in an atmosphere of
pure nitrogen. The heat released by the chemical reaction between the metal and gas is
sufficient to sinter the nitride reaction product into a hard, finished item. See powder
metallurgy. Titanium nitride coatings can also be deposited by thermal spraying whereas
TiN powders are produced by nitridation of titanium with nitrogen or ammonia at 1200
Titanium nitride
Other commercial variants
There are several commercially-used variants of TiN
that have been developed in the past decade, such
titanium carbon nitride (TiCN) and titanium aluminium
nitride (TiAlN), which may be used individually or in
alternating layers with TiN. These coatings offer similar
or superior enhancements in corrosion resistance and
hardness, and additional colors ranging from light gray
to nearly black, to a dark iridescent bluish-purple
A knife with a Titanium OxyNitride
depending on the exact process of application. These
coatings are becoming common on sporting goods,
particularly knives and handguns, where they are used for both cosmetic and functional
As a constituent in steel making
Titanium nitride is also produced intentionally within some steels by judicious addition of
titanium to the alloy. TiN forms at very high temperatures because of its very low enthalpy
of formation, and even nucleates directly from the melt in secondary steelmaking. It forms
discrete, micrometre-sized cubic particles at grain boundaries and triple points, and
prevents grain growth by Ostwald ripening up to very high homologous temperatures.
Titanium nitride has the lowest solubility product of any metal nitride or carbide in
austenite, a useful attribute in microalloyed steel formulas.
External links
[1] http:/ / www. commonchemistry. org/ ChemicalDetail. aspx?ref=25583-20-4
[2] Hugh O. Pierson (1996). Handbook of refractory carbides and nitrides: properties, characteristics, processing,
and applications (http:/ / books. google. co. jp/ books?id=pbt-RWodmVAC& pg=PA193). William Andrew. p. 193.
ISBN 0815513925. .
[3] Stone, D. S.; K. B. Yoder; W. D. Sproul (July 1991). "Hardness and elastic modulus of TiN based on continuous
indentation technique and new correlation". Journal of Vacuum Science and Technology A 9 (4): 2543-2547.
doi: 10.1116/1.577270 (http:/ / dx. doi. org/ 10. 1116/ 1. 577270).
[4] Toth, L.E. (1971). Transition Metal Carbides and Nitrides. New York: Academic Press.
[5] " Products (http:/ / www. ionfusion. com/ products. htm)". IonFusion Surgical. . Retrieved 2009-06-25.
[6] " Titanium Nitride (TiN) Coating (http:/ / www. matweb. com/ search/ datasheet.
aspx?MatGUID=ffbf753c500949db95e502e043f9a404)". MatWeb. . Retrieved 2009-06-25.
[7] Dziura, Thaddeus G.; Benjamin Bunday; Casey Smith; Muhammad M. Hussain; Rusty Harris; Xiafang Zhang;
Jimmy M. Price (2008). "Measurement of high-k and metal film thickness on FinFET sidewalls using
scatterometry". Proceedings of SPIE (International Society for Optical Engineering) 6922 (2): 69220V. doi:
10.1117/12.773593 (http:/ / dx. doi. org/ 10. 1117/ 12. 773593).
[8] " Newly discovered 'superinsulators' promise to transform materials research, electronics design (http:/ /
www. physorg. com/ news126797387. html)". 2008-04-07. .
[9] " Specialties (http:/ / www. mmicoating. com/ technology. html)". Molecular Metallurgy, Inc. . Retrieved
[10] " Product Guide (http:/ / www. mmicoating. com/ product. html)". Molecular Metallurgy, Inc. . Retrieved
IUPAC name
CAS number
Molecular formula
Molar mass
114.827 g/mol
clear colourless liquid
Melting point
−15 °C
Boiling point
55.7 °C
Main hazards
Except where noted otherwise, data are given for materials in their standard state (at 25 °C, 100 kPa)
Infobox references
Trimethylgallium, Ga(CH3)3, often abbreviated to TMG, is the preferred metalorganic
source of gallium for metalorganic vapour phase epitaxy (MOVPE) of gallium-containing
compound semiconductors, such as GaAs, GaN, GaP, GaSb, InGaAs, InGaN, AlGaInP, InGaP
and AlInGaNP.
TMG is a clear, colorless, pyrophoric liquid[2] . Even the hydrocarbon solutions of TMG,
when sufficiently saturated, are known to catch fire on exposure to air. TMG is known to
react violently with water and other compounds that are capable of providing labile active
hydrogen (i.e. protons). Therefore, TMG needs to be handled with care and caution, e.g.
stored in a cool, dry place at 0 to 25 °C, under inert atmosphere, and ensuring that storage
temperatures would not exceed 40 °C to avoid deterioration.
External links
• Informative commercial link to Trimethylgallium and other metalorganics.
• Interactive Vapor Pressure Chart for metalorganics [4].
[1] http:/ / www. commonchemistry. org/ ChemicalDetail. aspx?ref=1445-79-0
[2] Journal of Crystal Growth (2004); doi: doi:10.1016/j.jcrysgro.2004.09.007 (http:/ / dx. doi. org/ doi:10. 1016/ j.
jcrysgro. 2004. 09. 007)
[3] http:/ / electronicmaterials. rohmhaas. com/ products/ default. asp?product=Trimethylgallium
[4] http:/ / electronicmaterials. rohmhaas. com/ businesses/ micro/ metalorganics/ vapor. asp?caid=291
Vapour phase decomposition
Vapour phase decomposition (VPD) is a method used in the semiconductor industry to
improve the sensitivity of atomic absorption spectroscopy (AAS) in order to detect metal
impurities of very small concentrations on → wafer surfaces.
This can be achieved by enhancing the impurity concentration in the solution to be
analyzed. In standard AAS, the impurity is dissolved together with the matrix element. In
VPD, the surface of the wafer is exposed to hydrofluoric acid vapour, which causes the
surface oxide to dissolve together with the impurity metals. The acid droplets, condensed
on the surface, are then analyzed using AAS.
The method has yielded good results for the detection and measurement of nickel and iron.
Wafer (electronics)
A wafer is a thin slice of semiconductor material, such
as a silicon crystal, used in the fabrication of integrated
circuit and other microdevices. The wafer serves as the
substrate for microelectronic devices built in and over
the wafer and undergoes many → microfabrication
process steps such as doping or → ion implantation, →
etching, deposition of various materials, and →
photolithographic patterning.
Several types of solar cells are made from such wafers.
A solar wafer is a circular solar cell made from the
entire wafer (rather than cutting into smaller
rectangular solar cells).
An etched silicon wafer
Wafer (electronics)
Intel's silicon wafer
Wafers are formed of highly
pure (99.9999% purity), [1]
crystalline material
. One
process for forming crystalline
Czochralski growth invented
by the Polish chemist Jan
Czochralski. In this process, a
cylindrical ingot of high purity
crystalline silicon is formed by
pulling a seed crystal from a
'melt'. [3] [4]
The → Czochralski process.
The ingot is then sliced with
an inner diameter diamond
coated blade and polished to
form wafers [5] . The size of
wafers for photovoltaics is 100
– 200 mm square and the
thickness is 200 - 300 μm. In
the future, 160 μm will be the
standard [6] . Electronics use
wafer sizes from 100 - 300mm
2 inch, 4 inch, 6 inch, and 8 inch wafers
The resulting thin wafers can then be doped to achieve the desired electronic properties.
Wafer (electronics)
Cleaning, texturing and etching
Wafers are cleaned with weak acids to remove unnecessary particles, or repair damage
caused in the sawing process. The wafers are textured to create a rough surface to increase
the solar cell efficiency. The generated PSG (→ phosphorus silicate glass) is removed from
the edge of the wafer in the etching [7] .
Wafer properties
Standard wafer sizes
Silicon wafers are available in a variety of sizes from 25.4 mm (1 inch) to 300 mm (11.8
inches). [8] → Semiconductor fabrication plants (also known as fabs) are defined by the size
of wafers that they are tooled to produce. The size has gradually increased to improve
throughput and reduce cost with the current state-of-the-art fab considered to be 300mm
(12 inch), with the next standard set to be 450mm (18 inch).[9] [10] Intel, TSMC and
Samsung are separately conducting research to the advent of 450mm "prototype"
(research) fabs by 2012. Dean Freeman, an analyst with Gartner Inc., predicted that
production fabs could emerge sometime between the 2017 and 2019 timeframe.[11]
1 inch.
2 inch (50.8 mm). Thickness 275 µm.
3 inch (76.2 mm). Thickness 375 µm.
4 inch (100 mm). Thickness 525 µm.
5 inch (127 mm) or 125 mm (4.9 inch). Thickness 625 µm.
150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
• 300 mm (11.8 inch, usually referred to as "12 inch" or "Pizza size" wafer). Thickness 775
• 450 mm ("18 inch"). Thickness 925 µm (expected).[12]
Wafers grown using materials other than silicon are generally not available in sizes over
100 mm, and will have different thicknesses than a silicon wafer of the same diameter.
Wafer thickness is determined by the mechanical strength of the material used; the wafer
must be thick enough to support its own weight without cracking during handling.
The larger the wafer, the less space on the edges as a percentage of total space. This
means, less of the wafer is un-etched, and in theory should have higher productivity. This is
the basis of shifting to larger and larger wafer sizes. Conversion to 300 mm wafers from
200 mm wafers began in earnest in 2000, and reduced the price per die about 30-40%.[13]
However, this was not without significant problems for the industry.
The next step to 450 mm should accomplish similar productivity gains as the previous size
increase. However, machinery needed to handle and process larger wafers results in
increased investment costs to build a single factory. There is considerable resistance to
moving up to 450 mm by 2012 despite the obvious productivity enhancements, mainly
because companies feel it would take too long to recoup their investment.[14] The difficult
and costly 300 mm process only accounted for appoximately 20% of worldwide capacity on
a square inches basis by the end of 2005.[15] The step up to 300 mm required a major
change from the past, with fully automated factories using 300 mm wafers versus barely
automated factories for the 200 mm wafers. These major investments were undertaken in
the economic downturn following the dot-com bubble, resulting in huge resistance to
Wafer (electronics)
upgrading to 450 mm by the original timeframe.
Other initial technical problems in the ramp up to 300 mm included vibrational effects,
gravitational bending (sag), and problems with flatness. Among the new problems in the
ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric
ton) and take 2-4 times longer to cool, and the process time will be double.[16] All told, the
development of 450 mm wafers require significant engineering, time, and cost to overcome.
Analytical die count estimation
For any given wafer diameter [d, mm] and target IC size [S, mm2], there is an exact number
of integral die pieces that can be sliced out of the wafer. The gross Die Per Wafer [DPW]
can be estimated by the following expression:
Note, that the gross die count does not take into account the die defect loss, various
alignment markings and test sites on the wafer.
Crystalline orientation
Wafers are grown from crystal having a regular crystal
structure, with silicon having a diamond cubic structure
with a lattice spacing of 5.430710 Å (0.5430710 nm).
When cut into wafers, the surface is aligned in one
of several relative directions known as crystal
orientations. Orientation is defined by the Miller index
with [100] or [111] faces being the most common for
silicon. [17] Orientation is important since many of a
single crystal's structural and electronic properties are
highly anisotropic. → Ion implantation depths depend
on the wafer's crystal orientation, since each direction
Diamond Cubic Crystal Structure,
offers distinct paths for transport. [18] Wafer cleavage
Silicon unit cell
typically occurs only in a few well-defined directions.
Scoring the wafer along cleavage planes allows it to be
easily diced into individual chips ("dies") so that the billions of individual circuit elements
on an average wafer can be separated into many individual circuits.
Wafer flats and orientation notches
Wafers under 200 mm generally have flats cut into one or more sides indicating
crystallographic planes of high symmetry (usually the {110} face) and, in old-fashioned
wafers (those below about 100 mm diameter), the wafer's orientation and doping type (see
illustration for conventions). Modern wafers use a notch to convey this information, in order
to waste less material [19] .
Wafer (electronics)
Impurity doping
Silicon wafers are generally not 100% pure silicon, but
are instead formed with an initial impurity doping
concentration between 1013 and 1016 per cm3 of boron,
phosphorus, arsenic, or antimony which is added to the
melt and defines the wafer as either bulk n-type or
p-type.[20] However, compared with single-crystal
silicon's atomic density of 5×1022 atoms per cm3, this
still gives a purity greater than 99.9999%. The wafers
can also be initially provided with some interstitial
contamination are kept to a minimum.
metals, in particular, must be kept below parts per
billion concentrations for electronic applications. [22]
Flats can be used to denote doping and
crystallographic orientation. Red
represents material that has been
Compound semiconductors
While silicon is the most prevalent type of wafer used in the electronics industry, other
compound III-V or II-VI type wafers have also been employed. Gallium arsenide (GaAs)
wafers are one common III-V semiconductor material which can be produced using the
Czochralski process. [4]
See also
Crystalline silicon
→ Epitaxy
Layer (electronics)
Low-cost solar cell
→ Rapid thermal processing
Screen printing
Silicon on insulator (SOI) wafers
Solar panel
→ RCA clean
Zone melting
Wafer (electronics)
External links
• Everything Wafers [23] - A guide to semiconductor substrates type, property, cleaving,
etching, and fabrication.
• Star Silicon [24] - Information and products related to the Silicon Wafer and Solar Wafer
[1] name="Semi" SemiSource 2006: A supplement to Semiconductor International. December 2005. Reference
Section: How to Make a Chip. Adapted from Design News. Reed Electronics Group.
[2] SemiSource 2006: A supplement to Semiconductor International. December 2005. Reference Section: How to
Make a Chip. Adapted from Design News. Reed Electronics Group.
[3] Levy, Roland Albert (1989). Microelectronic Materials and Processes (http:/ / books. google. com/
books?id=wZPRPU6ne7UC& pg=PA248& sig=8JXOn_Dc0fPFnyEEkWh53lKWCOk#PPA6,M1). pp. 1–2. ISBN
0792301544. . Retrieved 2008-02-23.
[4] Grovenor, C. (1989). Microelectronic Materials (http:/ / books. google. com/ books?id=Ecl_mnz1xcUC&
pg=PA122& dq=GaAs+ Wafer+ Manufacture& as_brr=3&
sig=eu7LVmemnCFtCk9s0Cmo4HK4OwM#PPA113,M1). CRC Press. pp. 113–123. ISBN 0852742703. .
Retrieved 2008-02-25.
[5] Nishi, Yoshio (2000). Handbook of Semiconductor Manufacturing Technology (http:/ / books. google. com/
books?id=Qi98H-iTgLEC& pg=PA70& dq=wafer+ flat+ and+ notch&
sig=j6VYgO2HhC_UBhanpRLa9UZC4Pk#PPA71,M1). CRC Press. pp. 67–71. ISBN 0824787838. . Retrieved
http:/ / www. omron-semi-pv. eu/ en/ wafer-based-pv/ wafer-preparation/ slicing-the-ingot. html
http:/ / www. omron-semi-pv. eu/ en/ wafer-based-pv/ front-end/ wet-process. html
" Silicon Wafer (http:/ / www. semiwafer. com/ products/ silicon. htm)". . Retrieved 2008-02-23.
Intel, Samsung, TSMC reach agreement about 450mm tech (http:/ / www. intel. com/ pressroom/ archive/
releases/ 20080505corp. htm)
[10] Presentations/PDF/FEP.pdf ITRS Presentation (PDF) (http:/ / www. itrs. net/ Links/ 2008Summer/ Public)
[11] Industry Agrees on first 450-mm wafer standard - (http:/ / www. eetimes. com/ news/ latest/
showArticle. jhtml?articleID=211300360& pgno=1), retrieved on October 22, 2008.
[12] Industry Agrees on first 450-mm wafer standard - (http:/ / www. eetimes. com/ news/ latest/
showArticle. jhtml?articleID=211300360& pgno=1)
[13] for 300 mm: Approaching Industry Goals (http:/ / www. semiconductor. net/
article/ CA47551. html)
[14] 450 mm: A Promise Postponed (http:/ / www. semiconductor. net/ article/ CA6445470. html?nid=3655)
[15] A Simulation Study of the Cost and Economics of 450 mm Wafers (http:/ / www. semiconductor. net/ article/
CA6617173. html?nid=3660)
[16] Wafer Thickness for 450 mm (http:/ / www. semiconductor. net/ article/
CA6617173. html?nid=3660)
[17] O'Mara, William C. (1990). Handbook of Semiconductor Silicon Technology (http:/ / books. google. com/
books?id=COcVgAtqeKkC& pg=PA351& dq=Czochralski+ Silicon+ Crystal+ Face+ Cubic& lr=& as_brr=3&
sig=ht-dgSy1lzBMYC7IXPp9W5QBqYo). William Andrew Inc.. p. 349-352. ISBN 0815512376. . Retrieved
[18] Nishi, Yoshio (2000). Handbook of Semiconductor Manufacturing Technology (http:/ / books. google. com/
books?id=Qi98H-iTgLEC& pg=PA70& dq=wafer+ flat+ and+ notch&
sig=j6VYgO2HhC_UBhanpRLa9UZC4Pk#PPA71,M1). CRC Press. pp. 108–109. ISBN 0824787838. . Retrieved
[19] " Wafer Flats (http:/ / www. tf. uni-kiel. de/ matwis/ amat/ elmat_en/ kap_5/ illustr/ i5_2_4. html)". . Retrieved
[20] Widmann, Dietrich (2000). Technology of Integrated Circuits (http:/ / books. google. com/
books?id=uYNn1N6YSwQC& pg=PA39& dq=Czochralski+ Doping+ Silicon& as_brr=3&
sig=xRljFzhA9fSbRddEc3Gg3-Wht2U). Springer. pp. 39. ISBN 3540661999. . Retrieved 2008-02-24.
[21] Levy, Roland Albert (1989). Microelectronic Materials and Processes (http:/ / books. google. com/
books?id=wZPRPU6ne7UC& pg=PA248& sig=8JXOn_Dc0fPFnyEEkWh53lKWCOk#PPA1,M1). pp. 6–7, 13.
ISBN 0792301544. . Retrieved 2008-02-23.
[22] Rockett, Angus (2008). The Materials Science of Semiconductors. pp. 13. ISBN 9780387256535.
Wafer (electronics)
[23] http:/ / www. ee. byu. edu/ cleanroom/ everything_wafers. phtml
[24] http:/ / www. starsilicon. com/
Wafer dicing
Wafer dicing is the process by which individual silicon chips or integrated circuits on a
silicon wafer or ceramic tile are separated following the processing of the wafer. The dicing
process can be accomplished by scribing and breaking, by mechanical sawing (normally
with a machine called a Dicing Saw) or by laser cutting. Following the dicing process the
individual silicon chips are encapsulated into I.C. Packages which are then suitable for use
in building electronic devices such as computers, etc.
During dicing, silicon wafers are typically mounted on dicing tape which has a sticky
backing that holds the wafer on a thin sheet metal frame. Once a wafer has been diced, the
remaining components that are left on the dicing tape are referred to as die, dice or dies;
these are the small integrated circuits that will be integrated into a lead-frame package or
placed directly on a PC board substrate as a "bare die". The area that has been cut away
are called die streets which are typically about 75 micrometres (0.003 inch) wide. Once a
wafer has been diced, the die will stay on the dicing tape until they are extracted by die
handling equipment, like a die bonder or die sorter, further in the electronics assembly
The size of the die left on the tape may range from 35 mm (very large) to 0.5 mm square
(very small). The die created may be any shape generated by straight lines, but they are
typically rectangular or square shaped.
Materials diced include:
• Ceramics.
• Delicate compound semiconductors.
Depending upon the material, kerf may be as small as 50 micrometres, and dies may be
diced as small as 300 micrometres. [1]
External links
• Edgetek [2] thinning, polishing, dicing, picking, inspection, assembly, bonding, over
molding, test, shipping
[1] http:/ / www. edgetek. fr/ EN
[2] http:/ / www. edgetek. fr
Wafer fabrication
Wafer fabrication
Wafer Fabrication is a procedure composed of many repeated sequential processes to
produce complete electrical or photonic circuits. Examples include production of radio
frequency (RF) amplifiers, LEDs, optical computer components, and CPUs for computers.
Wafer fabrication is used to build components with the necessary electrical structures.
The main process begins with electrical engineers designing the circuit and defining its
functions, and specifying the signals, inputs, outputs and voltages needed. These electrical
circuit specifications are entered into electrical circuit design software, such as SPICE, and
then imported into circuit layout programs, which are similar to ones used for computer
aided design. This is necessary for the layers to be defined for wafer mask production. The
resolution of the circuits increases rapidly with each step in design, as the scale of the
circuits at the start of the design process is already being measured in fractions of
micrometers. Each step thus increases circuit density for a given area.
The silicon wafers start out blank and pure. The circuits are built in layers in clean rooms.
First, photo-sensitive resistance patterns are photo-masked in micrometer detail onto the
wafers' surface. The wafers are then exposed to short-wave ultraviolet light and the
unexposed areas are thus etched away and → cleaned. Hot chemical vapors are deposited
on to the desired zones and baked in high heat, which permeate the vapors into the desired
zones. In some cases, ions, such as O2+ or O+, are implanted in precise patterns and at a
specific depth by using RF-driven ion sources.
These steps are often repeated many hundreds of times, depending on the complexity of the
desired circuit and its connections.
New processes to accomplish each of these steps with better resolution and in improved
ways emerge every year, with the result of constantly changing technology in the wafer
fabrication industry. New technologies result in denser packing of minuscule surface
features such as transistors and micro-electro-mechanical systems (MEMS). This increased
density continues the trend often cited as Moore's Law.
A → fab is a common term for where these processes are accomplished. Often the fab is
owned by the company that sells the chips, such as AMD, Intel, Texas Instruments, or
Freescale. A foundry is a fab at which semiconductor chips or wafers are fabricated to
order for third party companies that sell the chip, such as fabs owned by Taiwan
Semiconductor Manufacturing Company (TSMC), United Microelectronics Corporation
(UMC) and Semiconductor Manufacturing International Corporation (SMIC).
Wafer-scale integration
Wafer-scale integration
Wafer-scale integration, WSI for short, is a yet-unused system of building very-large
integrated circuit networks that use an entire → silicon wafer to produce a single
"super-chip". Through a combination of large size and reduced packaging, WSI could lead
to dramatically reduced costs for some systems, notably massively parallel supercomputers.
The name is taken from the term very-large-scale integration, the current state of the art
when WSI was being developed.
The concept
To understand WSI, one has to consider the normal chip-making process. A single large
cylindrical crystal of silicon is produced and then cut into disks known as wafers. The
wafers are then cleaned and polished in preparation for the fabrication process. A
photographic process is used to pattern the surface where material ought to be deposited
on top of the wafer and where not to. The desired material is deposited and the
photographic mask is removed for the next layer. From then on the wafer is repeatedly
processed in this fashion, putting on layer after layer of circuitry on the surface.
Multiple copies of these patterns are deposited on the wafer in a grid fashion across the
surface of the wafer. After all the possible locations are patterned, the wafer surface
appears like a sheet of graph paper, with grid lines delineating the individual chips. Each of
these grid locations is tested for manufacturing defects by automated equipment. Those
locations that are found to be defective are recorded and marked with a dot of paint. The
wafer is then sawed apart to cut out the individual chips. Those defective chips are thrown
away, or recycled, while the working chips are placed into packaging and re-tested for any
damage that might occur during the packaging process.
Flaws on the surface of the wafers and problems during the layering/depositing process are
impossible to avoid, and cause some of the individual chips to be defective. The revenue
from the remaining working chips has to pay for the entire cost of the wafer and its
processing, including those discarded defective chips. Thus, the higher number of working
chips or higher yield, the lower the cost of each individual chip. In order to maximize yield
one wants to make the chips as small as possible, so that a higher number of working chips
can be obtained per wafer.
The vast majority of the cost of fabrication (typically 30%-50%) is related to testing and
packaging the individual chips. Further cost is associated with connecting the chips into an
integrated system (usually via a printed circuit board). Wafer-scale integration seeks to
reduce this cost, as well as improve performance, by building larger chips in a single
package – in principle, chips as large as a full wafer.
Of course this is not easy, since given the flaws on the wafers a single large design printed
onto a wafer would almost always not work. It has been an ongoing goal to develop
methods to handle faulty areas of the wafers through logic, as opposed to sawing them out
of the wafer. Generally, this approach uses a grid pattern of sub-circuits and "rewires"
around the damaged areas using appropriate logic. If the resulting wafer has enough
working sub-circuits, it can be used despite faults.
Wafer-scale integration
Production attempts
Many companies attempted to develop WSI production
systems in the 1970s and 80s, but all failed. TI and ITT
both saw it as a way to develop complex pipelined
microprocessors and re-enter a market where they
were losing ground, but neither released any products.
Gene Amdahl also attempted to develop WSI as a
method of making a supercomputer, starting Trilogy
Systems in 1980 and garnering investments from
Groupe Bull, Sperry Rand and Digital Equipment
Corporation, who (along with others) provided an
estimated $230 million in financing. The design called
for a 2.5" square chip with 1200 pins on the bottom.
Early WSI attempt by Trilogy Systems.
The effort was plagued by a series of disasters, including floods which delayed the
construction of the plant and later ruined the clean-room interior. After burning through
about 1/3rd of the capital with nothing to show for it, Amdahl eventually declared the idea
would only work with a 99.99% yield, which wouldn't happen for 100 years. He used
Trilogy's remaining seed capital to buy Elxsi in 1985, a maker of VAX-compatible machines.
The Trilogy efforts were eventually ended and "became" Elxsi.
The last serious attempt to use WSI appears to have been Clive Sinclair's involvement at his
MetaLab think tank. When looking for submissions for ideas, he received the plans of Ivor
Catt to produce a new WSI known as the Catt Spiral. Catt proposed to extend work that he
had previously done for Burroughs, this had been abandoned at about the same time as
Burroughs's merger with Sperry to become Unisys [1]. As the name implies, the Spiral was
not laid out in a grid, but a series of cylinders of small chips on the wafer, connected to all
of its neighbors.
After processing, the wafer was sent to a tester that connected in turn to the chips around
the outside rim of the wafer, testing each one until it found one that worked. When it did, it
would ask that working chip to pass along the test signals to one of its neighbors, starting
with the "next" one on the same track. This process was continued until it ran out of
working chips, thereby eventually finding all of the working ones on the wafer and writing
that information back into NVRAM. The design required only one set of pins, connected to
that first working chips, and did not require extensive packaging due to details of the wafer
Sinclair saw a sweet spot in the market at a time when RAM prices were still fairly high and
hard disk systems were very expensive. After preliminary meetings in 1983 Catt convinced
Sinclair that the idea was "for real" and started development of a 512kB memory that would
reduce the cost of future Sinclair products – it was a similar low-cost development from
Ferranti that made the original Sinclair products so inexpensive. Sinclair eventually
organized a new company, Anamartic, to produce the design, but a crash in RAM prices
soon rendered the entire system infeasible.
Ivor Catt continues to promote the idea today, as the basis for a spiral-like supercomputer
system he calls the Kernel. A basic Kernel would include 1 million processors in a 1000 by
1000 grid.
Wafer-scale integration
See also
• wafer-level Packaging
[1] http:/ / www. ivorcatt. org/ icr-ew47boole. pdf
Article Sources and Contributors
Article Sources and Contributors
Chemical vapor deposition Source: Contributors: 2over0, Afluegel, Altenmann, Amp, Anoopm,
Art Carlson, Beetstra, Bob, Bryan Derksen, CitizenB, Conversion script, DMTagatac, Danield101, Dave Foley, Dgrant, Dicklyon, Don Mattox, Drilnoth,
Duk, FSIM, Frap, Gene Nygaard, GregorB, Guillom, Hooperbloob, HopeChrist, Houbaamumu, Hugo-cs, IReceivedDeathThreats, Iepeulas, J. Finkelstein,
JMiall, Jaraalbe, Jeffrey Smith, Kaare, Kajit, Kkmurray, Krash, Krkaiser, Lisatwo, Lupinoid, Lysdexia, Mac Davis, Mark Yen, Markus Kuhn,
Materialscientist, Michael Hardy, Mike Dill, Mion, Mstoia, Nnh, Oleg Alexandrov, Opticcow, Ossmann, Pcmcelli, Physchim62, Pinktulip, Polyparadigm,
Pusher, Rifleman 82, RockMFR, Romanm, RyanSmith345, S-kei, SR, Sapphic, Shaddack, Shadow1, Smack, Some standardized rigour, Speedoflightning,
TheBendster, Tim Starling, Tooto, Twisp, Vsmith, Wqdai, WulfTheSaxon, 67 anonymous edits
Semiconductor device fabrication Source: Contributors: ARTE, Aaronmz, Altenmann, Ancheta
Wis, Arabani, ArielGold, Atlant, Axeman89, BC Mack, Bantman, Biblbroks, Bobblewik, Bobo192, Bramble k, Brews ohare, Bryan Derksen, Cbarnes12,
Cipherswarm, Conversion script, DESiegel, Dancter, Daniel.Cardenas, Dantheox, Darrensavery, David Carron, Deglr6328, Dicklyon, Dismas, Dr Napalm,
DrTorstenHenning, Duk, Dulciana, Edcolins, Fgb, Flowanda, Fourohfour, Garth 187, HenkeB, Hooperbloob, Huaiwei, JMPZ, Janke, Jcarroll, Jdawson76,
JeremyA, Jesse Viviano, John, Karlleeser, Kelisi, Kevin Schostek, King of Hearts, Kmccoy, Krellis, Kvkvamsi, Laudaka, Lone Skeptic, Luke Robison,
Mainstream Nerd, MariusStrom, Matt Britt, Mav, MikeDba, Myhister, Nate Silva, Neier, Nihonjoe, Nohat, NotMuchToSay, Oliver Lineham, Oliverdl, Phil
Holmes, Polyparadigm, Radagast83, Riconnaissance, Rmalloy, Rmhermen, Rnoonan, Romanski, Scottfisher, Shirifan, Shyland, Smack, Steveo1544,
Stokerm, Stuartfost, Subsolar, Tim Starling, Timwi, Tom verbeure, Triwbe, Underpants, Wavelength, William Avery, Xinghuei, 147 anonymous edits
Chemical- mechanical planarization Source: Contributors: Altenmann, Bobtucker13,
Cloud2cloud, Cmp rookie, Darrensavery, Dongyeh, Duk, Forbsey, Garion96, Gejigeji, Gentgeen, GregAsche, IMSeditor, IReceivedDeathThreats, KFrising,
Myatlasshrugged, Polyparadigm, Pxma, Quintote, Redlen, Shalom Yechiel, Su-no-G, Themintyman, Thermochap, 39 anonymous edits
Physical vapor deposition Source: Contributors: 1ForTheMoney, A. B., Altenmann,
Antonyaddy, Austintexas007, CharlesWemyss, DocWatson42, Don Mattox, Donald Albury, Drjonfox, Everyking, FSIM, Fang Aili, Haucomm, Iepeulas,
JimScott, Josel777, Knordlun, Moreschi, PVDcoating, Primarscources, Pz-Poland, ScatmanCrothers, SiobhanHansa, Slashme, Smack, Some standardized
rigour, Sonjaaa, Testingeq, TheBendster, Tsiaojian lee, Verdatum, Vsmith, Wizard191, Yettie0711, 40 anonymous edits
Atomic layer deposition Source: Contributors: Barticus88, Businessman332211,
Chandlerbingco, Dual Freq, Eimell, Frap, Gene Nygaard, Gjmulhol, Happyjsue, Kelly Martin, Lostdrone, Milehighmounty, Pearle, Poppy, RJFJR,
Racklever, Radagast83, Smack, Speedoflightning, Teryx, Vuo, WikHead, 朝彦, 49 anonymous edits
Molecular beam epitaxy Source: Contributors: 12singa, Asdfsafsa, Benjaminshi, Bryan
Derksen, Bungo77, Chaiken, Chem-awb, Debussy Agutter, Editore99, Flynn475, Gene Nygaard, Headbomb, Heron, Jaraalbe, Jared81, Jezzerk,
Joshuajohnlee, JustinWick, Kajit, Lights, Liveste, LorenzoB, MER-C, Mark Yen, Mattopia, Michael Hardy, Mion, Nashikawa, ONUnicorn, Ojigiri,
Oysterman1, Pahidla, Pdaskanu, Phudga, Pinktulip, Polyparadigm, Sabih omar, Sewebster, Shaddack, Smack, Vitaleyes, WulfTheSaxon, 47 anonymous
Czochralski process Source: Contributors: 10987sa, [email protected], Ancheta Wis, Andy
Dingley, AnnaP, Bantman, Bryan Derksen, Closedmouth, Darrien, Dgrant, Emesee, Giftlite, Guillom, Guroadrunner, Heron, Hooperbloob, Jaraalbe,
Jpgordon, Jrockley, Karlhahn, Kukini, Listowy, Looxix, Lzur, Maury Markowitz, Maximus Rex, Mr0t1633, Murphyjd, Nashikawa, Oleg Alexandrov,
Plattopus, Rmhermen, Robchurch, Robofish, Sabih omar, Sam Hocevar, SeanMack, Sjschen, Srleffler, Tetracube, The1physicist, Twisp, Valerychani, Van
helsing, Warut, 58 anonymous edits
Plasma ashing Source: Contributors:, Abdull, Alsocal, Arnowaschk, Art Carlson,
ChemGardener, Conversion script, Hooperbloob, Icairns, Krash, Pmetzger, Slick514, Smack, Stevegiacomelli, Xapht, 9 anonymous edits
Rapid thermal processing Source: Contributors: Allwin21, Chaser, ChemGardener,
Drnathanfurious, Irene Ringworm, Mac, Matt.whitby, Perceval, Physchim62, Radagast83, Sonoma-rich, Tregoweth, 33 anonymous edits
Furnace anneal Source: Contributors: A2Kafir, Alynna Kasmira, Amadeust, Amalas, Aranel,
Duk, Hooperbloob, Rmhermen, Toffile, 3 anonymous edits
Ion implantation Source: Contributors: Afluegel, Ahoerstemeier, Alai, Andrei Liutec,
Bluemoose, Bobblewik, CharlesC, Chuckiesdad, Conscious, Conversion script, Cyferz, Darrien, Dschwen, Duk, Eirikr, FSIM, Gaius Cornelius, Guillom,
Hike395, Hooperbloob, Irene Ringworm, Kkmurray, Knordlun, Lommer, Michael Hardy, Olof, Phil Holmes, Polyparadigm, Pungh0Li0, Reddi, Scottfisher,
Sergio.ballestrero, Shaddack, SimonP, Skippyfr, Smack, Sonoma-rich, TheBendster, Tom verbeure, Wik, Wizardman, 60 anonymous edits
Etching (microfabrication) Source: Contributors: Allwin21, ChemGardener, Dollhous,
Drnathanfurious, Dspark76, Editore99, Gene Nygaard, Guillom, Iepeulas, Jdwest32, Mac, Mgordon42, MrKIA11, Rhadamante, Rich257, Sleigh, Smack,
Thermochap, Twisp, Wizard191, 13 anonymous edits
Dry etching Source: Contributors: Altenmann, Bosone, ChemGardener, Coffee, Daniel Newby,
DeadEyeArrow, Dspark76, Hooperbloob, Iepeulas, Light current, Radagast83, Rhadamante, Shamiryan, Solejheyen, Twisp, 19 anonymous edits
Epitaxy Source: Contributors: Ahoerstemeier, AmiDaniel, Antikon, BabuBhatt, BrokenSegue,
Cacycle, Cantus, CyrilB, DMTagatac, Debussy Agutter, Dimidola, Dori, Editore99, Eequor, Gaius Cornelius, Ghepeu, J. Finkelstein, Jaraalbe, Jarry1250,
Lindvaln, MER-C, Mac, Mayriounette, Mdsam2, Mild Bill Hiccup, Nabla, NoahJD, Nunh-huh, Oxymoron83, Pathaksandeep, Pinktulip, Rich Farmbrough,
Robin S, Sabih omar, SallyForth123, Shadowjams, Simongar, Smack, Snafflekid, Spiritia, Srleffler, Stevenj, TastyPoutine, Tetracube, Tomgally,
Wavelength, 39 anonymous edits
Photolithography Source: Contributors: Abardea, Abmfg, Altenmann, Amit A., Anatoly.bourov,
Anwar saadat, Atlant, Barticus88, Bourdillona, Caco de vidro, Chaiken, Citruswinter, Citynoise, Commander Nemet, Conical Johnson, Conversion script,
D Thong, Ddawson, Deglr6328, Devanney, Dinging, DinkY2K, Dmccreary, Dmn, Donarreiskoffer, DrTorstenHenning, Duk, EdH, Editore99, Egil, Eirikr,
Everyguy, FSIM, FindEngine, FocalPoint, Gaius Cornelius, Glengarry, Gracefool, Gresszilla, Guiding light, Guillom, J. Finkelstein, JeremyA, Jondel,
Kazkaskazkasako, Ketsuekigata, Krash, Kwixtartpahtee, LithoGuy, Lupus00, Lysdexia, Matt Britt, Maximus Rex, Melderman, Mindmatrix, Mrh30, Oleg
Alexandrov, Pietervanpelt, Plantsurfer, Ray Van De Walker, Rdsmith4, Redlen, Rich Farmbrough, Rmhermen, Robertvan1, ShaunL, Shufengbai, Smack,
Srleffler, Stokerm, Striderx, Subversive.sound, The wub, The1physicist, TheBendster, Twisp, Urvabara, Usubikingaddict, Valermos, Wca42, Willemo,
Wizard191, Xoneca, Zeimusu, 119 anonymous edits
Thermal oxidation Source: Contributors: Anandbhushan, Auntof6, Beetstra, Berserkerus,
Guillom, KrlosT, KryptoCleric, Rossheth, Smack, Twisp, Yonatan, 11 anonymous edits
Wafer testing Source: Contributors: Ancheta Wis, Avdgeijn, BC Mack, David Haslam, Divajoni,
DragonHawk, Dspark76, Duk, Nelson50, Paulcris, Philopp, Radagast83, Rex.sandbach, Rmhermen, Tom verbeure, Wfraga, Wmwmurray, 10 anonymous
Wafer prober Source: Contributors: Alan Liefting, Amalas, Brad101, JubalHarshaw, Moe
Epsilon, Radagast83, Rex.sandbach, Robofish, Scm83x, Triplestop, Wmwmurray, 13 anonymous edits
Non- contact wafer testing Source: Contributors: CIreland, Wfraga
Article Sources and Contributors
Die preparation Source: Contributors: Amalas, Arodrig6, Dicklyon, Duk, Graham87,
Hooperbloob, Keilana, Kubigula, LokiClock, Mattisse, Meisterkoch, Perfecto, Radagast83, Redquark, Rmhermen, Tom verbeure, Wease459, 4 anonymous
Integrated circuit packaging Source: Contributors: Abdull, Altenmann, Amalas, Amikake3,
BenFrantzDale, Bissinger, CyrilB, DarkFalls, Duk, E Wing, Hooperbloob, Kopp.dave, Laudak, Loren.wilton, McCart42, Mellery, Michael Hardy, Sergei
Frolov, Twisp, Worky worky, Xinghuei, 19 anonymous edits
Die attachment Source: Contributors: Abdull, Adrger, Atlant, CyrilB, Duk, Hooperbloob,
Jehochman, Meisterkoch, Pyrop, Remuel, Snafflekid, Tom verbeure, 2 anonymous edits
Wire bonding Source: Contributors: Al Lemos, Altenmann, CyrilB, Drichards2, Duk,
Eigenpirate, Gene Nygaard, Henry Delforn, Hooperbloob, Inductiveload, JohnOwens, Manfreeed, Paululrich, Pseudomoi, Retired username, Shaddack,
Sommacal Alfonso, Spartaz, Srleffler, Twirligig, Twisp, 12 anonymous edits
Flip chip Source: Contributors: Adrger, CryptoDerk, Dancter, Danield101, Dysprosia,
Edgarrabbit, ElectraFlarefire, EoGuy, Glloq, Hellbus, Hooperbloob, Jehochman, Jnc, Josh Parris, Julesd, Khym Chanur, Kinema, Maury Markowitz, Okto8,
Omegatron, Parikshit Narkhede, Pseudomoi, RJFJR, RTC, Rmhermen, Secretlondon, SiobhanHansa, Toresbe, Twisp, ZyMOS, 33 anonymous edits
Quilt packaging Source: Contributors: Ilikefood, Kopp.dave, TheMolecularMan, Waggers,
Whpq, 12 anonymous edits
Integrated circuit encapsulation Source: Contributors: Altenmann, Amalas, BenFrantzDale,
Can't sleep, clown will eat me, CyrilB, Duk, Hooperbloob, Mellery, Rich Farmbrough, Thehelpfulone, Toffile, Twisp, 7 anonymous edits
Plating Source: Contributors: A.M.962, Altzinn, Anton Rakitskiy, Ayudante, BenFrantzDale,
BorgQueen, Bretterofer, Ceramic2metal, Chris the speller, Ckelloug, DV8 2XL, Diapason8, Duk, Electron9, Eliz81, EvanGrim, Fstep, Gene Nygaard,
Gzuckier, Haegis9, Henrygb, Hobbes.hutabarat, Hooperbloob, I I K I I, ISC PB, IceCreamAntisocial, Iepeulas, J. Finkelstein, Jack Bethune, KEKEC,
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Stone, Tevildo, Tomgally, TonyGerillo, Una Smith, Wbrameld, Welsh, Wizard191, 113 anonymous edits
Semiconductor fabrication plant Source: Contributors: 10987sa, Amalas, And4e, Biblbroks,
Booyabazooka, Computerjoe, David Haslam, Dddrewski, Denni, Dicklyon, Do it, EarthCat, Enblixt, Exeunt, Fernvale, IIXII, Jdawson76, Kilmer-san, Mac,
Mainstream Nerd, Mellery, Museo8bits, Ng.j, Pan Dan, Paulsweden, Postdlf, RJFJR, Ramu50, Raryel, Sahrin, SarekOfVulcan, Skynxnex, Sysys,
Wmwmurray, 23 anonymous edits
Lights out (manufacturing) Source: Contributors: GVnayR, J04n, Monkeyblue, Âme Errante, 1
anonymous edits
Foundry model Source: Contributors: AK Auto, Aaronmz, AlistairMcMillan, Alvis, Andrewa,
Bk2204, Bogsat, Brentdax, Canderson7, CanisRufus, Computerjoe, Dicklyon, Duk, Exeunt, Fernvale, Hooperbloob, Jeepday, Jeff3000, Jersyko,
Jgruszynski, Khalid hassani, Melchoir, Moxfyre, Nonstopdrivel, Pearle, Piperh, RJFJR, RedWolf, SarekOfVulcan, SchmuckyTheCat, Sietse Snel, 11
anonymous edits
Advanced Silicon Etch Source: Contributors: Deville, DrShort, Dugwiki, Gail, Ka Faraq Gatri,
KristianMolhave, Mboverload, Paxse, Reedy, Rich Farmbrough, Skapur, Svenski994, Twisp, 6 anonymous edits
Buffered oxide etch Source: Contributors: Dspark76, Dzheezus, Gene Nygaard, Rhadamante,
Sarosh, Stephenb, Stormbay, 4 anonymous edits
Deep reactive- ion etching Source: Contributors: Barticus88, BernardKevin, Bobblewik,
Colonies Chris, CriX, Dumb&lerned, Faradayplank, GeeJo, Kelly Martin, Krash, Markbegbie, Markus Kuhn, Matt Britt, Phactotum, Red Thunder,
Rhadamante, SamiF, Shaddack, Smack, Sobczaks, Twisp, V8rik, 17 anonymous edits
Reactive- ion etching Source: Contributors: A2Kafir, Altenmann, Ameyabapat, Art Carlson,
Azhyd, BernardKevin, Dollhous, Eirikr, Iepeulas, Jschultz, Lone Skeptic, Matt Britt, Quale, Rich257, Rmhermen, Smack, Twisp, Zoicon5, 21 anonymous
Airgap Source: Contributors: Gene Nygaard, Henriok, Hughcharlesparker, J.delanoy, JaGa,
Jyothymj, KBi, Rwwww, Undead warrior, Waggers, 4 anonymous edits
B- staging Source: Contributors: Bissinger, Jehochman, Retired username, SimonP, 1
anonymous edits
Ball bonding Source: Contributors: Adrger, Coro, DMG413, Duk, Hooperbloob, Sam Hocevar,
Shaddack, Srleffler, Underpants, 10 anonymous edits
Barrier metal Source: Contributors: Polyparadigm, Shaddack, 7 anonymous edits
Borophosphosilicate glass Source: Contributors: Afluegel, BC Mack, Bryan Derksen,
Cepheiden, Darrien, Duk, Elkman, Jdrewitt, Shaddack, Spacepotato, Taqi Haider, 2 anonymous edits
Capacitance voltage profiling Source: Contributors: BartG, Bctwriter, Bissinger, Brews ohare,
Ferritecore, Headbomb, Hooperbloob, Mirkov, Oli Filth, Rajah, Retired username, 3 anonymous edits
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Alfred Y. Cho Source: Contributors: Archanamiya, Binksternet, Buhuzu, Etacar11, Hebrides,
JLaTondre, Jaraalbe, Jiuguang Wang, Joan kingston, Katharineamy, Ketiltrout, Needruns2009, Osund, PDH, Pinktulip, Rettetast, Richard Arthur Norton
(1958- ), Ser Amantio di Nicolao, Snowolf, Strangerer, WingkeeLEE, 9 anonymous edits
Cleanroom Source: Contributors: 75th Trombone, ABCD, Aaronmz, Accurrent, Adrian J. Hunter,
Ahoerstemeier, [email protected], Allan McInnes, Andycjp, Angela, Anshuk, Anthony5429, Argon233, AttishOculus, Axeman89, Beetstra, Bobblewik,
Capecodeph, Cathald, Csari, Deathawk, Deglr6328, DrTorstenHenning, Driscolj, Drooling Sheep, Duk, Dysprosia, Edcolins, Elkman, Environ1561, Gaius
Cornelius, Gbellet, Gene Nygaard, Generala, Haham hanuka, Hankwang, Hismattness, Hqb, IReceivedDeathThreats, Iest5005, Interiot, JFreeman, JaGa,
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anonymous edits
Coining, Inc. Source: Contributors: Bogeythecat, Debresser, Dicklyon, Laudak, Wperdue, 2
anonymous edits
Article Sources and Contributors
Dark current spectroscopy Source: Contributors: Carlossuarez46, Jeodesic, Jetzzfan,
RHaworth, Stephenb
Deal- Grove model Source: Contributors: Khonshu7, Seidenstud, Smack, 11 anonymous edits
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Haslam, Davidbatet, Hooperbloob, Johncruise, Myhister, Old Moonraker, Sergivs-en, Toffile, 4 anonymous edits
Doping (semiconductor) Source: Contributors: 88melh, ARTE, Adeut85, Adriaan90,
Ahoerstemeier, Alynna Kasmira, Arjun01, As14288, Bergsten, Bobo192, Brews ohare, Cruccone, Cutler, Cuvette, David Haslam, Dcljr, Dspark76, Dual
Freq, ElectraFlarefire, Flyskippy1, Gmazeroff, Guillom, Headbomb, Hooperbloob, Jcarroll, Jcwf, Karolkalna, Laurascudder, Mac, Mako098765, Michael
Hardy, Mpatel, NawlinWiki, Nilzxx, Peter bertok, Phil Holmes, Polyparadigm, Rajkapoor1988, Sfahey, Shaddack, Sjrosen, Slicing, Snafflekid,
SophisticatedPrimate, Tiptoety, Turn On My Mike, Unmitigated Success, Wazzizi, Wutwatwot, 42 anonymous edits
Electron beam induced current Source: Contributors: Andrea Cioffi, Bochica, Cm the p,
Dicklyon, Elonka, Jcwf, Malcolma, Sbyrnes321, Skier Dude, 11 anonymous edits
Epiwafer Source: Contributors: DS1953, Dialectric, Pinktulip, 3 anonymous edits
Evaporation (deposition) Source: Contributors: Cepheiden, DNova, FSIM, Gene Nygaard,
GregRM, Guillom, Onopearls, Patinal, Smack, TheBendster, WarthogDemon, 11 anonymous edits
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MARQUIS111, Mabahj, Maury Markowitz, Mbutts, Melchoir, Museo8bits, Night Gyr, Nonstopdrivel, Olmaltr, Phil Bastian, RJFJR, RevRagnarok, Sam916,
SarekOfVulcan, Silvestre Zabala, TheGiantHogweed, Timwi, Vsabio, 46 anonymous edits
Finetech Source: Contributors: Chowbok, Greenshed, Iridescent, Mcmullen writes, PaulHanson,
Rcawsey, Tequalizer eng, 13 anonymous edits
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Azboh20, Blake-, Blechnic, Cm the p, Comparat, D6, Dicklyon, DrMikeF, EdC2, Eno-ja, Gcgazzadi, Gene Nygaard, Gmhorn, Guiding light, Ion13beam,
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Shadowsong, Pascal666, Pavithran, 2 anonymous edits
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anonymous edits
Hardmask Source: Contributors: Guiding light, KathrynLybarger, 1 anonymous edits
Health hazards in semiconductor manufacturing occupations Source: Contributors:
Altenmann, Brewcrewer, Fabrictramp, Gabriel1907, Hence Jewish Anderstein
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current, Nihonjoe, Pearle, Skarebo, Tangotango,, 21 anonymous edits
Ion Beam Mixing Source: Contributors: Jarry1250, Lynnrice, PeaceNT, Redvers, Rich
Farmbrough, Rjwilmsi, Swpb, Woohookitty, 4 anonymous edits
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Shaddack, TaintedMustard, Vsmith, Yermih, 15 anonymous edits
Ion beam lithography Source: Contributors: Betacommand, Hersfold, Malcolma, Quetsilquatl,
Sabih omar, Semachin, 1 anonymous edits
Laser trimming Source: Contributors: Adrian Banerter, Altaphon, Atlant, CFMWiki1, Duk,
Katiemurphy1, Peter Lenk, Several Times, 12 anonymous edits
Lift- off (microtechnology) Source: Contributors: Ninorota, Twisp, 2 anonymous edits
Low temperature co- fired ceramic Source: Contributors: Adrian Banerter, Am088, Caulde,
Chriseandrews, David451, Dekisugi, Emersoni, Fredvanner, Freedomlives, Ilabadie, Katiemurphy1, Malcolma, Ollagnij, Pissant, Repliedthemockturtle,
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MOSIS Source: Contributors: Abdull, Dbouldin, Delirium, Ilovetacos, Jgruszynski,
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Metal- induced crystallization Source: Contributors: Joe Decker, Joriki, MER-C, Marwan123,
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Metalorganic chemical vapor deposition Source: Contributors: Anetode, Koozie79, Smack, 2
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Microfabrication Source: Contributors: Altenmann, Axeman89, Barticus88, Batna05,
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Multi- project wafer service Source: Contributors: Altenmann, Artaxiad, Dbouldin,
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Negative bias temperature instability Source: Contributors: 1ForTheMoney, DmitTrix,
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Plasma etching Source: Contributors: Allwin21, Altenmann, Antiliby, Astronouth7303,
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Plasma- immersion ion implantation Source: Contributors: Cyferz, Dhawalmahajan,
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Process design kit Source: Contributors: Ihcoyc, Malcolma, Rich Farmbrough, Steven Hepting,
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Pulsed laser deposition Source: Contributors: 7segment, Adam4445, Audiodude, Charles
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Shallow trench isolation Source: Contributors: Gwernol, Mainstream Nerd, Naturalion,
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Silicate glass Source: Contributors: Afluegel, BC Mack, Darrien, Duk, Epolk, Jdrewitt,
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Silicon on sapphire Source: Contributors: Akulkis, Barticus88, Bobblewik, Chowbok,
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Smart Cut Source: Contributors: Miguelzinho, Page Up, Twisp
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Spreading Resistance Profiling Source: Contributors: Chuckiesdad, GrammarHammer 32,
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Austintexas007, Balloonguy, Don Mattox, Geologyguy, Golbez, GreysAnatomy, Iepeulas, Kbwikipedia, Keeper76, MBirkholz, Materialscientist, Mattopia,
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Substrate mapping Source: Contributors: Avdgeijn, P. Zwegers, Pavium
Tetrakis(dimethylamido)titanium Source: Contributors: Axiosaurus, Chem-awb, Edgar181,
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Three- dimensional integrated circuit Source: Contributors: Augustojv, Dicklyon,
Gretchenpatti, Oleg Alexandrov, Philjcb, Rich Farmbrough, Toffile, Twisp, 8 anonymous edits
Through- silicon via Source: Contributors: Gretchenpatti, MER-C, Oleg Alexandrov, Tosaka1, 9
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Titanium nitride Source: Contributors: Albmont, Albris, Awyllie, Beetstra, Berkay0652,
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Trimethylgallium Source: Contributors: Axiosaurus, BENCH 420, Beetstra, Benjah-bmm27,
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Vapour phase decomposition Source: Contributors: Johnpseudo, 3 anonymous edits
Wafer (electronics) Source: Contributors: 10987sa, 21655, 6re, Alan Liefting, Altenmann,
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Wafer fabrication Source: Contributors: Artier, Asparagus, Bobblewik, CanisRufus, Chfowler,
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Wayward, 9 anonymous edits
Wafer- scale integration Source: Contributors: Ceyockey, Cmdrjameson, Dyl, Eric-Wester,
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