Structure for Packaging, Integrating and Reusing IP within Tool
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Structure for Packaging, Integrating and Reusing IP within Tool Flows John A. Swanson Senior Manager Synopsys Solutions Group What is SPIRIT SPIRIT is a consortium consisting of leading EDA, IP and SoC integrators aiming at increasing the efficiency of SoC integration by defining new standards for support in EDA environments and IP packaging © 2005 Synopsys, Inc. (2) Why SPIRIT The industry needs a standard mechanism for the importing of IP into any EDA tooling environment, and for describing IP in such a manner that IP integration can be automated © 2005 Synopsys, Inc. (3) The Two SPIRIT Standards IP meta-data description. The meta-data standard will create a common way to describe IP, compatible with automated integration techniques and enabling integrators to use IP from multiple sources with SPIRIT-compliant tools. IP tool integration API. The tool integration API will provide a standard method for linking tools into an IP framework, enabling a more flexible, optimized development environment. SPIRIT-compliant tools will be able to interpret, configure, integrate and manipulate IP blocks that comply with the proposed IP meta-data description. © 2005 Synopsys, Inc. (4) A Closer Look at SPIRIT SOC Design Design Flows IP Views RTL (VHDL, Verilog) TLM (SystemC, SystemVerilog) Documentation (HW, eSW) Device Drivers © 2005 Synopsys, Inc. (5) IP Tools Rules Knowledge A Closer Look at SPIRIT Design Capture SOC Design Address Map Interfaces Registers Protocol Bus width Design Design Implementation Flows Engine IP Views RTL (VHDL, Verilog) TLM (SystemC, SystemVerilog) Documentation (HW, eSW) Device Drivers IP Tools Rules Knowledge High Speed OCB System Bus Memory Bridge Peripheral PeripheralOCB Bus GPIO © 2005 Synopsys, Inc. (6) Interface IP RAP Interrupt Controller A Closer Look at SPIRIT Meta-Data XML Configurations and Generators Configurable IP Architectural point-tools SOC Design Address Map Interfaces Registers Protocol Bus width Interface Configuration Component Configuration Memory Map Design Design Implementation Flows Engine IP Views RTL (VHDL, Verilog) TLM (SystemC, SystemVerilog) Documentation (HW, eSW) Device Drivers IP Configurator Design Capture IP Tools IP Generator Rules Knowledge Interface IP High Speed OCB System Bus Memory Bridge Bus Generation Peripheral PeripheralOCB Bus Clock Generation Memory Control Driver Generation GPIO Generator Chain RAP Interrupt Controller RTL netlister eSW Build Instrumentation Design Checkers SPIRIT SPIRIT Schema Schema and and Generator Generator Interface Interface © 2005 Synopsys, Inc. (7) What I presented last time… Revision Date: June 7th 2004 SPIRIT Schedule (Detail) • New Member Sign-Up: Ongoing! – Reviewing and contributing members • SPIRIT 1.0: Scope – RTL / Loose Generators – Proposed Standard (Full Member Review): NOW! – Validated Public Release: Early Q4, 2004 • • SPIRIT 2.0: Scope – ESL / Verification / Tight Generators – Requirements: Q3 2004 – Development: Q4 2004 / Q1 2005 – Review and Release: Q2 / Q3 2005 SPIRIT deliverables roll into major industry standards body – Presented as a validated, defacto industry standard 14 © 2005 Synopsys, Inc. (8) Quick Update • SPIRIT V1.0 was released at IP-SOC in December 2004 Specification at: http://www.spiritconsortium.org • SPIRIT V1.1 is in development Extensions to support flow into synthesis • SPIRIT V2.0 is also in development Verification Technical Working Group ESL Technical Working Group Schema Technical Working Group • Development plans can also be downloaded from: http://www.spiritconsortium.org © 2005 Synopsys, Inc. (9) Verification Working Group VWG Charter • Develop, validate and deliver enhancements to the SPIRIT V1.0 XML schema needed to support the verification of IP-based designs. • Support the construction of test benches containing relevant configurable verification IP and associated test files needed to support the verification of IP based designs. • Describe the type of verification environments in which the verification IP can be used to support the verification of IP based designs. 3 © 2005 Synopsys, Inc. (10) Verification Working Group VWG Development process • Ensure Schema backward compatibility – Only change schema when necessary – Each schema change proposal reviewed by SWG and has to follow a strict process • For each requirement, follow 2 step process – Problem description • Example illustrating the problem • Solutions and Limitations in current schema – Problem solution • Schema extension proposal (on top of SPIRIT 1.0) • Example (xml) based on the schema proposal • Phase development – Phase1: Keep each TWG (EWG, VWG, SWG) orthogonal – Phase2: Merge TWG (EWG, VWG, SWG) schema 9 © 2005 Synopsys, Inc. (11) ESL Working Group ESL Charter • Goal – Develop, validate and deliver XML schema, documentation and examples to describe configurable system-design models so that full SoC design models can be automatically built and run. • General scope – Enhance SPIRIT 1.0 to support SoC Designs modelling (HW and SW) at various transactional levels (TLM). 3 © 2005 Synopsys, Inc. (12) ESL Working Group EWG Development process • Ensure Schema backward compatibility – Only change schema when necessary – Each schema change proposal reviewed by SWG and has to follow a strict process • For each requirement, follow 2 step process – Problem description • Example illustrating the problem • Solutions and Limitations in current schema – Problem solution • Schema extension proposal (on top of SPIRIT 1.0) • Example (xml) based on the schema proposal • Phase development – Phase1: Keep each TWG (EWG, VWG, SWG) orthogonal – Phase2: Merge TWG (EWG, VWG, SWG) schema 8 © 2005 Synopsys, Inc. (13) coreAssembler Validating the Standard with IP from Multiple Vendors Galaxy Discovery DFT Compiler VCS VCS Vera Vera LEDA LEDA Magellan Magellan Formality Formality ESP ESP SystemVerilog // SystemC SystemC SystemVerilog DesignWare Verification Verification IP IP DesignWare DesignWare Library Library & & Cores Cores DesignWare Milkyway Milkyway Physical Physical Compiler Compiler Astro Astro Star-RCXT StarStar-RCXT DesignWare Cores System System Studio Studio Saber Saber JupiterXT JupiterXT Floorplan Floorplan Compiler Compiler PrimeTime SI SI PrimeTime DesignWare AMBA IP Power Compiler Module Compiler Design Design Compiler Compiler NanoSim NanoSim HSPICE HSPICE Hercules Hercules DesignWare USB HSOTG ARM926DJS Proteus Proteus/ /InPhase InPhase CATS CATS Taurus Taurus Aurora Aurora Raphael Raphael SiVL/ / IC SiVL SiVL/ ICWorkbench Workbench Your IP Virtual VirtualStepper Stepper Design DesignServices Services System AHBA AHB Bus DesignWare TSMC 90nm Library Bridge GPIO SPIRIT IP © 2005 Synopsys, Inc. (14) Philips IP Peripheral AMBA APB Bus DesignWare IP Your IP ST Memory RAP Interrupt Controller IP Subsystem coreAssembler Thank You!
