HW D2: Sequential Logic, Counters, Debounce
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HW D2: Sequential Logic, Counters, Debounce
REV 3; July 18, 2010
Contents
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1
Flop Reminder: edge recorder (2 points)
1
2
Debouncers (4 points)
2.1 SPST (2 points) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 SPDT (2 points) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2
2
3
Counter (3 points)
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4
Applying an IC Counter (3 pts, total)
4.1 Crummy: async clear (1 point) . . . . . . . . . . . . . . . . . . . . . .
4.2 Good: fully synchronous divide-by-eleven (2 points, total) . . . . . . . .
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3
3
5
Timing Diagram of Synchronous vs Asynchronous Schemes (2 points)
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6
Reaction Timer (5 points)
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Flop Reminder: edge recorder (2 points)
Make a circuit that lights an LED when a rising edge occurs on a signal named TRIG. The LED should stay lit till someone
presses a pushbutton. The pushbutton should be effective even if TRIG happens to stay high.
HW D2: Sequential Logic, Counters, Debounce
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2.1
2
Debouncers (4 points)
SPST (2 points)
Show how to debounce a switch of the single-pole, single-throw form shown below:
Figure 1: Debouncer for SPST switch
Please show two ways.
2.2
SPDT (2 points)
Show how to debounce a switch of the single-pole, double-throw form shown below:
Figure 2: Debouncer for SPDT switch
Please show two ways (and please don’t duplicate a method you showed in part a).
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Counter (3 points)
Increment the counter (i.e., clock it) once each time button A or is pushed or switch B is moved to the right. Clear the counter
when button CLEARIT is pushed. Debounce only as needed.
Figure 3: counter interface problem
HW D2: Sequential Logic, Counters, Debounce
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Applying an IC Counter (3 pts, total)
Figure 4: ’161 IC counter: 4-bit
• If ENT (enable) is not asserted, the counter simply holds its present state;
• CY (carry out) is high if Count = 15, and if ENT is asserted; CY is low otherwise;
• “Synchronous Load”: Data (at the 4 “D” inputs) is loaded into the counter on the next rising edge of the clock if LD* is asserted (low)
You’ll hook this up two ways to count to 11 and then reset back to zero:
4.1 Crummy: async clear (1 point)
Use the asynchronous clear (R) to make a crummy divide-by-eleven counter: (Fill in the timing diagram on the next page to
understand why it’s crummy.)
4.2
Good: fully synchronous divide-by-eleven (2 points, total)
Use the synchronous load (LD*) to make a good divide-by-eleven counter. Make sure all inputs are hooked up appropriately.
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HW D2: Sequential Logic, Counters, Debounce
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4
Timing Diagram of Synchronous vs Asynchronous Schemes (2 points)
In the preceding question, you used both an asynchronous (crummy) method, and a fully-synchronous (good) method. Your
counters, in two cases, ran from zero up, and were to divide by 11. Use the timing diagrams below to show how the sync
version is better than the async. Let your timing diagrams begin near the end of the cycle: at count 9, and show what happens
in the next 4 clock periods.
HW D2: Sequential Logic, Counters, Debounce
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5
Reaction Timer (5 points)
Here is an exercise that lets you design a complete (standalone) device using just counters, logic and flops! The circuit should
let a person test their “reaction time” thus:
• Person A presses a button to start a timer (made with a big counter) and light an LED.
• Person B then presses another button as soon as they see the LED light up and the counter stops and display the reaction
time.
The circuit is complicated by the need to detect whether B has cheated—that is, whether B has hit his button before A. Add
this complication later.
Note that a worked example called ’bullet timer’ does a task much like the one requested here.
Here are some specifications for the circuit, each of which should be added for complete points:
• The “display” will be handled by LCD we’ll use in class which takes up to 16-bits in and shows the equivalent number.
• A pushbutton, A, starts the timing; another pushbutton, B, should stop the timing. You should decide whether to use a
single-throw or double-throw pushbutton (see Ch. 9, §9.04, p. 577, if you’re not sure of this distinction); A also turns on
a green LED (it wants 3mA at 2V), to which the other person is supposed to respond by pressing B.
• You are given a 1.024 MHz oscillator;
• 1 ms display resolution is appropriate for your timer, so you need to decide which counter bits need to be connected to
the display.
• You need to decide how many bits the counter itself needs to be.
• Debounce only where necessary;
• Let a third pushbutton, C, reinitialize the machine. When the C button is pushed, the machine resets the counter, clears
all LEDs and awaits another measurement cycle.
• If person B cheats, hitting his button before A, turn on a RED “cheat” LED.
• If the counter overflows, light a yellow “overflow” LED.