Asynchronous Sequential
Circuits
Synchronous Machines Recap.
 Up
to this point, we only considered synchronous
circuits with a clock to synchronize state changes
 A Mealy machine looks like this:
Inputs
x1
xn
z1 Outputs
zn
CL
Yk … Y1
y1 … yk
Mem
clk

Clock makes many things nice:
»
»
»
»
Between clock pulses, yi Yi
Multiple input changes are OK
Static hazards are dealt with
Variable delay paths through CL are fine
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Asynchronous Machine Model
 An
asynchronous machine model is similar:
Inputs
x1
xn
CL
y1 … yk

z1 Outputs
zn
Yk … Y1
Clocked devices are replaced with delay elements
» Now we need to consider xi and yi as the total state



For unchanging input state, if yi=Yi 8 1· i· k, then
the machine is in a stable state.
Input changes cause unstable states
We assume no subsequent input changes until
machine is in a stable state, again (fundamental mode)
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Hazards
 While
hazards are things to be avoided, in general,
they are especially important when dealing with
asynchronous machines
 There
are two classes of hazards:
» Static hazards
– A static hazard is the possibility of a circuit’s output producing a
glitch when we would expect it remain constant.
» Dynamic hazards
– A dynamic hazard is the possibility of a circuit’s output producing
multiple changes in logic level when only one is expected.
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Static Hazards
 Consider
the following circuit:
Assume every gate has unit delay. If X=Z=1 and Y
goes from 10, then the following timing diagram
can be drawn:
Note how F has a glitch on it
although, logically, the function
F=XY’+YZ should not have
changed value for X=Z=1.
1-5 - David Zar - 3/30/2010
Finding Static Hazards
 How
can we find static hazards, in general?
» Let’s look at a K-map for the circuit F=XY’+YZ
X YZ 00
01
0
1
11
10
1
1
1
1
The hazard comes about for if we move from one product
term to the other we could move through a minterm that
is a zero (such as X’Y’Z or XYZ’). This is what causes the
glitch.
» For SOP circuits, look for adjacent product terms that do
not have minterms in common.
» For POS circuits, look for adjacent sum terms that do not
have maxterms in common.
1-6 - David Zar - 3/30/2010
Eliminating Static Hazards
 Now
that we found the problem, can we eliminate
it?
 Yes, since we can add additional product (sum)
terms to cover the areas where we have a potential
hazard.
» For the previous example, we can simply cover XY’Z and
XYZ
X YZ 00
01
0
1
11
10
1
1
1
1
Now the function changes to Fhf=XY’+YZ +XZ which is
functionally equivalent but hazard-free.
1-7 - David Zar - 3/30/2010
Dynamic Hazards
 Dynamic
hazards arise when gates have different
delays and there are multiple paths through these
gates to the output.
 In
two-level circuits, you can never have a dynamic
hazard if a variable and its complement are not
connected to the same first-level gate.
 The
problem of detecting dynamic hazards in multilevel circuits is harder than static hazards.
 If
all static hazards are eliminated, however, no
dynamic hazards will remain
1-8 - David Zar - 3/30/2010
Fundamental Mode Design
 Let’s
design a gated-clock circuit!
 Remember, only one input can change at a time
(fundamental mode) and we have two inputs: C and
G (C is a periodic clock signal and G is a gate signal)
 We can draw a timing diagram of what the output
(Z) should look like in time
 For
synchronous machines, we build a state-table;
for asynchronous machines we build a flow-table
» Entries in a flow-table are the state and the output
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Primitive Flow Table
A
primitive flow table is a flow table where
» Only one stable state per row
» Outputs specified only for stable states
 For
example, using our timing diagram for the gated
clock circuit, we can build a primitive flow table.
 Label each state/output set with a different number.
These will become the stable states in our primitive
flow table.
1-10 - David Zar - 3/30/2010
Gated Clock Primitive Flow Table
 Here
is the resulting primitive flow table
 From
this, we can draw merger graphs and tables as
we’ve done for synchronous FSMs
1

2


3
24

24
4
24
05
05
X
X
05
24


0
1
2
3
4
5
1-11 - David Zar - 3/30/2010
0
2
5

1
4
3
Reduced Flow Table
 In
the same way we reduce state tables, we find a
reduced flow table.
 From the merger table/graph we see the maxcompatibles are (012)(13)(345). From these, it’s
obvious that a closed cover is (012)(345).
 If we assign state A=(012) and state B=(345)
 Now
we perform state assignment. With two states,
this is trivial: let A=0, B=1
 We also need to assign the outputs! Choose them
wisely (to keep output equations minimal)
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Implementing Asynchronous Machines
 With
the reduced flow table complete with state
assignments and outputs assigned, we can write
output and next-state equations using Boolean
reduction techniques we already know
y CG 00
01
11
10
1
1
11
10
1
1
0
 We
must ensure a hazard-free
design! So Y=c’G+yC+yG
1
Z=yC
y CG 00
01
0
1
1
1
Y=c’G+yC
1-13 - David Zar - 3/30/2010
Implementation Procedure (Summary)
 The
general procedure to implement an asynchronous
state machine:
» Form primitive flow table
» Reduce primitive flow table to minimum number of stable
states (reduced flow table)
» Assign internal state variables (state assignment)
» Derive excitation and output functions
– Minimize
– But be hazard-free
» Draw circuit diagram/implement with gates
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State Assignment and Races
 For
asynchronous machines, state assignment is more difficult
than for synchronous machines
» Sometimes, more than d log2 ne internal state variables are required
In state y1y2=00 x1x2=01 stable then x20
y1y2=00 x1x2=00 unstable for y1y2=11
Unstable for we could go to state 01 or 10 first!
A
condition where we have multiple internal state variables
change is called a race
» Critical races could put us in the in the wrong stable state
» Noncritical races put us in the correct stable state, eventually
» Cycles are a sequence of unstable states
 The
race, above, is noncritical for going to state 01 or 10 will
still get us to state 11 (the desired state) with the inputs stable.
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Critical Races and Cycles
In state y1y2=11 x1x2=00 stable then x21
y1y2=11 x1x2=01 unstable for y1y2=00
Unstable for we could go to state 10 and stop!
 The
race, above, is critical for going to state 10 will stop us in
the wrong state.
 If we consider state y1y2=01 x1x2=10 stable then x21
»
»
»
»
y1y2=01 x1x2=11 unstable for y1y2=11
y1y2=11 x1x2=11 unstable for y1y2=10
y1y2=10 x1x2=11 stable
This is a cycle since we sequenced through multiple states to become
stable. (Not necessarily a problem!)
 We
cannot tolerate critical races, however. We must do
something to eliminate the critical races
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Eliminating Critical Races
 We
can eliminate the critical race by inserting a cycle in
column 01:
)
 Another
alternative is to change the state assignment:
)
 NOTE:
There is still a noncritical race in column 00 and a cycle
in column 11.
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Transition Diagrams
 Dealing
with these state assignment issues is helped
by a transition diagram.
a
b
)
c
 Ideally,
we’d like all related states to differ by one bit.
» Not possible for above
y1
y2 0
1
a
b
0
1
1-18 - David Zar - 3/30/2010
c
a and c are not adjacent
State Assignment
 Two
general methods for state assignment:
» Add transient state and internal cycles
» Add additional stable states replicating original states
 Adding
a state d:
a
b
d
c
)
y1
y2 0
1
a
b
d
c
0
1
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In general, this may require
additional state bits since we are
increasing the number of states
State Assignment (cont.)
 Replicate
y1
y2 0
1
a
b
c
c
0
1
 Output
stable states:
function must recognize both 10 and 11 as
state c.
 General state replication maps may be drawn. For
example:
y2 \y1y0 00
01
11
10
y2 \y1y0 00
01
11
10
0
a
c
c
d
0
a
b
c
d
1
a
b
b
d
1
c
d
a
d
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Hazards Revisited
 Recall
static and dynamic hazards are functions of the
implementation (i.e. they can be corrected)
 Essential Hazards are functions of the problem
» We must examine individual delays to ensure the hazard
does not cause a malfunction.
Consider this circuit where x has a
much larger delay to Y1 than to Y0
x
CL
y1 … yk
Yk … Y1
» Initially, x1y1y0=000: x1 ) 101; x0 ) 011; x1 ) 110
» Reconsider with delay: x1, Y0 sees 100  1; now Y1 sees 001  1;
then Y0 sees 110 and we’re stable in the wrong state!
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Fixing Essential Hazards
 The
fix:
» Ensure the delay from x to Y1 is small enough or
» Ensure delay from Y0 to y0 is large enough
X
Y0
y0
d tcle < b tclc + b tdc + b tclc = 2b tclc + b tdc
Y1
b tdc > d tcle – 2b tclc
btclc btdc btclc
dtcle
Y0
Y1
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