B ASIC E LEMENTS
Simplified view:
➜ Processor
➜ Main Memory
Computer System Overview
• referred to as real memory or primary memory
• volatile
Operating Systems
Slide 1
Slide 3
➜ I/O modules
• secondary memory devices
2004/S2
• communications equipment
• terminals
➜ System bus
• communication among processors, memory, and I/O
modules
O PERATING S YSTEM
T OP -L EVEL C OMPONENTS
➜ Provides an abstraction layer over the concrete hardware
➜ Allocation of resources
Monitor
• Processor
Keyboard
Floppy
disk drive
Hard
disk drive
Keyboard
controller
Floppy
disk
controller
Hard
disk
controller
• Memory
Slide 2
Slide 4
• I/O devices
➜ Optimisation of resource utilisation
CPU
➜ Protection and Security
Memory
Video
controller
Understanding operating systems therefore requires some
basic understanding of computer systems
B ASIC E LEMENTS
Bus
1
E XAMPLE : L ARGE P ENTIUM S YSTEM
2
E XAMPLE : L ARGE P ENTIUM S YSTEM
Local bus
Cache bus
Level 2
cache
P ROCESSOR R EGISTERS
Memory bus
PCI
bridge
CPU
➜ Data and address registers
Main
memory
• Hold operands of most native machine instructions
• Enable programmer to minimize main-memory references by
optimizing register use
PCI bus
Slide 5
Slide 7
SCSI
USB
Mouse
ISA
bridge
IDE
disk
Graphics
adaptor
Available
PCI slot
• Used by processor to control operating of the processor
Monitor
Keyboard
• user-visible
➜ Control and status registers
• Used by operating-system routines to control the execution
of programs
ISA bus
• Sometimes not accessible by user (architecture dependent)
Modem
Sound
card
Printer
Available
ISA slot
U SER -V ISIBLE R EGISTERS
P ROCESSOR
➜ Fetches intructions from memory, decodes and executes them
➜ May be referenced by machine language instructions
➜ Set of instructions is processor specific
➜ Available to all programs - application programs and system
programs
➜ Instructions include:
Slide 6
➜ Types of registers
✱ load value from memory into register
Slide 8
✱ combine operands from registers or memory
• Address
✱ branch
– Index
– Segment pointer
– Stack pointer
➜ All CPU’s have registers to store
✱ key variables and temporary results
✱ information related to control program execution
P ROCESSOR R EGISTERS
• Data
• Many architectures do not distinguish different types
3
C ONTROL AND S TATUS R EGISTERS
4
I NSTRUCTION F ETCH
C ONTROL
AND
S TATUS R EGISTERS
E XECUTE
➜ Program counter (PC) holds address of the instruction to be
fetched next
➜ Program Counter (PC)
➜ The processor fetches the instruction from memory
• Contains the address of an instruction to be fetched
➜ Program counter is incremented after each fetch
➜ Instruction Register (IR)
Slide 9
AND
Slide 11
• Contains the instruction most recently fetched
➜ Overlapped on modern architectures (pipelining)
➜ Processor Status Word (PSW)
Fetch Cycle
Execute Cycle
Fetch Next
Instruction
Execute
Instruction
• condition codes
• interrupt enable/disable
START
• supervisor/user mode
HALT
I NSTRUCTION R EGISTER
C ONTROL
AND
➜ Fetched instruction is placed in the instruction register
S TATUS R EGISTERS
➜ Types of instructions
➜ Condition Codes or Flags
• Processor-memory
• Bits set by the processor hardware as a result of operations
Slide 10
– transfer data between processor and memory
• Can be accessed by a program but not altered
Slide 12
• Examples
• Processor-I/O
– data transferred to or from a peripheral device
– positive/negative result
– zero
– overflow
• Data processing
– arithmetic or logic operation on data
• Control
– alter sequence of execution
I NSTRUCTION F ETCH AND E XECUTE
5
I NTERACTION BETWEEN P ROCESSOR AND I/O D EVICES
6
I NTERRUPT C YCLE
➀ Fetch next instruction
➁ Execute instruction
I NTERACTION
BETWEEN
P ROCESSOR
AND
I/O D EVICES
➂ Check for interrupt
➃ If no interrupts, fetch the next instruction
➜ CPU much faster than I/O devices
➄ If an interrupt is pending, divert to the interrupt handler
- waiting for I/O operation to finish is inefficient
Slide 13
Slide 15
- not feasible for mouse, keyboard
Fetch Cycle
➜ I/O module sends an interrupt to CPU to signal completion
Execute Cycle
Interrupt Cycle
Interrupts
Disabled
➜ Interrupts normal sequence of execution
START
➜ Interrupts are also used to signal other events
Fetch Next
Instruction
Execute
Instruction
Check for
Interrupt;
Interrupts Process Interrupt
Enabled
HALT
C LASSES
OF I NTERRUPTS
➜ Asynchronous (external) events
• I/O
I NTERRUPT H ANDLER
• Timer
• Hardware failure
Slide 14
Slide 16
➜ Synchronous interrupts or program exceptions
caused by program execution:
➜ A program that determines nature of the interrupt and performs
whatever actions are needed
➜ Control is transferred to this program by the hardware
➜ Generally part of the operating system
• arithmetic overflow
• division by zero
• execute illegal instruction
• reference outside user’s memory space
I NTERRUPT C YCLE
7
C ONTROL F LOW W ITH AND W ITHOUT I NTERRUPTS
8
C ONTROL F LOW W ITH
User
Program
I/O
Program
4
1
I/O
Command
WRITE
AND
User
Program
W ITHOUT I NTERRUPTS
I/O
Program
4
1
WRITE
I/O
Command
User
Program
I/O
Program
4
1
M ULTIPLE I NTERRUPTS
I/O
Command
WRITE
5
Sequential Order:
2a
END
Slide 17
2
*
2b
WRITE
2
5
WRITE
Slide 19
Interrupt
Handler
Interrupt
Handler
➜ Interrupts remain pending until the processor enables interrupts
5
WRITE
➜ After interrupt handler routine completes, the processor checks
for additional interrupts
END
END
3a
*
3
➜ Disable interrupts so processor can complete task
3
3b
WRITE
WRITE
(a) No interrupts
WRITE
(c) Interrupts; long I/O wait
(b) Interrupts; short I/O wait
M ULTIPLE I NTERRUPTS
User Program
Slide 18
➜ Interrupt X occurs
➜ CPU disables all interrupts (only
those with lower priority)
➜ Interrupt handler may enable
interrupts
➜ Interrupt Y occurs
➜ Sequential or nested interrupt
handling
Interrupt
Handler X
M ULTIPLE I NTERRUPTS
Interrupt
Handler Y
Priorities:
Slide 20
(a) Sequential interrupt processing
User Program
➜ Higher priority interrupts cause lower-priority interrupts to wait
➜ Causes a lower-priority interrupt handler to be interrupted
Interrupt
Handler X
➜ Example: when input arrives from communication line, it needs
to be absorbed quickly to make room for more input
Interrupt
Handler Y
(b) Nested interrupt processing
M ULTIPLE I NTERRUPTS
9
M EMORY
10
M EMORY
G OING D OWN
Sould be
➜ fast
H IERARCHY
➜ Decreasing cost per bit
➜ abundant
Slide 21
THE
➜ Increasing capacity
➜ cheap
Slide 23
➜ Increasing access time
➜ Decreasing frequency of access of the memory by the
processor
Unfortunately, that’s not the reality...
Solution:
Locality of reference is essential!
• combination of fast & expensive and slow & cheap
memory
M EMORY H IERARCHY
D ISK CACHE
Typical access time
Slide 22
1 nsec
Registers
2 nsec
Cache
10 nsec
Main memory
64-512 MB
10 msec
Magnetic disk
5-50 GB
Magnetic tape
20-100 GB
100 sec
G OING D OWN THE H IERARCHY
➜ A portion of main memory used as a buffer to temporarily to
hold data for the disk
Typical capacity
<1 KB
Slide 24
1 MB
➜ Disk writes are clustered
➜ Some data written out may be referenced again. The data are
retrieved rapidly from the software cache instead of slowly from
disk
➜ Mostly transparent to operating system
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CACHE M EMORY
12
CACHE M EMORY
CACHE D ESIGN
Block Transfer
➜ Cache size
Word Transfer
• small caches have a significant impact on performance
➜ Line size (block size)
CPU
Main Memory
Cache
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Slide 27
• the unit of data exchanged between cache and main
memory
• hit means the information was found in the cache
➜ Contains a portion of main memory
• larger line size ⇒ higher hit rate
until probability of using newly fetched data becomes less
than the probability of reusing data that has been moved
out of cache
➜ Processor first checks cache
➜ If not found in cache, the block of memory containing the
needed information is moved to the cache
replacing some other data
CACHE D ESIGN
CACHE /M AIN M EMORY S YSTEM
Line
Number Tag
0
1
2
Block
¥
¥
¥
➜ Mapping function
Memory
address
0
1
2
3
• determines which cache location the data will occupy
Block
(K words)
➜ Replacement algorithm
• determines which line to replace
C—1
Slide 26
Block Length
(K Words)
Slide 28
¥
¥
¥
(a) Cache
• Least-Recently-Used (LRU) algorithm
➜ Write policy
• When the memory write operation takes place
• Can occur every time line is updated (write-through policy)
Block
• Can occur only when line is replaced (write-back policy)
2n — 1
– Minimizes memory operations
– Leaves memory in an obsolete state
Word
Length
(b) Main memory
CACHE D ESIGN
13
I NTERACTION BETWEEN I/O D EVICES AND P ROCESSOR
14
I NTERACTION
BETWEEN
I/O D EVICES
AND
P ROCESSOR
I NTERRUPT-D RIVEN I/O
➜ Controller (chip or set of chips) provides a simple interface to OS
- often, embedded OS running on the controller
Slide 29
➜ Software that communicates with controller is called device
driver
Slide 31
➜ Most drivers run in kernel mode
➜ To put new driver into kernel, system may have to
- be relinked
- be rebooted
- dynamically load new driver
Issue Read
command to
I/O module
CPU → I/O
Do something
else
Read status
of I/O
module
I/O → CPU
Interrupt
Check
status
➜ Processor is interrupted when I/O
module ready to exchange data
➜ Processor is free to do other work
➜ No needless waiting
➜ Consumes a lot of processor time
because every word read or written
passes through the processor
Error
condition
Ready
No
Read word
from I/O
Module
I/O → CPU
Write word
into memory
CPU → memory
Done?
Yes
Next instruction
(b) Interrupt-driven I/O
P ROGRAMMED I/O (P OLLING )
Slide 30
➜ I/O module performs the action, not the
processor
➜ Sets appropriate bits in the I/O status
register
➜ No interrupts occur
➜ Processor checks status until operation is
complete
Issue Read
command to
I/O module
CPU → I/O
Read status
of I/O
module
I/O → CPU
D IRECT M EMORY ACCESS
Not
ready
Check
status
Error
condition
Ready
Read word
from I/O
Module
I/O → CPU
Write word
into memory
CPU → memory
Slide 32
• Wastes CPU cycles
No
➜ Transfers a block of data
directly to or from memory
➜ An interrupt is sent when the
task is complete
➜ The processor is only involved
at the beginning and end of
the transfer
CPU → DMA
Issue Read
Do something
block command
to I/O module
else
Read status
of DMA
module
Interrupt
DMA → CPU
Next instruction
Done?
Yes
Next instruction
(a) Programmed I/O
I NTERRUPT-D RIVEN I/O
15
D IRECT M EMORY ACCESS
16