FinFET
History, Fundamentals and Future
Tsu‐Jae King Liu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720‐1770 USA
June 11, 2012
2012 Symposium on VLSI Technology Short Course
Impact of Moore’s Law
Transistor
Scaling
Higher Performance,
Investment
Lower Cost
# DEVICES (MM)
Market
Growth
CMOS generation: 1 um • • 180 nm • • 32 nm Source: ITU, Mark Lipacis, Morgan Stanley Research
YEAR
http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf
2
1996: The Call from DARPA
• 0.25 m CMOS technology was state‐of‐the‐art • DARPA Advanced Microelectronics (AME) Program Broad Agency Announcement for 25 nm CMOS technology
1998 International Technology Roadmap for Semiconductors (ITRS)
Technology Node
Gate Oxide Thickness, TOX (nm)
Drive Current, IDSAT
1999
2002
2005
2008
2011
2014
2017
2020
180 nm
130
nm
100
nm
70
nm
50 nm
35 nm
25 nm
18 nm
1.9‐2.5
1.5‐1.9
1.0‐1.5
0.8‐1.2
0.6‐0.8
0.5‐0.6
Solutions being pursued
No known
solutions
End of Roadmap
 UC‐Berkeley project “Novel Fabrication, Device Structures, and Physics of 25 nm FETs for Terabit‐Scale Electronics” • June 1997 through July 2001
3
MOSFET Fundamentals
Metal Oxide Semiconductor
Field‐Effect Transistor:
0.25 micron MOSFET XTEM
GATE LENGTH, Lg
Gate
Source
Drain
Si substrate
http://www.eetimes.com/design/automotive‐design/4003940/LCD‐driver‐highly‐integrated
GATE OXIDE THICKNESS, Tox
4
MOSFET Operation: Gate Control
N‐channel MOSFET Desired cross‐section
characteristics:
• High ON current
Gate
• Low OFF current
gate oxide
Leff
N+
P
Source
Body
• Current between Source and Drain is controlled by the Gate voltage.
• “N‐channel” & “P‐channel” MOSFETs operate in a complementary manner
N+
“CMOS” = Complementary MOS
Drain
log ID
increasing E
n(E)  exp (‐E/kT)
Sourceincreasing
VGS
distance
ION
DRAIN CURRENT
Electron Energy Band Profile
Inverse slope is subthreshold swing, S
[mV/dec]
IOFF
Drain
0
VTH
GATE VOLTAGE
VDD
5
CMOS Devices and Circuits
CIRCUIT SYMBOLS
N‐channel P‐channel
MOSFET
MOSFET
D
S
D
INVERTER
LOGIC SYMBOL
VDD
G
G
S
CMOS INVERTER CIRCUIT
VOUT
VDD
S
D
V
D OUT
VIN
GND
S
0
CMOS NAND GATE
VDD
VIN
STATIC MEMORY (SRAM) CELL
NOT AND (NAND)
TRUTH TABLE
WORD LINE
BIT LINE
0
or
1
1
or
0
BIT LINE 6
Improving the ON/OFF Current Ratio
Gate
log ID
Cox
Cdep
Source
Body
S
ION
Ctotal
Cox
Drain
VDD
VGS
• The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential.
higher ION/IOFF for fixed VDD, or lower VDD to achieve target ION/IOFF
reduced drain‐induced barrier lowering (DIBL):
log ID
Source
increasing VDS
Drain
increasing VDS
IOFF
VGS
7
MOSFET in ON State (VGS > VTH)
width velocity inversion‐layer charge density
I D  W  v  Qinv
v   eff
gate‐oxide capacitance
Qinv  Cox (VGS  VTH )
gate overdrive
mobility
DRAIN CURRENT, ID

Gate
Source
Drain
Substrate
DRAIN VOLTAGE, VDS
8
Effective Drive Current (IEFF)
CMOS inverter chain:
VDD
V2
S
D
VIN
D
GND
S
VOUT
V3
NMOS DRAIN CURRENT
V1
VDD
VDD/2
V2
V1
tpLH
tpHL
IH + IL
IEFF = 2
V3
TIME
IDSAT
IH (DIBL = 0)
VIN = VDD
IH
VIN = 0.83VDD
VIN = 0.75VDD
IL
0.5VDD
VIN = 0.5VDD
VDD
NMOS DRAIN VOLTAGE = VOUT
M. H. Na et al. (IBM), IEDM Technical Digest, pp. 121‐124, 2002
9
CMOS Technology Scaling
XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.)
90 nm node
T. Ghani et al.,
IEDM 2003
65 nm node
(after S. Tyagi et al., IEDM 2005)
45 nm node 32 nm node
K. Mistry et al.,
IEDM 2007
P. Packan et al.,
IEDM 2009
• Gate length has not scaled proportionately with device pitch (0.7x per generation) in recent generations.
– Transistor performance has been boosted by other means.
10
MOSFET Performance Boosters
• Strained channel regions  eff
• High‐k gate dielectric and metal gate electrodes  Cox
Cross‐sectional TEM views of Intel’s 32 nm CMOS devices
P. Packan et al. (Intel), IEDM Technical Digest, pp. 659‐662, 2009
11
Process‐Induced Variations
• Sub‐wavelength lithography:
– Resolution enhancement techniques are costly and increase process sensitivity
• Gate line‐edge roughness:
courtesy Mike Rieger (Synopsys, Inc.)
photoresist
• Random dopant fluctuations (RDF):
– Atomistic effects become significant in nanoscale FETs
SiO2
Source
Gate
Drain
A. Brown et al., IEEE Trans.
Nanotechnology,
p. 195, 2002
A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007
12
A Journey Back through Time…
Why New Transistor Structures?
• Off‐state leakage (IOFF) must be suppressed as Lg is scaled down
– allows for reductions in VTH and hence VDD
• Leakage occurs in the region away from the channel surface
 Let’s get rid of it!
Lg
Ultra‐Thin‐Body
MOSFET:
Gate
Gate
Source
Source
Drain
Drain
Buried Oxide
Substrate
“Silicon‐on‐
Insulator” (SOI)
Wafer
14
Thin‐Body MOSFETs
• IOFF is suppressed by using an adequately thin body region.
– Body doping can be eliminated  higher drive current due to higher carrier mobility
 Reduced impact of random dopant fluctuations (RDF)
Ultra‐Thin Body (UTB)
Double‐Gate (DG)
Lg
Gate
Gate
Source
Drain
Buried Oxide
TSi
Drain
Source
TSi
Gate
Substrate
TSi < (1/4)  Lg
B. Yu et al., ISDRS 1997
TSi < (2/3)  Lg
R.‐H. Yan et al., IEEE TED 1992
15
Effect of TSi on Leakage
Lg = 25 nm; Tox,eq = 12Å
TSi = 10 nm
TSi = 20 nm
G
G
106
Si Thickness [nm]
0.0
S
D
3x102
G
8.0
12.0
S
D
16.0
20.0
10‐1
Leakage Current
Density [A/cm2]
@ VDS = 0.7 V
4.0
G
Ioff = 2.1 nA/m
Ioff = 19 A/m
16
Double‐Gate MOSFET Structures
PLANAR:
VERTICAL
FIN:
L. Geppert, IEEE Spectrum, October 2002
17
DELTA MOSFET
D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda (Hitachi Central Research Laboratory), “A fully depleted lean‐channel transistor (DELTA) – a novel vertical ultrathin SOI MOSFET,” IEEE Electron Device Letters Vol. 11, pp. 36‐39, 1990 • Improved gate control observed for Wg < 0.3 m
– Leff= 0.57 m
Wl = 0.4 m
18
Double‐Gate FinFET
• Self‐aligned gates straddle narrow silicon fin
• Current flows parallel to wafer surface
Gate Length, Lg
Source
S
G
D
Gate 1
Drain
Current
Flow
Gate 2
G
Fin Height, Hfin
Fin Width, Wfin
19
1998: First N‐channel FinFETs
D. Hisamoto, W.‐C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.‐J. King, J. Bokor, and C. Hu, “A folded‐channel MOSFET for deep‐sub‐tenth micron era,” IEEE International Electron Devices Meeting Technical Digest, pp. 1032‐1034, 1998 Plan View
Lg = 30 nm
Wfin = 20 nm
Hfin = 50 nm
Lg = 30 nm
Wfin = 20 nm
Hfin = 50 nm
• Devices with Lg down to 17 nm were successfully fabricated
20
1999: First P‐channel FinFETs
X. Huang, W.‐C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.‐K. Choi, K. Asano, V. Subramanian, T.‐J. King, J. Bokor, and C. Hu, “Sub 50‐nm FinFET: PMOS,” IEEE International Electron Devices Meeting Technical Digest, pp. 67‐70, 1999 Lg = 18 nm
Wfin = 15 nm
Hfin = 50 nm
Transmission Electron Micrograph
21
2000: Vested Interest from Industry
• Semiconductor Research Corporation (SRC) & AMD fund project:
– Development of a FinFET process flow compatible with a conventional planar CMOS process
– Demonstration of the compatibility of the FinFET structure with a production environment
(October 2000 through September 2003)
• DARPA/SRC Focus Center Research Program funds projects:
– Approaches for enhancing FinFET performance (MSD Center, April 2001 through August 2003)
– FinFET‐based circuit design (C2S2 Center, August 2003 through July 2006)
22
FinFET Structures
Original:
Gate‐last process flow
Gate
Source
Si Fin
Drain
Gate
Improved:
Gate‐first process flow
Source
Drain
23
Fin Width Requirement
Measured FinFET DIBL
• To adequately suppress DIBL, Lg/Wfin > 1.5
 Challenge for lithography!
N. Lindert et al. (UC‐Berkeley), IEEE Electron Device Letters, Vol. 22, pp. 487‐489, 2001 24
Sub‐Lithographic Fin Patterning
Spacer Lithography a.k.a. Sidewall Image Transfer (SIT) and Self‐Aligned Double Patterning (SADP) 1. Deposit & pattern sacrificial layer
3. Etch back mask layer
to form “spacers”
SOI
SOI
BOX
BOX
2. Deposit mask layer (SiO2 or Si3N4)
4. Remove sacrificial layer;
etch SOI layer to form fins
SOI
fins
BOX
BOX
Note that fin pitch is 1/2 that of patterned layer
25
Benefits of Spacer Lithography
• Spacer litho. provides for better CD control and uniform fin width
SEM image of
FinFET with spacer‐defined fins:
Y.‐K. Choi et al. (UC‐Berkeley), IEEE Trans. Electron Devices, Vol. 49, pp. 436‐441, 2002
26
Spacer‐Defined FinFETs
Y.‐K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.‐J. King, J. Bokor, and C. Hu, "Sub‐20nm CMOS FinFET technologies,” IEEE International Electron Devices Meeting Technical Digest, pp. 421‐424, 2001
Lg = 60 nm, Wfin = 40 nm
Transfer Characteristics
Output Characteristics
27
2001: 15 nm FinFETs
-2
10
-4
10
-6
10
-8
10
Transfer Characteristics
-2
Vd=-1.0 V P+Si0.4Ge0.6 Vd=1.0 V
Gate
Vd=0.05 V
Vd=-0.05 V
N-body=
18
-3
2x10 cm
10
-6
10
10
-10
10
-4
-8
-10
10
-12
10
10
NMOS
PMOS
-1.0 -0.5 0.0
0.5
1.0
1.5
Gate Voltage, Vg [V]
-12
10
2.0
Drain Current, Id[uA/um]
Drain Current, Id [A/um]
Y.‐K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.‐J. King, J. Bokor, C. Hu, "Sub‐20nm CMOS FinFET technologies,” IEEE International Electron Devices Meeting Technical Digest, pp. 421‐424, 2001
Output Characteristics
600
500
600
PMOS
400
|Vg-Vt|=1.2V
NMOS
400
Voltage step
: 0.2V
300
500
300
200
200
100
100
0
-1.5 -1.0 -0.5 0.0
0.5
1.0
0
1.5
Drain Voltage, Vd [V]
Wfin = 10 nm; Tox = 2.1 nm
28
2002: 10 nm FinFETs
SEM image:
B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.‐Y. Yang, C. Tabery, C. Hu, T.‐J. King, J. Bokor, M.‐R. Lin, and D. Kyser, "FinFET scaling to 10nm gate length,"
International Electron Devices Meeting Technical Digest, pp. 251‐254, 2002 Output Characteristics
TEM images
• These devices were fabricated at AMD, using optical lithography.
29
Hole Mobility Comparison
Measured Field‐Effect Hole Mobility
Mobility(cm2/V-sec)
160
140
Vg-Vth=.8V
120
<100> channel
• DG FET has higher hole mobility due to lower transverse electric field
100
80
FinFET
• For the same gate overdrive, hole mobility in DG‐FinFET is 2× that in a control bulk FET
60
Bulk FET
40
20
0
0
0.5
Effective Field (MV/cm)
1
30
FinFET Process Refinements
Y.‐K. Choi, L. Chang, P. Ranade, J. Lee, D. Ha, S. Balasubramanian, A. Agarwal, T.‐J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," IEEE International Electron Devices Meeting Technical Digest, pp. 259‐262, 2002 Fin‐sidewall smoothening for
improved carrier mobilities
Gate work function tuning for VTH adjustment
31
FinFET Reliability
Id / Id [%]
Y.‐K. Choi, D. Ha, J. Bokor, and T.‐J. King, “Reliability study of CMOS FinFETs,” IEEE International Electron Devices Meeting Technical Digest, pp. 177‐180, 2003 30
Stress Bias Condition: Vg=Vd=2.0V
20
• Narrower fin  improved hot‐carrier (HC) immunity
Lg=80nm
10
• HC lifetime and oxide QBD
are also improved by smoothening the Si fin sidewall surfaces (by H2
annealing)
VT / VT [%]
0
-10
-20
-30
0
10
W fin=18nm
W fin=34nm
1
W fin=26nm
W fin=42nm
2
10
10
Stress Time [sec]
3
10
32
Tri‐Gate FET
Lg = 60 nm
Wfin = 55 nm
Hfin = 36 nm
B. Doyle et al. (Intel), IEEE Electron Device Letters, Vol. 24, pp. 263‐265, 2003
33
SOI Multi‐Gate MOSFET Designs
Tri‐Gate FET
Relaxed fin dimensions
WSi > Lg/2; HSi > Lg/5
HSi / Leff
FinFET
Narrow fin
WSi ~ Lg/2
body dimensions required for
DIBL=100 mV/V
Tox = 1.1nm
WSi / Leff
UTB FET
Ultra‐thin SOI
HSi ~ Lg/5
after Yang and Fossum, IEEE Trans. Electron Devices, Vol. 52, pp. 1159‐1164, 2005
34
Double‐Gate vs. Tri‐Gate FET
• The Double‐Gate FET does not require a highly selective gate etch, due to the protective dielectric hard mask.
• Additional gate fringing capacitance is less of an issue for the Tri‐Gate FET, since the top fin surface contributes to current conduction in the ON state.
Double‐Gate FET
Tri‐Gate FET
channel
after M. Khare, 2010 IEDM Short Course
35
Independent Gate Operation
• The gate electrodes of a double‐gate FET can be isolated by a masked etch, to allow for separate biasing.
– One gate is used for switching. – The other gate is used for VTH control.
Drain
Gate1
Gate2
Back‐
Gated FET
Source
D. M. Fried et al. (Cornell U.), IEEE Electron Device Letters, Vol. 25, pp. 199‐201, 2004
L. Mathew et al. (Freescale Semiconductor), 2004 IEEE International SOI Conference
36
Bulk FinFET
• FinFETs can be made on bulk‐Si wafers
 lower cost
 improved thermal conduction
with super‐steep retrograde well (SSRW) or “punch‐
through stopper” at the base of the fins
• 90 nm Lg FinFETs
demonstrated
 Wfin = 80 nm
 Hfin = 100 nm
DIBL = 25 mV
C.‐H. Lee et al. (Samsung), Symposium on VLSI Technology Digest, pp. 130‐131, 2004
37
Bulk vs. SOI FinFET
(compared to SOI FinFET)
H. Bu (IBM), 2011 IEEE International SOI Conference
38
2004: High‐k/Metal Gate FinFET
D. Ha, H. Takeuchi, Y.‐K. Choi, T.‐J. King, W. Bai, D.‐L. Kwong, A. Agarwal, and M. Ameen, “Molybdenum‐gate HfO2 CMOS FinFET technology,” IEEE International Electron Devices Meeting Technical Digest, pp. 643‐646, 2004
39
IDSAT Boost with Embedded‐SiGe S/D
Process flow:
IOFF vs. ION
Lg = 50 nm
Wfin = 35 nm
Hfin = 65 nm • 25% improvement in IDSAT
is achieved with silicon‐
germanium source/drain, due in part to reduced parasitic resistance
P. Verheyen et al. (IMEC), Symposium on VLSI Technology Digest, pp. 194‐195, 2005
40
Fin Design Considerations
• Fin Width
Gate Length
– Limited by etch technology
– Tradeoff: layout efficiency vs. design flexibility
Drain
• Fin Height
Source
– Determines DIBL • Fin Pitch
– Determines layout area
Fin Height
Pfin
Fin Width
– Limits S/D implant tilt angle
– Tradeoff: performance vs. layout efficiency
41
FinFET Layout
• Layout is similar to that of conventional MOSFET, except Pfin
that the channel width is quantized:
Source
Gate
Source
Gate
Drain
Drain
Source
Source
Bulk‐Si MOSFET
FinFET
The S/D fins can be merged by selective epitaxy:
M. Guillorn et al. (IBM), Symp. VLSI Technology 2008
Intel Corp.
42
Impact of Fin Layout Orientation
• If the fin is oriented || or  to the wafer flat, the channel surfaces lie along (110) planes.
– lower electron mobility
– higher hole mobility (Series resistance is more significant at shorter Lg.)
• If the fin is oriented 45° to the wafer flat, the channel surfaces lie along (100) planes.
L. Chang et al. (IBM), SISPAD 2004
43
FinFET‐Based SRAM Design
Best Paper Award: Z. Guo, S. Balasubramanian, R. Zlatanovici, T.‐J. King, and B. Nikolic, “FinFET‐based SRAM design,” Int’l Symposium on Low Power Electronics and Design, pp. 2‐7, 2005 6‐T SRAM Cell Designs Cell Layouts
Butterfly Curves
Reduced cell area with
independently gated PGs
44
State‐of‐the‐Art FinFETs
22nm/20nm high‐performance CMOS technology
• Lg = 25 nm
XTEM Images of Fin
C.C. Wu et al. (TSMC), IEDM 2010
45
Looking to the Future…
2010 International Technology Roadmap for Semiconductors (ITRS)
2012
Gate Length
2014
2016
2018
2020
2022
2024
24 nm 18 nm 15 nm 13 nm 11 nm 10 nm
7 nm
Gate Oxide Thickness, TOX (nm)
Drive Current, IDSAT
End of Roadmap
(always ~15 yrs away!)
46
FinFET vs. UTBB SOI MOSFET
Cross‐sectional TEM views
of 25 nm UTB SOI devices
NFET
TSi = 5 nm
PFET
TSi = 5 nm
K. Cheng et al. (IBM), Symposium on VLSI
Technology Digest, pp. 128‐129, 2011
B. Doris (IBM), 2011 IEEE International SOI Conference
*C.C. Wu et al.
(TSMC), IEDM
2010
47
Projections for FinFET vs. UTBB SOI MOSFETs
NMOS:
Electron Mobility
Electron Mobility (cm2/V.s)
300
FDSOI
Open: FinFET
Closed: FDSOI
250
Unstrained
Longi.
Trans.
Vertical
200
150
Unstrained
Longi.
Trans.
Vertical
FinFET
100
12
12
12
Unstrained
Longi.
Trans.
Vertical
12
13
2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )
Hole Mobility
Hole Mobility (cm2/V.s)
Technology Node:
PMOS:
Open: FinFET
Closed: FDSOI
300
270
240
210
180
20nm
tSOI =7nm; tFIN =10nm
Unstrained
Longi.
Trans.
Vertical
12
12
12
12
13
2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )
14/16nm
tSOI =5nm; tFIN =7.5nm
FinFET
Unstrained
Longi.
Trans.
Vertical
12
12
12
13
10/12nm
tSOI =3.5nm; tFIN =5nm
0
0
0
0
0
FinFET
12
2x10
4x10
6x10 8x10 10
-2
Inversion Charge Concentration (cm )
150
0
120
0
90
0
Unstrained
Longi.
Trans.
Vertical
FinFET
FDSOI
FDSOI
60
12
12
0
FDSOI
12
12
13
2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )
12
12
12
12
13
2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )
12
12
12
12
13
2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )
N. Xu et al. (UC‐Berkeley), IEEE Electron Device Letters, Vol. 33, pp. 318‐320, 2012
48
Remaining FinFET Challenges
• VTH adjustment
– Requires gate work‐function (WF) or Leff tuning
– Dynamic VTH control is not possible for high‐aspect‐ratio multi‐fin devices
• Fringing capacitance between gate and top/bottom of S/D
– Mitigated by minimizing fin pitch and
using via‐contacted, merged S/D
M. Guillorn, Symp. VLSI Technology 2008
• Parasitic resistance
– Uniform S/D doping is difficult to achieve with conventional implantation
 Conformal doping is needed
e.g. Y. Sasaki, IEDM 2008
H. Kawasaki, IEDM 2008
• Variability
– Performance is very sensitive to fin width
– WF variation dominant for undoped channel
T. Matsukawa, Symp. VLSI Technology 2008
49
Random Dopant Fluctuation Effects
• Channel/body doping can be eliminated to mitigate RDF effects. • However, due to source/drain doping, a trade‐off exists between performance & RDF tolerance for Lg < 10nm:
ION vs. TSi
IOFF and VT vs. TSi
1E-4
 SD = 3nm
75
VT (mV)
IOFF (A /  m)
1E-6
50
1E-8
Lg = 9nm, EOT = 0.7nm
1E-10
25
4.5
SD = 3nm
100
5.5
TSi (nm)
6.5
0
ION (mA / m)
SOI FinFET w/ atomistic S/D gradient regions:
0.8
0.4
4.5
5.5
TSi (nm)
V. Varadarajan et al. (UC-Berkeley), IEEE Silicon Nanoelectronics Workshop, 2006
6.5
50
HSi / Leff
Bulk vs. SOI Multi‐Gate FET Design
• To ease the fin width requirement, the fin height should be reduced.
tri‐gate SOI (thick BOX)
[J.G. Fossum et al., IEDM 2004] WSi / Leff
• The bulk tri‐gate design has the most relaxed body dimension requirements.
 SSRW (at the base of the fin) improves electrostatic integrity
X. Sun et al. (UC‐Berkeley), IEEE Electron Device Letters, Vol. 29, pp. 491‐493, 2008
51
SOI MOSFET Evolution
• The Gate‐All‐Around (GAA) structure provides for the greatest capacitive coupling between the gate and the channel.
http://www.electroiq.com/content/eiq-2/en/articles/sst/print/volume-51/issue-5/features/nanotechnology/fully-gate-all-around-silicon-nanowire-cmos-devices.html
52
Scaling to the End of the Roadmap
32 nm
planar
22 nm
multi‐gate segmented channel
beyond 10 nm
stacked nanowires
3‐D:
Intel Corp.
quasi‐planar:
P. Packan et al. (Intel), IEDM 2009
B. Ho (UCB), ISDRS 2011
C. Dupré et al. (CEA‐LETI)
IEDM 2008
Stacked gate‐all‐around (GAA) FETs achieve the highest layout efficiency.
53
Summary
• The FinFET was originally developed for manufacture of self‐aligned double‐gate MOSFETs, to address the need for improved gate control to suppress IOFF, DIBL and process‐induced variability for Lg < 25nm.
• Tri‐Gate and Bulk variations of the FinFET have been developed to improve manufacturability and cost. • It has taken ~10 years to bring “3‐D” transistors into volume production.
• Multi‐gate MOSFETs provide a pathway to achieving lower power and/or improved performance.
• Further evolution of the MOSFET to a stacked‐channel structure may occur by the end of the roadmap.
54
Acknowledgments
• Collaborators at UC‐Berkeley
Profs. Hu, King, Bokor
Prof.
Subramanian Digh Hisamoto
Hideki Takeuchi Xuejue Huang
Wen-Chin Lee Jakub Kedzierski
Yang‐Kyu
Choi
Stephen Tang
Peiqi Xuan
Leland Chang
Nick Lindert
Sriram
Kyoungsub
Balasubramanian Zheng Guo Pushkar Ranade, Charles Kuo, Daewon Ha
Shin
Radu
Zlatanovici
Prof. Nikolic
• Early research funding: DARPA, SRC, AMD
• UC Berkeley Microfabrication Laboratory
(birthplace of the FinFET)
55