Reliability Handbook
Contents
Integrity and Reliability
Package Integrity Tests
Device Reliability Tests
Appendix 1 Calculations
Appendix 2 Example of Failure Rate Calculation
INTEGRITY AND RELIABILITY
ZETEX Semiconductors’ Reliability department routinely performs a variety of industry standard tests on
batches of both discrete components and linear IC’s. Each test comprises three parts:
• A pre-test verifies that only good devices are used.
• The devices are then subjected to the specified conditions for a defined duration.
• Electrical tests decide if each device still meets specification requirements.
The tests divide into two groups: those that show the integrity of the packaging, and those that predict the
overall reliability of a particular device family.
PACKAGE INTEGRITY TESTS <top>
These tests relate only to the package, and therefore represent a broad range of device types.
TEMPERATURE HUMIDITY WITH BIAS (THB)
For up to 2000 hours the devices are stored in an environment at 85°C and 85%RH, (hence the
commonly recognised name for this test: "85/85"), under reverse bias. The objective of the test is to
check the ability of the package to protect the device from a damp environment.
TEMPERATURE CYCLING (TC)
The objective is to determine the ability of the package to withstand rapid changes of temperature
within an air environment. The temperature range involved is usually in the order of -55°C to +150°C
although this varies from device to device. Each cycle lasts 60 minutes unless otherwise specified.
This test is designed to accelerate the effects of thermal mismatch amongst the die/assembly
components
RESISTANCE TO SOLDER HEAT (RSHD, RSHF, RSHH & RSHR)
These single cycle tests simulate the various conditions that will be seen by the devices during PCB
board assembly processes. The use of these tests will check for the integrity of the assembled
package. Conditions are:
RSHD:
RSHF:
RSHH:
RSHR:
260°C, 10 seconds, Dip
260°C, 30 seconds, Float
350°C / 400°C, 3 seconds, Hand solder
260°C max, reflow cycle, 3 times
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Reliability Handbook
MOISTURE SENSITIVITY LEVEL (MSL)
MSL relates to the packaging and handling precautions for semiconductors. The MSL indicates the
time period to which a moisture sensitive device can be exposed to ambient room conditions
(approximately 30°C/60%RH).
During the solder reflow process; the sudden expansion of any trapped moisture inside the
component can result in internal separation (delamination) of the plastic encapsulation from the die
or lead-frame, wire bond damage, die damage, and internal cracks. Most of this damage is not
visible on the component surface. In extreme cases, cracks will extend to the component surface. In
the most severe cases, the component will bulge and pop, this is known as the "popcorn" effect.
Testing involves submitting the device to standard assembly conditions including repeated reflow
cycles, followed by testing to datasheet parameters. C-mode Scanning Acoustic Microscopy (CSAM) testing can be performed to validate internal integrity.
Zetex products comply with IPC/JEDEC J-STD-020C at MSL 1 – unlimited storage.
HOT STORAGE (HS)
The devices are stored without bias in an environment at the maximum storage temperature (from
the device data sheets) for up to 2000 hours. This tests the resistance of the plastic package to
degradation and the resistance of the wire bonds to wire bond type failure mechanisms.
COLD STORAGE (CS)
The devices are stored without bias in an environment at the minimum storage temperature (from
the device data sheets) for up to 2000 hours. This tests the resistance of the plastic package to
degradation and the resistance of the wire bonds to wire bond type failure mechanisms.
AUTOCLAVE (CLV)
Autoclave, also known as “Pressure Cooker Test (PCT) is an environmental test which measures
device resistance to moisture penetration and the resultant effects of galvanic corrosion. Conditions
employed during the test include 121°C, 100% relative humidity and 2 atmospheres pressure. This
test is highly accelerated and is generally carried out for 96 hours.
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Reliability Handbook
SOLDERABILITY / SOLDERABILITY (UNLEADED)
This test verifies the package’s ability to solder onto PCBs successfully using SnPb or lead-free
solder.
SOLDERABILITY POST HOT STORE
Solderability testing is performed after storage for 16 hours at 150°C has been performed.
SOLDERABILITY POST TEMPERATURE & HUMIDITY
Solderability testing is performed after storage for 168 hours at 85°C/85%RH has been performed.
SOLDER WETTABILITY
This test, which is related to solderability, measures the time taken for the solder to “wet” the
device’s legs/pins using a wetting balance. This must occur within 3 seconds.
ESD TESTING
These tests determine the device/package’s ability to withstand damage or degradation by exposure
to electrostatic discharge. There are three types of testing:
CDM - Charged Device Model – this simulates the discharge that occurs as a charged component
discharges to another object at a different electrostatic potential.
The results are classified as follows:
<125V, 125 to <250V, 250 to <500V, 500V to <1000V, 1000 to <1500,
1500 to <2000, ≥2000V
HBM - Human Body Model –
this simulates the discharge from a human being. The results are
in the ranges as follows:
<250V, 250 to <500V, 500V to <1000V, 1000 to <2000, 2000 to <4000,
4000 to <8000, ≥8000V
MM
- Machine Model –
this simulates the discharge from a machine. The results are in
the ranges as follows:
<100V, 100 to <200V, 200V to <400V, ≥400V
All these tests use a defined electrical charge which is applied to the device across all the pin
combinations, testing is usually performed from the lowest voltage upwards to determine the
maximum withstand voltage.
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Reliability Handbook
DEVICE RELIABILITY TESTS <top>
The results from these tests are used to predict the reliability of the devices in terms of FIT (1 FIT = 1 failure
per billion (1E9 -One thousand million) device hours and mean time to failure (MTTF). As the tests depend to
some extent on the design of a particular die, the results are grouped together into families of similar
devices.
HIGH TEMPERATURE OPERATING LIFE (HTRB, HTGB AND HTOL)
High Temperature Operating Life (HTOL), High Temperature Gate Bias (HTGB) and High
Temperature Reverse Bias (HTRB) tests are performed to accelerate failure mechanisms that are
thermally activated through the use of biased operating conditions. The temperature and voltage
used in the stress will vary with the product being stressed, but will generally be from 125 to 200°C
with a bias of between 80% and 100% of maximum rating. Duration of the test will be between 168
and 2000 hours.
The tests carried out on the product stresses the die and may cause junction leakage. Parametric
changes may also occur due to ionic impurities that can be released onto the die surface, either from
the package or the die itself. The high temperature of this test accelerates failure mechanisms
according to the Arrhenius equations and so simulates a test conducted at a lower temperature for a
very much greater length of time.
LOW TEMPERATURE OPERATING LIFE (LTOL)
This test biases the operating nodes. Typically, several input parameters may be adjusted to control
internal power dissipation. These include: supply voltages, clock frequencies, input signals, etc.,
which may be operated even outside their specified values, but resulting in predictable and nondestructive behaviour of the devices under stress. The particular bias conditions should be
determined to bias the maximum number of potential operating nodes in the device. The test is
intended to look for failures caused by hot carriers.
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Reliability Handbook
Appendix 1
RELIABILITY CALCULATION DEFINITIONS
A1.1 CALCULATIONS <top>
The cumulative hours are calculated using the formula:
Cumulative Hours = Number of devices tested x Test hours
Percentage fails are calculated by:
Number of failures
Number of devices tested
% Failures =
X 100%
The mean time before failure is the average time it takes for a failure to occur. It is calculated using the
formula:
Total device hours
MTBF =
Total number of failures
Failure Rate is the reciprocal of the MTBF.
1
MTBF
FR =
ELECTRICAL TRIALS
A1.2 FAILURE RATE CALCULATION
ACCELERATION FACTORS
Increasing the temperature of the test environment to which the devices are subjected can accelerate most
failure mechanisms. It is therefore possible to perform relatively short tests (typically from 1 week to 2
months) which simulate many years of device stressing under more normal conditions. Clearly it is
necessary to have some measure of how greatly the failure mechanisms are accelerated.
Suppose a device is stressed at a high temperature, T2 for time t2. It is required to find the equivalent, t1,
which would cause the device the same level of stress at a lower temperature T1. It is noted that if T2>T1
then t2>t1. The acceleration factor is then defined as:
A=
t1
t2
that is, the ratio of the time at the lower temperature to that at the higher. Since the acceleration factor is a
dimensionless ratio, it will be equal to the ratio of any other parameters proportional to the stress times. The
most useful ratio is that of failure rates, which are inversely proportional to stress times; if f1 is the failure rate
at T1, and f2 the failure at T2 then....
T2>T1 implies that f2>f1 and A=
t1
t2
So if f2 is known f1 is found simply as f1 = A.f2
All that is now required is to find the value of the acceleration factor.
Acceleration factor
© Zetex Semiconductors Plc 2004-6
=e
⎡ EA ⎛ 1 1
⎢ ×⎜⎜ −
⎣⎢ k ⎝ T1 T2
⎞⎤
⎟⎟ ⎥
⎠ ⎦⎥
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Reliability Handbook
A1.3 TEMPERATURE ACCELERATION
The High Temperature Reverse Bias (HTRB) test is an example of a temperature-accelerated test. It is
usually found that the rates of the reactions causing device failure are accelerated with temperature
according to the Arrhenius equation.
Where
EA. = activation energy of the failure mechanism
k = Boltzman constant = 8.6E-5 eV/K
A, T1, T2 are as defined above
The activation energy, EA, is found experimentally and is usually of the order of 1.0eV, depending on the
predominant failure mechanism. For the failure mechanisms in Zetex products, a value of 0.9eV has been
determined.
A1.4 CHI-SQUARED DISTRIBUTION
The failure rate predictions quoted in this report are based on a statistical tool known as the "chi-squared"
distribution. This is simply a mathematical model that describes the relationship between the actual failure
rate of a given device and the observed failure rate of a limited sample of that device. It is generally accepted
that the chi-squared distribution is the most accurate model for calculating failure rates from the relatively
small numbers of failures observed when testing electronic components.
A1.5 THE CHI SQUARED MULTIPLIER, χ2
The value of the chi squared multiplier, χ2, depends on the Upper Confidence Level (UCL or α ) to which the
failure rate is to be quoted, (see section A1.6 about confidence levels), and the degrees of freedom (ν),
calculated from the number of failures, n. The actual values are derived directly from the chi-squared
distribution and are usually summarised in tables. The first five values, to a UCL of 60%, are tabulated
below:
ν
χ2
Degrees of freedom
Chi-Squared value
2
1.83
4
4.04
6
6.21
8
8.35
10
10.5
A1.6 UPPER CONFIDENCE LEVEL (UCL)
The reliability predictions in this report are expressed with a UCL of 60%. This means that for any given
device, there is a 60% chance that its failure rate will be less than or equal to the value given. A UCL of 60%
is deemed adequate for most applications, however where greater confidence is required the reliability
figures should be multiplied by the factor given in the table below:
TOTAL
NUMBER OF
FAILURES
0
1
2
3
4
5
6
7
8
© Zetex Semiconductors Plc 2004-6
FAILURE RATE MULTIPLYING FACTORS
60% UCL
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
90% UCL
2.52
1.93
1.71
1.60
1.52
1.47
1.44
1.40
1.38
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95% UCL
3.27
2.35
2.03
1.86
1.74
1.67
1.61
1.57
1.53
99% UCL
5.03
3.29
2.71
2.41
2.21
2.08
1.98
1.90
1.84
Reliability Handbook
A1.7 CALCULATING THE DEGREES OF FREEDOM
Since we require the maximum potential failure rate, the value of n used is taken to be 1 greater than the
actual number of failures observed during the test period. In order to take the "worst case" it is assumed that
the next failure would have occurred at the same time as the test was terminated. If the actual number of
failures observed is n, then...
Degrees of freedom = ν = 2(n+1)
A1.8 DETERMINING FIT VALUE
Now that the degrees of freedom has been calculated and the correct χ2 value has been determined from the
Chi squared distribution table the failure rate is calculated from:
FR =
χ2
2 × EDH
Where: EDH = Equivalent device hours
To convert the failure rate to a fit value this formula must be used:
FIT value =
FR
10 −9
A1.9 REFERENCES
Further discussion on accelerated testing can be found in the following documents:
(1) "VLSI Technology" Edited by Sze. 1984
Mc-Graw-Hill International Book Company
(2) "A Review of the Status of Plastic Encapsulated Semiconductor Component Reliability" RE Lawson
British Telecom Journal Vol 2 No 2 April 1984
Further discussion on the application of the chi-squared distribution to failure rate calculations can be found in:
"Electronic Equipment Reliability" JC Cluley MacMillan
The derivation of the chi-squared distribution and tables is discussed in most advance statistics textbooks.
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Reliability Handbook
Appendix 2
Example of a Failure Rate Calculation <top>
PNP High performance SOT23
Test performed:
HTRB for 1008 hours
Number tested:
400
Number of failures: 0
Cumulative Device Hours = number of devices tested x Test time
= 400 x 1008 = 403,200
The acceleration factor is calculated from the Arrhenius equation (see section A1.3)
Test temperature:
Service temperature:
Activation energy:
AF = e
150°C = 423 Kelvin
55°C = 328 Kelvin
0.9eV
0.9
1 ⎞⎤
⎡
⎛ 1
×⎜
−
⎟⎥
⎢
−5
⎣ 8.63 x10 ⎝ 328 423 ⎠ ⎦
= 1262.318
Equivalent device hours = Cumulative Device Hours x Acceleration Factor
403,200 x 1262.31 = 508,966,617.6 Hours
It is now possible to calculate the failure rate
Degrees of freedom = 2 x (Number of failures + 1) = 2 x (0 + 1) = 2
From the Chi-square table in Appendix 1, χ2 = 1.83
The failure rate is found using the formula
FR =
χ2
2 × EDH
=
-9
1.83
= 1.80 x 10
2 × 508966617.6
It is then converted to a FIT value using the formula:
FIT Value = =
FR 1.8 ×10 −9 = 1.80 FIT
=
10 −9
10 −9
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Tel: (49) 89 45 49 49 0
Fax: (49) 89 45 49 49 49
email: europe.sales@zetex.com
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USA
Tel: (1) 631 360 2222
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Tel: (852) 26100 611
Fax: (852) 24250 494
email: asia.sales@zetex.com
Zetex products are distributed worldwide. For details, see http://www.zetex.com/
© Zetex Semiconductors Plc 2004-6
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Zetex Semiconductors plc
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Chadderton, Oldham, OL9 9LL
United Kingdom
Tel: (44) 161 622 4444
Fax: (44) 161 622 4446
email: hq@zetex.com