IJSART - Volume 1
Issue 10 –OCTOBER 2015
ISSN [ONLINE]: 2395-1052
High Performance FPGA-Based Decimal-To Binary
Conversion Schemes for Decimal Arithmetic
E. Jebamalar Leavline1, G. Sudha2, S.Sivashankari3
1, 2, 3
1, 2, 3
Department of Electronics and Communication Engineering
Bharathidasan Institute of Technology, Anna University, Tiruchirappalli – 620 024, India
ABSTRACT- Decimal arithmetic is more suitable for human
approaches where binary arithmetic for computers. This gap
is bridged by conversion techniques. This work presents highperformance decimal-to-binary conversion circuits to support
decimal arithmetic. Bits of the BCD inputs are grouped into a
number of groups. The contribution of each group to the
overall binary result is computed separately. Then these
contributions are added to form the final binary result. The
proposed circuits perform significantly better than existing
BCD-to-binary conversion circuits. The comparison reveals
that certain bit-grouping may perform better than others. This
BCD to Binary conversion circuit implement on FPGA in
Xilinx platform. The growth of this circuit in area and delay
for BCD inputs is analyzed.
I. INTRODUCTION
Many of today’s applications such as financial,
Internet-based, and scientific application handle decimal
operands. There are two major approaches for performing
arithmetic on decimal operands. They are,
 Directly manipulating the decimal operands which has the
advantage of reducing potential rounding errors.
 Converting the decimal operands to binary and perform the
required arithmetic in binary and convert the result back to
decimal.
The advantage of the second method is that it utilizes
the already predominant binary arithmetic hardware.
Furthermore some applications require methods like the
second approach due to the use of the already optimized
binary hardware. In this paper, we present several high
performance architectures for decimal to binary conversion to
support decimal arithmetic. We first split the BCD input into
several groups of bits and then compute the contributions to
form the final result. For example, suppose that the BCD
operand to be converted to binary is (346)10 or (0011 0100
0110)BCD. For a group size of 4 bits (one BCD digit), the
digit 6 contributes (0110)2 to the final binary result. The digit
4 contributes (40)10 or (101000)2. The digit 3 contributes
(300)10 or (100101100)2. After obtaining the contribution of
each digit in the BCD operand we add these contributions to
obtain final result. Therefore, adding (0110)2 + (101000)2 +
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(100101100)2 in binary results into (101011010)2 = (346)10.
While this approach seems simple, that it performs
significantly better than existing techniques for converting
BCD numbers to their binary equivalents on FPGAs.
There are several reasons for this superior
performance. First, all the contributions are computed in
parallel and the addition of these contributions is done via
binary addition in the FPGA which results into a fast circuit.
Second, the outputs of the contribution generation circuit for a
given group are functions of a number of variables equals to
the group size. For example, in a 4-bit grouping, the outputs of
the group contribution generation are functions of the 4 bits of
the group. By choosing the group size that matches the lookup table size on an FPGA family, each function requires only
one look-up table (LUT) in the FPGA which results into a
compact overall design.
This scheme is based on splitting the input BCD
number into groups of consecutive bits from the least
significant position to the most significant position. For
example, if there are M groups then the least significant group
would be denoted as G0 and the most significant group would
be denoted as GM-1. The binary contribution of each group
varies based on its position or index. It is generated using a
digital hardware that has the individual bits of the group as
inputs and the individual bits of the binary contribution as
outputs. The binary contributions from all groups are added
using a binary addition stage to generate the binary equivalent
of the input BCD number.
There are three different bit-grouping schemes for
BCD-to-binary conversion. These are 4-bit grouping, 6-bit
grouping, and 8-bit grouping. Verilog dataflow modeling is
used for programming these techniques. We first compare the
performance of 4-bit grouping (one BCD digit grouping)
scheme to other existing schemes. We then compare the
performance of the different grouping schemes (4-bit or 1
BCD digit, 6-bit or 1.5 BCD digits, and 8-bit or 2 BCD digits)
with existing method on FPGA Spartan 3-XC3S200-2 FT256
device in Xilinx platform.
The rest of this paper is organized as follows:
Section II discusses techniques for decimal to binary
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IJSART - Volume 1
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conversion and other related work. Section III discusses our
proposed grouping techniques for BCD to binary conversion
in details.
Section IV discusses simulation and
implementation result of our work. Section V provides area
and delay analysis for grouping schemes. Section VI discusses
the conclusion of the paper.
II. LITERATURE REVIEW
There are two major approaches for decimal
arithmetic.
 Direct manipulation of BCD numbers and
 BCD arithmetic based on binary hardware.
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As the number of digits grows, the size of the multipliers
needed quickly grows. The authors in [8] re-write the above
equation using Horner’s rule as follows:
D= (((Dn-110+Dn-2)10+…….) 10+D0).
The authors in [8] also present other arrangements of
this formula to increase parallelism of computations as
follows:
D= (((Dn-110+Dn-2)100+…….) 100+(D110+D0)).
D=(((Dn-1100+Dn-210+Dn-3)103+…)103+(D2102+D110+D0)).
D=(((Dn-1103+Dn-2102+Dn-310)104+…)104+
(D3103+D2102+D110+D0)).
In 2007-2008, the authors of Binary-coded decimal
digit multipliers, G. Jaberipur and A. Kaivani presented
architecture for BCD digit by BCD digit multiplication, and
also the authors of Decimal multiplication using compact
BCD multiplier, R.James, T. Shahana also proposed the same
architecture [3, 4]. In 2009, the authors of A high performance
unified BCD and binary adder/subtractor, A. Singh, A. Gupta,
S. Veeramachaneni, M.B. Srinivas presented techniques for
BCD addition subtraction on to BCD operands, while in the
same year R.D. Kenney, M.J. Schulte, the authors of Highspeed multi operand decimal adders, proposed techniques that
operate on multi operands[5, 6].
In [13], the authors proposed a method to convert a
BCD number to its binary equivalent based on expanding the
BCD number and then shifting the individual BCD digits to
left (multiplying by multiples of 2) according to their position
in the BCD number. For example, the BCD number 76 is
expanded to (7 x10 + 6 x 1 = 7x (8 + 2) + 6 x 1 = 7 x 23 + 7 x
21 + 6 x 20). This means that the binary equivalent of the BCD
number 76 can be obtained by the addition of 7 shifted to the
left 3 times (0111000)2, 7 shifted to the left 1 time (01110)2,
and 6 not shifted (0110)2. The binary result is (0111000)2 +
(01110)2 + (0110)2 = (1001100)2. The authors in [13]
employed 4-bit carry-look-ahead addition in a complex tree
structure to design an 8-digit to 27-bit converter.
In 2008-2011, the authors M. Véstias, H. Neto of
Parallel decimal multipliers using binary multipliers and the
authors H. Neto, M. Véstias of Decimal multiplier on FPGA
using embedded binary multipliers and the authors M.
Vestias, H. Neto of Iterative decimal multiplication using
binary arithmetic [8-10] described the architectures which are
the examples of BCD arithmetic based on binary hardware,
that is the BCD number is first converted to its binary
equivalent the arithmetic is performed in binary and the result
is converted back to BCD. They highlighted several
techniques such as traditional successive division by 2. In this
technique the BCD input is shifted right by one bit position
each BCD digit in shifted number is tested. If the BCD digit is
greater than or equal to 8, the number 3 is subtracted from the
digit [8, 11–13] or the most significant bit in the digit is
cleared and the number 5 is added to the digit [8]. The
procedure is repeated until all bits are generated. Another
method for converting a BCD number to its binary equivalent
is direct computation based on the following formula in
binary:
Dn-1…..D3D2D1D0=D(n-1)10(n1)
+…..+D3103+D2102+D1101+D0100.
The authors in [14] proposed a faster implementation
for the expansion method of [13]. The method was
demonstrated by presenting the implementation of a 7-digit to
24-bit converter. Instead of using 4-bit carry-look-ahead
adders to add the bits of the expanded numbers, the bits are
grouped according to their positions carefully such that the
result of adding the arranged bits within each group does not
exceed (15)10 = (1111)2. By applying this rule, partial sums are
obtained without any carry propagation at this stage of the
design. PROMs are used to generate these partial sums. Same
approach is followed in the second level of logic. The final
result, which is the sum of the outcomes of the first and the
second stages and any individual bits that do not belong to any
group, is obtained in the third stage where 4- bit carry-lookahead adders and other logic are used whenever needed. The
BCD to binary conversion method presented in [15] employs a
code converter that converts consecutive pairs of BCD digits
to their binary equivalent. The binary codes are generated
using PROMs. The final binary result is obtained by adding up
individual bits in the binary codes using the same approach in
[14].
A disadvantage of converting BCD numbers based on
this formula is that it requires multiplication of powers of 10.
The authors in [10] have employed a similar
technique to design a 4-digit BCD-to-binary conversion circuit
which they used in developing an iterative decimal multiplier.
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However, the BCD-to-binary circuit they developed does not
constitute a generic BCD-to-Binary conversion circuit.
Furthermore, they did not discuss the implementation and
performance of this conversion circuit as a separate module
since their focus was on creating an iterative BCD multiplier.
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Table 1. D3 Contribution generator output functions
The technique in [15] groups of 8-Bits similar to one
of the techniques presented in this work, the design of the
code converter and the addition stages in [15] is different than
ours. In addition, the design in [15] always separated the least
significant BCD digit and considers it as a one group by itself.
In our case, we focus on designing a generic circuit
for parallel BCD-to-binary conversion which can be used in
any BCD arithmetic circuit that utilizes binary hardware. We
compute the binary equivalent of a BCD number based on the
direct formula using novel method. Instead of using
multipliers to compute of each term of the formula, we
compute the contribution of each term of the formula, we
compute the contribution of each digit using direct Boolean
functions
III. GROUPING TECHNIQUES FOR BCD TO BINARY
CONVERSION
A. 4-BIT GROUPING:
In this scheme the size of the group is 4 bits (1 BCD
digit). The scheme is outlined in Fig. 2 where WD0 is used to
represent the size of the output of the D0 contribution
generator unit, WD1 is used to represent the size of the output
of the D1 contribution generator unit, and so on. The BCD
input size is N BCD digits, DN-1 DN-2….. D1 D0, each digit is
fed to its corresponding contribution generator unit that
computes the contribution of that digit to the final binary
result. The contribution of D0 is the same four bits
representing D0.
From the table, we can derive the equations for these bits as
follows:
wd3[0]=0
wd3[1]=0
wd3[2]=0
wd3[3]=A0
wd3[4]=A1
wd3[5]=A3`A2`A0`+A2A0`A3`+A0A1`A2`A3
wd3[6]=A3`A2`A1`A0+A0`A1`A2`A3+A0`A1A3`+A1A2A3
wd3[7]=A3`A2A1`+A0A2`A3`+A1A2`A3`+A0A1`A3`
wd3[8]=A1`A2`A3+A1`A2A3`+A0A1`A3`+A1A3`
wd3[9]=A0A3`+A2A3`+A0`A1A3`+A1`A2`A3
wd3[10]=A0`A1A3`+A0`A1`A2A3`+A0`A1`A2`A3
wd3[11]=A0A1A3`+A0`A1`A2A3`+A0`A1`A2`A3
wd3[12]=A1A2A3`+A0A2A3`+A0`A1`A2`A3
wd3[13]=A0A1`A2`A3
Where A3, A2, A1, A0 are the 4-bit BCD
representation of D3. These Boolean functions represent the
contribution generation box corresponding to D3 among the
contribution generation boxes shown in Fig. 2.
For example, a (4)10 = (0100) BCD contributes
(0100)2 to the final binary result. D1 contributes the binary
equivalent of 10xD1 to the final binary result. In general, Di
contributes the binary equivalent of 10ixDi. We list the
contributions for each digit to the final result and derive the
Boolean functions that compute these contributions. Table 1
lists these contributions for the digit D3 as an example. For the
invalid inputs (greater than 1001), the functions’ outputs are
don’t care. As shown, D3’s contribution to the final binary
result WD3 is 14 bits in size
Fig.2 Architecture for 4-Bit grouping
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We note that a digit at position i contributes wdi to
the final binary results with size WDi where WDi =
[log2(9x10i)]+1 bits , i=0,1,….N-1 and the final binary result
w requires W bits where W = [log2(10N-1)]+1 bits,
An example to illustrate the 4-bit grouping approach
is shown in Fig. 3. In this example, the input size is 8 BCD
digits (i.e., eight 4-bit groups). The binary contribution of each
group is first generated and then all these contributions are
added using the binary addition stage to generate the binary
equivalent.
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whereas the most significant four bits can be any BCD digit
(0–9). It should be pointed out that the size of the most
significant group in this scheme can be 6 bits, 4 bits, or 2 bits
according to the number of BCD digits in the input. When
converting the decimal equivalent of each group to binary, the
least significant K bits of the binary equivalent are zeros. K
increases according to the position of the group from right to
left. For a given group Gi, Ki is calculated using the following
equation:
Ki = 3i/2,
i even
Ki = 3i+1/2, i odd
Also, the size of the binary equivalent of each group
increases according to the position of the group from right to
left. If the size of the binary equivalent of group Gi is WGi,
then WGi is calculated using the following equation:
WGi= [log2(39x103i/2)]+1 i even
WGi= [log2(98x103i-1/2)+1 i odd
Fig.3 An example to illustrate the approach 4-Bit grouping
B. 6-BIT GROUPING
In this scheme, the size of each group is 6 bits (1.5
BCD digits). The BCD input size is N BCD digits DN-1 DN-2 . .
. D1 D0. The groups are referenced as G0, G1, G2…. Gm, where
m=[2N/3-1]. For an even integer i, the least significant four
bits of group Gi are composed of the BCD digit D3i/2 . On the
other hand, the most significant two bits of group Gi are the
least significant two bits of the BCD digit D3i/2+1. For an odd
integer i, the least significant two bits of group Gi are
composed of the most significant two bits of the BCD digit D
3i-1/2, while the most significant four bits of group Gi are the
BCD digit D 3i-1/2+1.
Given a group Gi, if i is even then the greatest
decimal value of the group is 39x103i /2 . This is because the
most significant two bits of the group comes from the least
two bits of a BCD digit. Therefore, they can be only 00, 01,
10, 11 in binary or 0, 1, 2, 3 in decimal whereas the least
significant four bits can be any BCD digit (0–9).
Fig.4 An example to illustrate the approach of 6-Bit grouping
The Boolean equation of each bit in the binary
equivalent of group Gi is formulated based on the different
combinations of the group and its position among all groups.
An example to illustrate the 6-bit grouping approach is shown
in Fig. 4. In this example, the input size is 9 BCD digits (i.e.,
six 6-bit groups). The decimal equivalent of each group is
formed based on the 2 and 4 bits that compose the group as
has been mentioned. The binary contribution of each group is
first generated and then all these contributions are added using
the binary addition stage to generate the binary equivalent.
C. 8-BIT GROUPING
On the other hand, if i is odd then the greatest
decimal value of the group is 98 x103i-1/2 . This is because the
least significant two bits of the group come from the most
significant two bits of a BCD digit. Therefore, they can take
values of 00, 01, and 10 in binary or 0, 4, and 8 in decimal
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In this approach the size of the group is 8 bits (2
BCD digits). The number of groups in this case is [N/2].
Group Gi is composed from the BCD digit D2i that lies in the
right hand side of the group and the BCD digit D2i+1 that lies
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in the left hand side of the group. The largest decimal
equivalent of Gi is 99x102i. If the size of the binary equivalent
of group Gi is WGi then WGi is given by [log2(99x 102i)] + 1
and the number of the least significant bits in the binary
equivalent of group Gi that are zeros is 2i. The size of the
most significant group in this scheme can be 8 bits, or 4 bits
according to the number of BCD digits in the input.
IV. SIMULATION AND IMPLEMENTATION RESULTS
A. SIMULATION RESULT
Fig. 9 Simulation output for 8-Bit Grouping Method (for 8
BCD Digit Input)
This section explains the simulation results
EXPANDING METHOD:
Input= (99999999)10
= (10011001100110011001100110011001)BCD
Output=(101111101011110000011111111)
Fig. 10 RTL schematic view of 4-bit grouping method (4 BCD
Digit)
V. AREA AND DELAY ANALYSIS
Fig. 6 Simulation output for Expanding Method (for 8 BCD
Input)
We evaluate the area and delay for existing
expanding method and also 4-Bit, 6-Bit, 8-Bit groupings on
Spartan-3, Spartan-3E, Spartan-6, Virtex-4, Virtex-5, Virtex-6,
Virtex-7 FPGAs with 2-digit, 4-digit, 8-digit BCD input.
Table 3 shows the specifications of each FPGA which we used
for simulation
Fig. 7 Simulation output for 4-Bit Grouping Method (for 8
BCD Digit Input)
Fig. 11 Technology schematic view of 4-Bit grouping (4 BCD
Digit)
Fig.8 Simulation output for 4-Bit Grouping Method (for 8
BCD Digit Input)
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B. IMPLEMENTATION RESULT
Fig. 12 Implementation Setup with Spartan-3 FPGA kit
Fig.14 Delay (in ns) Comparison of different schemes on
different FPGA families
Fig. 13 Binary output of 1910(000100112) in Spartan-3 FPGA
kit
Table 3 Various FPGA Specification which used for
simulation
A. COMPARISON OF THE VARIOUS GROUPING
SCHEMES
The performance of a particular scheme on a
particular FPGA architecture is affected by the performance of
contributions generation stage and the performance of the
addition stage. Larger bit grouping may require a hierarchy of
LUTs on FPGAs with smaller size LUTs which may result in
poor contributions generation performance. On the other hand,
larger grouping requires smaller number of levels in the
addition stage and less number of adders in each level with
larger adder sizes.
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Fig.15 Delay (in ns) Comparison of different schemes on
different FPGA families
Fig. 16 Growth in delay (in ns) of expanding method as the
number of BCD digits to be converted to binary grows in
various FPGA Families
Conversely, smaller bit grouping may result into each
bit of the contributions generation stage fit into one LUT (i.e.,
may eliminate the need for a LUT hierarchy) with the penalty
of requiring larger number of levels and larger number of
smaller-size adders per level in the addition stage. Therefore,
it is not clear beforehand which bit grouping will win on a
particular architecture especially that the routing delay may
contribute significantly to the overall system delay. Figure 1112 show growth in delay and device utilization of the
Expanding method, 4-Bit, 6-Bit and 8-Bit grouping techniques
for 8-digit BCD input. Table 4 shows delay of various
methods in ns. Table 5 represents No of 4 input LUTs (area)
used in various methods.
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grouping is better than the 6-bit grouping on Virtex-5. The
same does not hold true for Virtex-6 and Virtex-7.
Fig. 17 Growth in delay (in ns) of 4-Bit grouping method as
the number of BCD digits to be converted to binary grows in
various FPGA Families
Fig. 19 Growth in delay (in ns) of the 8-Bit grouping method
as the number of BCD digits to be converted to binary grows
in Various FPGA Families
Fig. 18 Growth in delay (in ns) of the 6-Bit grouping method
as the number of BCD digits to be converted to binary grows
in Various FPGA Families
On Virtex-4, Spartan-3, Spartan-3E (4-input LUT
FPGAs) the best grouping is 2 BCD digit followed by 1.5
BCD and then 1 BCD digit. This indicates that the
performance gain achieved by fitting each bit in the
contributions into one LUT overweighs the performance
losses caused by a larger binary addition hierarchy. The same
observation holds true for the area performances of the
schemes. On 6-input LUT FPGAs (Virtex-5, Virtex-6 and
Virtex-7), the delay and area (in terms of the number of LUTs)
of the 6-bit grouping is more or less similar to that of the 4-bit
grouping. We note though that in the case of 4-bit grouping on
6-input LUTs, the utilization of the LUTs is very low. While
the 6-bit grouping beats the 4-bit grouping in terms of area on
the three 6-input LUTs FPGAs we use, the delay of 6-bit
grouping is better in some cases and worse in others than that
of 4-bit grouping. This indicates that some FPGA devices
optimize the routing delay better than others for our
architectures. For example, despite the fact that 6-bit grouping
results into smaller number of levels in the binary addition
stage than the 4-bit grouping, the overall delay of the 4-bit
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Fig. 20 Delay (in ns) Comparison for all methods as Input
BCD grows in Spartan-3 FPGA Family
Fig. 21 Comparison of no of 4 Input LUTs used in various
methods for Spartan-3 FPGA
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As a general note, the area of our schemes grows
exponentially as the number of digits increases whereas the
delay grows in a logarithmic fashion.
Fig. 23 Growth in area (in no of 4 Input LUTs) of the
expanding method as the number of BCD digits to be
converted to binary grows
Fig. 22 Comparison of no of 4 Input LUTs used in various
methods for Spartan-3E FPGA
Fig. 24 Growth in area (in no of 4 Input LUTs) of the 4-Bit
grouping method as the number of BCD digits to be converted
to binary grows
Table 4 Delay in nS (Used No. of 4 Input LUTs) for all methods
Table 5 Device Utilization (Used No. of 4 Input LUTs) for all methods
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Fig. 25 Growth in area (in no of 4 Input LUTs) of the 6-Bit
grouping as the number of BCD digits to be converted to
binary grows
Fig. 26 Growth in area (in no of 4 Input LUTs) of the 8-Bit
grouping as the number of BCD digits to be converted to
binary grows
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[2]
M.F. Cowlishaw, Decimal floating-point: algorism for
computers, in: Proceedings of the 16th IEEE Symposium
on Computer Arithmetic (ARITH16’03), ARITH ’03,
IEEE Computer Society, Washington, DC, USA, 2003,
p. 104.
[3]
G. Jaberipur, A. Kaivani, Binary-coded decimal digit
multipliers, computers digital techniques, IET 1 (2007)
377–381.
[4]
R. James, T. Shahana, K. Jacob, S. Sasi, Decimal
multiplication using compact BCD multiplier, in:
International Conference on Electronic Design, 2008,
ICED, 2008, pp. 1–6.
[5]
A. Singh, A. Gupta, S. Veeramachaneni, M.B. Srinivas,
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BCD
and
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M. Vazquez, G. Sutter, G. Bioul, J.P. Deschamps,
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VI. CONCLUSION
A range of efficient decimal-to-binary conversion
schemes to support BCD arithmetic based on binary hardware
is presented. First, we split the BCD input into several groups
of bits and compute the binary contribution of each group to
the overall binary result. The contributions are then added
using binary addition in FPGAs. For the selection of the group
size, we select it such that it matches the size of the lookup
tables on the target FPGA. Due to this choice, each function
among the outputs of the circuit that computes the contribution
of a given group fits exactly in one look-up table which results
into a compact design. We demonstrate in this paper that the
proposed architecture outperforms existing architectures in
terms of area and speed. Furthermore, we have discussed in
this paper the growth in area and delay of the proposed
schemes on various FPGA families as the number of BCD
digits in the input grows. The general conclusion is that the
area grows in an exponential fashion whereas the delay grows
in a logarithmic fashion.
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