Decimal Floating-Point Adder
INVENTORS • Michael Schulte, John Thompson, Nandini Jairam
WARF: P04245US
View U.S. Patent No. 7,546,328 in PDF format.
Since its founding in 1925 as the patenting and
licensing organization for the University of Wisconsin-
The Wisconsin Alumni Research Foundation (WARF) is seeking commercial
partners interested in developing a decimal floating-point adder that rapidly
performs decimal floating-point arithmetic, particularly addition and
subtraction.
Madison, WARF has been working with business and
industry to transform university research into products
that benefit society. WARF intellectual property
managers and licensing staff members are leaders in
the field of university-based technology transfer. They
are familiar with the intricacies of patenting, have
OVERVIEW
worked with researchers in relevant disciplines,
understand industries and markets, and have
negotiated innovative licensing strategies to meet the
Although most people use decimal arithmetic when performing calculations, computer
hardware usually only supports binary arithmetic. Numbers are typically input in decimal
form, converted to binary for processing, and then converted back to decimal for output.
However, converting between binary and decimal floating-point numbers is
computationally intensive, and many common decimal numbers cannot be represented
exactly in binary, leading to errors. Software packages for decimal arithmetic have been
developed, but they are often hundreds or even thousands of times slower than binary
operations in hardware.
individual needs of business clients.
THE INVENTION
UW-Madison researchers have developed a decimal floating-point adder that rapidly
performs decimal floating-point arithmetic, particularly addition and subtraction. The
decimal floating-point adder includes an alignment unit that aligns the significands (the
part of a decimal floating-point number that contains its significant digits) of two floatingpoint numbers so that the exponents associated with the floating-point numbers have
equal values. For example, the numbers 12.3 and 4.56 could be represented as 1230 X
10-2 and 456 X 10-2. A binary adder then adds the aligned significands. A correction unit
and an output conversion unit are included in the floating-point adder to produce the final
decimal floating-point number.
APPLICATIONS
• Numerically intensive commercial applications
Wisconsin Alumni Research Foundation | 614 Walnut Street, 13th Floor | Madison, WI 53726 | licensing@warf.org | www.warf.org
WARF: P04245US
KEY BENEFITS
• Faster than current decimal arithmetic software or hardware
• May be pipelined so that complete resultant decimal floating-point numbers are output each clock cycle
ADDITIONAL INFORMATION
Related Technologies
See WARF reference number P04398US for techniques for decimal floating-point division.
See WARF reference number P04399US for techniques for rapid decimal multioperand addition.
Tech Fields
Information Technology - Computing methods
CONTACT INFORMATION
For current licensing status, please contact Scott Pollyea at spollyea@warf.org or 608-890-2930.
Wisconsin Alumni Research Foundation | 614 Walnut Street, 13th Floor | Madison, WI 53726 | licensing@warf.org | www.warf.org