Geiger Mode Avalanche Photodiode with
CMOS Transimpedance Amplifier for
Optical Data Link Applications
A.M. Moloneya, A.P. Morrisona, J.C. Jacksonb, A. Mathewsonb and P.J. Murphyb
Department of Electrical and Electronic Engineering, University College Cork, Ireland
b
National Microelectronics Research Centre, ‘Lee Maltings’, Prospect Row, Cork. Ireland
a
Abstract – Simulations of the first realisation of a detector receiver combination based on
the Geiger mode avalanche photodiode (GMAP), which is an avalanche photodiode
compatible with a 1.5 m CMOS and SOI CMOS process, are presented. The receiver
design and simulations are achieved using a 1.5 m CMOS process. The simulations
incorporate ADS Level 3 model sets. Two receivers are simulated a dynamic and a nonadjustable both receivers are shown to work well to 1 Gb/s.
1 INTRODUCTION
High volumes of optoelectronic integrated circuits (OEICs) will be needed in the coming years
for optical interconnect, optical storage systems (CD-ROM, DVD), optical data links for use in
Local Area Networks (LANs), home networking, Fibre-to-the-Home (FTTH) and backbone
interconnect. To be competitive with copper technology for links and bus applications these
OEICs must be affordable therefore the high-speed, high-sensitivity III-V material systems
which have long been used for high-performance long-haul communication systems are not an
option. The growing need for such OEICs along with the low-cost of silicon and its potential
for very large scale integration has prompted a search for a monolithically integrated silicon
photoreceiver suitable for gigabit-rate data transmission. The most challenging aspect of
fabricating a high-performance monolithic silicon photoreceiver is the integration of a highspeed, high-sensitivity photodetector and an amplifier without adding complexity to the
existing transistor fabrication process [1]. Many different photodiodes have been successfully
integrated with silicon electronic circuitry to date. Schow et al have reported a lateral
interdigitated p-i-n photodiode integrated with an NMOS transimpedance preamplifier on bulk
silicon this reached a speed of 1 Gb/s [2] while on SOI substrate the receiver operated at 2 Gb/s
[1]. Heide integrated vertical p-i-n photodiodes in a twin-well 1.0 m CMOS process the
OEICs fabricated handled a data rate of 622 Mb/s with a single supply voltage of 3.3 V [3]. A
CMOS photodiode consisting of a standard CMOS N-well with an interdigitated network of Pdiffusion fingers was used by Woodward to form a monolithically integrated photoreceiver
with a sensitivity of -6.3 dBm at 1 Gbit/s [4]. A spatially modulated light detector (SMLdetector) with sense-amplifier receiver in standard 0.8 m CMOS operating at 180 Mb/s was
presented by Kuijk et al [5], while Fang et al integrated an amorphous silicon p-i-n photodiode
with a crystalline silicon n-p-n transistor and formed a photoreceiver [6].
This paper proposes that Geiger mode avalanche photodiodes that are CMOS and siliconon-insulator (SOI) CMOS compatible, have high gain and high responsivity are viable
candidates for use in gigabit, monolithically integrated, low-cost, high-reliability, silicon
photoreceivers. Simulations of transimpedance amplifiers incorporating the GMAPs are
presented here.
2 PHOTODETECTOR
The photodetector used in the simulations is the Geiger-mode avalanche photodiode (GMAP).
The GMAPs shown in Figure 1 with 20 m junction active areas and different overlap
dimensions were fabricated. Details of the fabrication of the GMAPs have been reported
previously [7]. The anode doping was tailored to provide the low (< 30 V) breakdown voltage.
The fabricated GMAPs have shown high responsivity (0.04 A/W at 5 V reverse bias, 0.4 A/W
at 27 V reverse bias), high gain (10 at 27 V, 100 at 27.25 V and in excess of 1000 at 27.5 V
reverse bias) and low dark current (5 pA at 5 V reverse bias 33 pA at 27.5 V reverse bias
corresponding to 7 fA/m2 and 47 fA/m2 respectively). The s-parameters for a 20 m
diameter GMAP with a 3 m junction overlap were used to develop a small signal equivalent
circuit - from which a bandwidth of 5.95 GHz for the photodetector was calculated [8].
A
n
ode
C
ath
ode
C
ath
ode
A
n
ode
O
xide
P+
N
+
P
P+
O
verlap
A
ctiveA
rea
P-Ep
i
P+S
u
bstrate
Figure 1Virtual guard ring GMAP structure showing active area and overlap region
The GMAP was implemented in the simulations using a capacitor. A GMAP has three
associated capacitances, bondpad capacitance, metal contact capacitance and depletion
capacitance. Since the simulations are of a monolithically integrated photoreceiver that is the
photodiode and receiver are on the same silicon substrate, there will be no metal contact and
bondpad capacitance and the capacitance of the GMAP is simply the depletion capacitance.
The capacitance was calculated using the SPICE level 3 (geometric junction model) equation
for depletion capacitance [9]. The depletion capacitance is modelled by junction bottom and
junction periphery capacitances. The formula for bottom area (Equation 1) and periphery
(Equation 2) capacitances is similar except each has its own model parameters. The model
parameters (Cj, Cjsw, mj, mjsw, j) have been previously extracted [7]. Each GMAP consists of
two bottom area capacitances (active area and overlap regions) and one periphery capacitance
(where N+ and P-epi meet) which are all in parallel and may be summed. Calculated
capacitances for a reverse bias voltage of –27 V are shown in Table 1 and Table 2. All the
capacitances are low (< 200 fF) and will not limit the speed of the amplifier excessively.
Carea (V ) 
C per (V ) 
Cj
 V
1 
 j



mj
C jsw P
 V
1 
 j



m jsw
(1)
(2)
where:
Cj = zero-bias junction capacitance per unit junction bottomwall area
A = junction area
Cjsw = zero-bias junction capacitance per unit junction periphery
P = junction perimeter
j = area junction contact potential
mj = area junction grading coefficient
mjsw = periphery junction grading coefficient
V = magnitude of the bias voltage
Table 1 Calculated GMAP capacitances with active area diameter = 20 m
Table 2 Calculated GMAP capacitances with active area diameter = 10 m
3 RECEIVER
The three basic preamplifier topologies commonly used for integrated photoreceivers are: 1)
the simple resistor terminated design, 2) the high-impedance (HZ) design and 3) the
transimpedance design. The transimpedance architecture has been chosen for this work since it
has been demonstrated as being the most suitable solution for a preamplifier for front-end
optical receiver circuits. TZ amplifiers present advantages of simplicity, high-bandwidth and
large dynamic range [10]. The f3dB of a TZ amplifier with a single dominant input pole is given
by Equation 2.
f3dB 
Av  1
2 R fb (Cin  C fb (1  Av ))
(3)
where:
Av = open-loop voltage gain of the voltage amplifier
Rfb = feedback resistance
Cfb = parasitic shunt capacitance across feedback resistor
Cin = input capacitance to the voltage amplifier (FET gate capacitance + photodiode
capacitance)
The feedback resistance Rfb must be kept large for low Johnson noise and hence good receiver
sensitivity therefore all capacitance must be as low as possible particularly that of the
photodetector (the dominant capacitance) to ensure high bandwidth.
Vdd
Cpd
M2
V1
M1
6.0/1.5
V2
2.0/1.5
2.0/1.5
2.0/1.5
M1
Mfn
2.0/1.5
Vdd
Cpd
M4
Vout
V1
6.0/1.5
V2
2.0/1.5
2.0/1.5
2.0/1.5
M2
M3
M4
Vout
M3
Mfn
2.0/1.5
Vt
Mfp
Mfp
2.0/1.5
2.0/1.5
Figure 2 (a) Circuit schematic of dynamic photoreceiver. (b) Circuit schematic of non-adjustable
photoreceiver
The HP ADS (Advanced Design System) simulator was used to establish the CMOS large
signal model and to evaluate the performance of the photoreceiver. ADS level 3 MOSFETs
were built using extracted SPICE level 3 model sets for the 1.5 m CMOS process. Figure 2
shows the circuit schematics for the dynamic and non-adjustable receivers respectively. The
photoreceiver preamplifiers are similar in design to those reported by A.V. Krishnamoorthy et
al [11] for optoelectronic-very-large-scale integration (OE-VLSI). The GMAP is modelled by
an AC-current source and capacitor. The receivers consist of transimpedance front-ends
followed by a decision stage. The transimpedance stage (M1, M2, Mfn and Mfp) incorporates a
CMOS inverter (M1 and M2), the large signal transfer characteristic of which shows a gain of
10.2 approximately (see Figure 3). For operation as an inverting small-signal voltage amplifier,
the inverter is biased in the high-slope region of the transfer characteristic using the
transimpedance feedback resistance. Feedback in the dynamic circuit is achieved using a
parallel combination of a common-gate NMOSFET and a saturated PMOSFET. The gate
voltage of the NMOSFET can be adjusted to give a feedback resistance which allows optimum
performance at a given bit-rate and optical power. Feedback is accomplished in the nonadjustable receiver using a diode connected NMOSFET and a parallel saturated PMOSFET.
The second stage of the photoreceivers (M3 and M4) is an inverter which acts as a decision
stage with a switching voltage of 2.1 V, this stage generates a logic level output.
5
Output (V)
4
3
2
1
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Input (V)
Figure 3 Large-signal transfer characteristic of CMOS inverter (M 1 and M2)
4
Output
Input
Voltage (V)
3
V1
2
Vout
1
0
0
2
4
6
8
10
Time (ns)
Figure 4 Simulation of the dynamic transimpedance photoreceiver at 1Gb/s with peak input current of 40
A. Photodiode capacitance is 75 fF, Vt=3.0 V and Vdd=5.0 V.
4
Output
Input
Voltage (V)
3
V1
2
Vout
1
0
0
2
4
6
Time (ns)
8
10
Figure 5 Simulation of the non-adjustable transimpedance photoreceiver at 1Gb/s with peak input current
of 40 A. Photodiode capacitance is 75 fF and Vdd=5.0 V.
Figures 4 and 5 show the simulated transient characteristics of the transimpedance receivers
at 1 Gb/s (500 MHz). The photodiode capacitance for both receivers was taken to be 75 fF
since simulations showed that to reach gigabit speed the capacitance had to be  75 fF (it can
be seen from Table 2 that this capacitance can be obtained for an active area diameter of
10m). At this bit-rate the feedback resistance of the dynamic receiver was 20.1 k and of the
non-adjustable was 20.6 k these resistances were calculated using Equation 4 where Id is the
photodetector current.
V2  V1
Id
(4)
4 CONCLUSION
Simulations of the first monolithic detector/receiver in a CMOS process based on the GMAP
detector are presented showing stable operation to 1 Gb/s. Much higher bit rate operation of
receivers based on the GMAP can be expected with the use of a submicron CMOS process.
Many optoelectronic applications can profit from this novel photoreceiver concept.
5 ACKNOWLEDGEMENTS
The authors wish to acknowledge the National Microelectronics Research Centre (NMRC)
Ireland for the use of the Spice level 3 model sets and Dr. Kevin McCarthy, UCC for advice on
the 1.5 m CMOS process.
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