Project Title:
TCC TUNABLE MULTIPURPOSE CMOS CLASSIFIER CIRCUITS
Abstract
In the everyday life of humans, to define the rules used to recognize a certain sound, image or
an analog data necessitates a sequence of complex processes and sometimes it even becomes
impossible. However, to develop well-defined software and hardware based criteria in the application
of pattern recognition problems, is possible. The aim of classification can be defined as to assign an
unknown object to a class containing similar objects (or to distinguish objects having the same
properties from those not possessing). Classification is used in a huge variety of applications such as
automatic target identification, artificial intelligence, artificial neural networks, analog to digital
converters, quantization, medical diagnosis, statistics etc.
Therefore nowadays, be it in the real or digital world, classification of data is becoming
increasingly important. But until recently, major work on classification was on developing algorithms
used in software packages whereas, in many applications it is becoming more and more important to
classify data much faster and in real time, entailing the need for hardware realization of these
algorithms. The recent developments in electronic technology has created a perfect medium for the
hardware realization of classifier structures which, in turn, will render many classifier application
prospects feasible in real time.
This project targets the design, realization, adaptation and application to real world problems
of high speed, tunable, trainable new classifier circuits using CMOS (BiCMOS) technology.
With the above purpose in mind, in the hardware related part of the project the concept of
“core-cell”, a single-input single-binary-output classifier which can be viewed as a building block for
the whole system, will be introduced. In order for this core-cell to be adaptable, special care will be
exercised to design it with externally tunable input-output-determining parameters. Once some
satisfactory designs are reached, the architecture of a multi-input multi-output classifier consisting of
core-cells will be developed and decided upon. Then both, the core-cell and the architecture will be
realized at transistor level in CMOS (BiCMOS) technology, tested with simulations and improved with
respect to low power consumption, small delay and low complexity. The final classifier circuit will be
realized this time with discrete components, the compatibility of results from simulations and
measurements will be checked and possible discrepancies diminished.
In the final step concerning hardware, the layout of the last classifier circuit at transistor level
will be obtained, tested with simulations and improved after several iterations until one satisfying the
desired properties is reached. At this stage, it is expected that user-parameter-tunability will be the
main factor forcing the layout design. For multi-input multi-output classifiers, it is envisaged to embed
a serial-input parallel-output memory-like unit into the design. After all desired properties are satisfied
and the layout verified the final design will be prototyped.
The software related part of the project will be concerned with the development of the training
algorithms for the tunable parameters of the classifier. With the aid of the developed software package
the user will determine the values for the tunable parameters using the training set pertaining to the
desired application and tune them externally to adjust the classifier to meet the requirements of the
application.
As the development of the software stage concerning training is independent of the hardware
realization the algorithms will be matured in parallel with the circuit design of the classifier in
conjunction with application to recent problems such as pattern recognition, diagnosis, analog to
digital converters etc.; if need be, pro- and post- processor blocks for these applications will also be
designed. As concurrent development of hardware and software is being employed, it will be possible
to incorporate the pre- and post-processing blocks into the layout.
Results and developments obtained from the developments and research will be discussed at
international platforms by attending conferences and the feedback received will help to ameliorate the
design of the classifier circuits and final findings will be published scientific journals covered by SCI.
Keywords: CMOS, Classifier, Analog/Digital Converter, Quantizer, Tuning