TR-30.2/01-03-002
TR-30.1/01-03-002
ELECTRICAL CHARACTERISTICS OF MULTIPOINT-LOW-VOLTAGE
DIFFERENTIAL SIGNALING (M-LVDS)
INTERFACE CIRCUITS FOR MULTIPOINT DATA INTERCHANGE
SP-4828
March 2001
1
SP-4828
2
SP-4828
ELECTRICAL CHARACTERISTICS OF MULTIPOINT-LOW-VOLTAGE
DIFFERENTIAL SIGNALING (M-LVDS)
INTERFACE CIRCUITS FOR MULTIPOINT DATA INTERCHANGE
Table of Contents
1
SCOPE .................................................................................................................... 1
2
DEFINITIONS, SYMBOLS, AND ABBREVIATIONS ............................................... 1
3
APPLICABILITY ...................................................................................................... 2
3.1 General applicability ...................................................................................................................... 2
3.2 Signaling rate.................................................................................................................................. 4
3.3 Transmission distance .................................................................................................................. 5
4
ELECTRICAL CHARACTERISTICS........................................................................ 5
4.1
4.2
4.3
4.4
5
Driver characteristics..................................................................................................................... 5
Receiver characteristics .............................................................................................................. 12
Interchange input impedance ..................................................................................................... 15
Interconnecting media electrical characteristics ...................................................................... 20
SYSTEM CONSIDERATIONS ............................................................................... 20
5.1
5.2
5.3
5.4
Failsafe operation ........................................................................................................................ 20
Transient protection .................................................................................................................... 21
Signal common (ground) ............................................................................................................. 21
Noise budgeting ........................................................................................................................... 23
ANNEX A (INFORMATIVE) .......................................................................................... 26
A.1 Interconnecting cable .................................................................................................................... 26
A.2 Additional characteristics.............................................................................................................. 26
A.3 Length ............................................................................................................................................. 26
A.4 Typical cable characteristics ........................................................................................................ 26
A.5 Cable length vs. signaling rate guidelines .................................................................................. 28
ANNEX B (INFORMATIVE) .......................................................................................... 30
ANNEX C (INFORMATIVE) .......................................................................................... 33
C.1 Related TIA/EIA standards ............................................................................................................ 34
C.2 Other related interface standards ................................................................................................. 34
ANNEX D (INFORMATIVE) .......................................................................................... 35
List of Figures
FIGURE 1 - MULTIPOINT APPLICATION OF M-LVDS INTERFACE CIRCUITS........................................ 3
i
SP-4828
FIGURE 2 – TWO-CIRCUIT APPLICATION OF M-LVDS. ........................................................................... 3
FIGURE 3 - MAXIMUM SIGNALING RATE CALCULATION........................................................................ 4
FIGURE 4 – DRIVER OUTPUT VOLTAGE AND CURRENT DEFINITIONS. .............................................. 5
FIGURE 5 - DRIVER OUTPUT SIGNALING SENSE. .................................................................................. 6
FIGURE 6 - DIFFERENTIAL OUTPUT VOLTAGE TEST CIRCUIT. ............................................................ 7
FIGURE 7 - OUTPUT VOLTAGE TEST CIRCUIT........................................................................................ 8
FIGURE 8 - DRIVER OFFSET VOLTAGE TEST CIRCUIT.......................................................................... 8
FIGURE 9 - DRIVER SHORT-CIRCUIT TEST CIRCUIT. ............................................................................ 9
FIGURE 10 - DRIVER OUTPUT SIGNAL WAVEFORM. ........................................................................... 11
FIGURE 11 - DYNAMIC DRIVER OUTPUT BALANCE MEASUREMENT................................................. 12
FIGURE 12 - RECEIVER VOLTAGE AND CURRENT DEFINITIONS. ...................................................... 12
FIGURE 13 - RECEIVER DIFFERENTIAL INPUT VOLTAGE THRESHOLD REQUIREMENTS. ............. 13
FIGURE 14 – TYPE-1 RECEIVER INPUT VOLTAGE RANGE. ................................................................. 14
FIGURE 15 – TYPE-2 RECEIVER INPUT VOLTAGE RANGE. ................................................................. 15
FIGURE 16 - ALLOWED STEADY-STATE INPUT CURRENT VERSUS INPUT VOLTAGE. ................... 16
FIGURE 17 - DIFFERENTIAL INPUT CURRENT TEST. ........................................................................... 17
FIGURE 18 - VOLTAGE AND CURRENT DEFINITIONS FOR TERMINATING INTERCHANGES. ......... 18
FIGURE 19 - OPTIONAL GROUNDING ARRANGEMENT A. ................................................................... 22
FIGURE 20 - OPTIONAL GROUNDING ARRANGEMENT B. ................................................................... 23
FIGURE 21 - OPTIONAL GROUNDING ARRANGEMENT C. ................................................................... 23
FIGURE 22 - SIGNALING RATE VERSUS CABLE LENGTH FOR A 5% EYE-PATTERN JITTER. ......... 29
FIGURE 23 - VOLTAGE RANGES OF DIFFERENTIAL INTERFACE STANDARDS. ............................... 34
List of Tables
TABLE 1 - RECEIVER INPUT VOLTAGE THRESHOLD REQUIREMENTS ............................................. 13
TABLE 2 - TYPE-1 RECEIVER NOISE BUDGET EXAMPLE. ................................................................... 24
TABLE 3 - TYPE-2 RECEIVER NOISE BUDGET EXAMPLE. ................................................................... 24
ii
SP-4828
FOREWORD
(This foreword is not part of this Standard)
This Standard was formulated under the cognizance of TIA Subcommittee TR-30.2 on
Data Transmission Interfaces.
This Standard specifies low-voltage differential signaling drivers and receivers for data
interchange across half-duplex or multipoint data bus structures. M-LVDS is capable of
operating at signaling rates up to 500 Mb/s. Devices may be designed for signaling
rates less than 500 Mb/s, 100 Mb/s for example, when economically or technically
required for that application.
This Standard was developed in response to a demand from the data communications
community for a general-purpose high-speed balanced interface standard for multipoint
applications. The voltage levels are specified such that maximum flexibility would be
provided, while providing a low-power high-speed differential interface. Driver output
characteristics are independent of power supply, and may be designed for standard
5 V, 3.3 V or lower power supplies. The requirements of this standard may be
implemented with any integrated circuit technology, such as BiCMOS, CMOS, or GaAs
technology. The low-voltage (565-mV typical) swing reduces power dissipation and the
potential for radiated emissions. Differential signaling provides multiple benefits over
single-ended signaling, notably common-mode rejection and magnetic field
cancellation.
The electrical signal levels are similar to those described in the TIA/EIA-644 standard,
and will interoperate with certain interchange circuits and signaling rates.
This Standard includes four informative Annexes. Annex A provides guidelines for
application, addressing signaling rate and cable length issues. Annex B covers printedcircuit board guidelines. Annex C provides comparison information with other interface
standards and references to this Standard. Annex D provides a derivation of the
formula for approximating the bus loading effects.
iii
SP-4828
1
SCOPE
This Standard specifies the electrical characteristics of low-voltage differential signaling
interface circuits that may be employed when specified for the interchange of binary
signals between equipment sharing a common data interchange circuit. The electrical
characteristics of the circuit are specified in terms of required voltage and current
values obtained from direct measurements of the driver and receiver components at the
multipoint line interface points.
The logic function of the driver and the receiver or the communication protocol is not
defined by this Standard, as it is application dependent. Optional receiver input
characteristics are specified to allow idle-line fail-safe or Wired-or signaling at slower
signaling rates.
Minimum electrical characteristics of the transmission media and interconnection
requirements are provided, where media refers to printed circuit board traces
(backplane) or cables. Further guidelines for application of this Standard are provided in
the annexes.
It is intended that this Standard will be referenced by other standards that specify the
complete interface (i.e., connector, pin assignments, function) for applications where
the electrical characteristics of a multipoint low-voltage differential interface circuit is
required. The referencing standard(s) also specify other characteristics of the interface
(such as signal quality, protocol, bus structure, and timing) essential for proper
operation across the interface.
When this Standard is referenced by other standards or specifications, it should be
noted that certain options are available. The author of those standards and
specifications must determine and specify those optional features that are required for
that application.
2
DEFINITIONS, SYMBOLS, AND ABBREVIATIONS
For the purposes of this Standard, the following definitions, symbols, and abbreviations
apply:
Bus. A bus is a common pathway or channel, between multiple devices. A single MLVDS interchange circuit.
Common-mode voltage. The common-mode voltage is equal to one half of the vector
sum of the voltages between each conductor of a balanced interchange circuit and
ground. The common-mode voltage is the sum of ground potential difference, driver
common-mode output voltage (driver offset voltage), and longitudinally coupled noise.
Idle line. An idle line is a multipoint line with all drivers off.
1
SP-4828
Inter-symbol interference. Inter-symbol interference is the time displacement of a
state transition due to a new wave (subsequent signal) arriving at the receiver site
before the previous wave has reached its final value.
Jitter. Jitter is the time variation of the instant a binary signal crosses a threshold (state
transition) from the ideal occurrence.
M-LVDS. Multipoint-Low-Voltage Differential Signaling
Multipoint. Multipoint refers to a communications line (network) that provides a path
from any one location to one or more.
Multipoint line. A multipoint line is a single line that interconnects two or more devices.
Point-to-Point. Point-to-point refers to a communications line that provides a
unidirectional path from one location to another (point A to point B).
Signaling rate. The signaling rate of a line, is the number of transitions (voltage or
frequency changes) that are made per second expressed in the units b/s (bits per
second). It may be different from the equipment’s data transfer rate, which employs the
same units.
Transition time. Unless otherwise specified, the transition time is the 10%-to-90% rise
or fall time of a binary signal.
Unit Interval. The unit interval (UI or tUI) is the mathematical inverse of the signaling
rate.
*. * (star) represents the opposite input condition for a parameter. For example, the
symbol Q represents the receiver output state for one input condition, while Q*
represents the output state for the opposite input state.
3
3.1
APPLICABILITY
General applicability
The provisions of this Standard may be applied to the circuits employed at the interface
between equipment where information being conveyed is in the form of binary signals.
The interface circuit (shown schematically in Figure 1) consists of a balanced
interconnecting media terminated at the ends by transmission-line termination
impedance (designated as Zt). There may be as many as thirty-two M-LVDS circuits
connected to the media at the interchange points.
This Standard specifies the electrical characteristics of the interchange points marked
A0, B0, and C0; A1, B1, and C1; and so on. The interconnected circuits may be a driver
(output only), receiver (input only), or transceiver (input and output).
2
SP-4828
Balanced Interconnecting
Media
A0
A1
An
Zt
Zt
B0
B1
Bn
Circuit 0
Circuit 1
Circuit n
C0
C1
Cn
Figure 1 - Multipoint application of M-LVDS interface circuits.
Balanced Interconnecting
Media
A0
Circuit 0
C0
A1
Zt
Circuit 1
Zt
B0
B1
C1
Figure 2 – Two-circuit application of M-LVDS.
The M-LVDS interface is intended for use where any of the following conditions prevail:
a) A multipoint LVDS connection is desired.
b) The signaling rate is too great for effective unbalanced (single-ended) operation.
c) The signaling rate exceeds the capability or system power constraints do not allow
use of a TIA/EIA-485 electrical interface.
d) The interchange circuit is exposed to noise sources that may cause a voltage of up
to ±1 V between circuit commons.
e) It is necessary to minimize electromagnetic emissions and interference with other
signals or the external environment.
3
SP-4828
3.2
Signaling rate
The M-LVDS interface circuit will normally be utilized on data, timing, or control circuits
where the signaling rate is up to a maximum limit of 500 Mb/s. This limit is determined
by the driver output transition times, the media characteristics, and the distance
between the driver and the load. Certain applications may impose a different (lower or
higher) limit for the maximum signaling rate. This may be accomplished by specifying a
different minimum driver transition time specification, a different percentage of transition
time vs. unit interval at the load, or by a different assumption of the maximum balanced
interconnecting media signal distortion.
The maximum limit is calculated at 500 Mb/s and is derived from a calculation of signal
transition time at the load assuming a loss-less balanced interconnecting media. The
recommended signal transition time at the load should not exceed 0.5 of the unit
interval , which should keep jitter from intersymbol interference to less than 5% of the
unit interval. This Standard specifies that the transition time of the driver into a test load
be 1 ns or slower. Therefore, with the fastest driver transition time, and a loss-less
balanced interconnecting media, and applying the 0.5t UI restriction, yields a minimum
unit interval of 2 ns or 500 Mb/s maximum signaling rate (see Figure 3).
Loss-less media
VZ
VX
VX
tUI
1 ns
1 ns
90%
50%
10%
VZ
tUI = 2 ns
time
Figure 3 - Maximum signaling rate calculation.
NOTE - 500 Mb/s is the maximum signaling rate for a single line. Employing a
parallel multipoint line structure (4, 8, 16, 32, etc.), can easily extend the
obtainable data transfer rate into the Gb/s range.
Drivers, receivers, and transceivers meeting this Standard need not operate at the
maximum signaling rate range specified. They may be designed to operate at lower
4
SP-4828
signaling rates that satisfy specific applications. When a driver is limited to a narrower
range of signaling rates, the transition time of the driver may be slowed accordingly to
limit noise generation.
3.3
Transmission distance
A maximum length of the balanced media is not specified directly but is a function of
signal degradation and noise coupling. These, in turn, are functions of the signaling
rate, the balanced media characteristics, and the application environment. It is
anticipated that maintaining the required 1 V of ground potential separation between MLVDS circuits will be difficult at distances of greater than 100 m.
4
ELECTRICAL CHARACTERISTICS
The M-LVDS interface circuit consists of any combination of drivers (D), receivers (R),
or transceivers (T) up to a total of thirty-two (32), a balanced interconnecting media, and
termination. The following electrical characteristics of the interchange connection of
these components will allow electrical compatibility and interchangeability of compliant
components.
4.1
Driver characteristics
The fundamental characteristic of an M-LVDS driver is the generation of a monotonic
first-step differential voltage of at least 100 mV at any A and B interchange connection
to the balanced media. Other characteristics that affect system performance are the
common-mode output voltage, the maximum differential output voltage, the output
impedance, and the output signal wave shape.
The requirements that follow define these characteristics in terms of the voltages and
currents defined in Figure 4.
IA
A
D
IB
VAB
VA
B
(VA+VB)/2
VOS
VB
C
Figure 4 – Driver output voltage and current definitions.
The signaling sense of the voltages appearing across the driver test load is defined in
Figure 5, may differ from that used on the interchange circuit, and is as follows:
5
SP-4828
a. The A terminal of the driver shall be negative with respect to the B terminal for a Low
state.
b. The A terminal of the driver shall be positive with respect to the B terminal for a High
state.
c. The outputs of a driver that is neither High or Low shall appear as a high impedance
(Off) relative to the load and as specified herein. The differential voltage across the test
load will be near zero volts.
The logic function of the driver is beyond the scope of this Standard, and therefore is
not defined.
Low
High
Low
Off
VB
V
VA
VAB = VA - VB
0V
Figure 5 - Driver output signaling sense.
4.1.1 Differential output voltage, VAB
The steady-state magnitude of the differential output voltage (V AB) shall be greater than
or equal to 480 mV and less than or equal to 650 mV when measured with the test
circuit shown in Figure 6. For the opposite binary state, the polarity of VAB shall be
reversed (VAB*). The steady-state magnitude of the difference between V AB and VAB*
shall be 50 mV or less.
480 mV < | VAB | < 650 mV
480 mV < | VAB* | < 650 mV
| VAB | - | VAB* | < 50 mV
6
SP-4828
A
High or Low
steady-state
logic input
3.32k
D
49.9
V
B
3.32k
+ -1 V to
VTEST
- 3.4 V
Note: Resistors are + 1%
Measured
parameter
Figure 6 - Differential output voltage test circuit.
The 49.9- resistor in the test circuit of Figure 6 simulates the nominal differential load
of the interconnecting media. The 3.32-k resistors represent thirty-two worst-case MLVDS receiver inputs. The test voltage simulates the allowable common-mode voltage.
4.1.2 Output voltages, VOA and VOB
To limit the maximum steady-state voltage at any interchange on the M-LVDS line with
thirty-two contending drivers, the maximum output voltage must be restricted. In this
test, each driver is allocated 1/32 of the current needed to drive the differential load to
2.4 V.
The steady-state output voltage between an output terminal of the driver circuit and its
common shall be between 0 V and 2.4 V when measured with a load resistor of at least
1.62 k (see Figure 7).
0 V < VOA < 2.4 V
0 V < VOB < 2.4 V
7
SP-4828
A
High or Low
steady-state
logic input
D
B
1.62 k
or greater
VO
Measured
parameter
C
Figure 7 - Output voltage test circuit.
4.1.3 Offset (common-mode output) voltage, VOS
The steady-state magnitude of the driver offset voltage (V OS), measured with the test
load of Figure 8, shall be greater than or equal to 0.3 V and less than or equal to 2.1 V
for either binary state. The steady-state magnitude of the difference of V OS for one
binary state and VOS* for the opposite binary state shall be 50 mV or less.
0.3 V < VOS < 2.1 V
0.3 V < VOS* < 2.1 V
| VOS - VOS* | < 50 mV
A
High or Low
Steady-state
logic input
24.9 + 1%
D
B
24.9 + 1%
Measured
parameter
Figure 8 - Driver offset voltage test circuit.
8
+
VOS
-
SP-4828
4.1.4 Short-circuit current, IOS
Since an M-LVDS multipoint line allows multiple drivers, the possibility of contention
requires a restriction on the power that may be supplied to the interchange. This is
accomplished with a maximum allowable current from the driver.
The peak magnitude of the driver output current (I OS) shall not exceed 43 mA with an
applied voltage from –1 V to 3.4 V and in either binary state (see Figure 9).
| IOS | < 43 mA
A
High or Low
steady-state
logic input
D
IOS
B
Measured
parameter
-1 V to 3.4 V
+
VTEST
-
C
Figure 9 - Driver short-circuit test circuit.
The driver shall not be damaged by continuous operation in any short-circuit output
condition including a differential voltage of zero volts (short circuit).
4.1.5 High-impedance state output currents
The output current of a driver that is neither HIGH or LOW shall meet the requirement
of 4.3 Interchange input impedance.
4.1.6 Output signal waveform
The differential output voltage transition time of a driver determines the maximum
signaling rate and stub lengths of an M-LVDS interface. Excessive over and under
shoot of the output signal can cause electromagnetic emissions or false logic state
changes on the media.
During transitions of the driver output between binary states (High-to-Low and Low-toHigh), the differential voltage measured across the 49.9  ± 1% test load shall change
monotonically between 0.1 and 0.9 of the steady-state output, VSS. The time for the
output voltage to rise between 0.1 and 0.9 or fall between 0.9 and 0.1 of V SS shall be
greater than or equal to 1 ns and less than or equal to 0.5 of the minimum unit interval
9
SP-4828
(see Figure 10).
standard.
The minimum unit interval should be specified in the referencing
1 ns < tr < 0.5 tUI
1 ns < tf < 0.5 tUI
NOTE – tUI should allow some time margin for data sampling and be longer than
2 ns.
The peak signal voltage on a Low-to-High transition, VPH, shall not be greater than
1.2 VSS. The peak signal voltage on a High-to-Low transition shall not be less than
-0.2 VSS. After crossing 0.8 VSS on a Low-to-High transition, the signal shall not go
below 0.8 VSS until the next state change occurs. After crossing 0.2 VSS on a High-toLow transition, the signal shall not go above 0.2 VSS until the next state transition.
VPH < 1.2 VSS
-0.2 VSS < VPL
VSS is defined as the voltage summation of the two steady-state values of the driver
output (VSS = VAB + VAB*).
Measurement fixtures and instrumentation used for compliance testing shall provide a
-3 dB bandwidth of 1 GHz minimum.
10
SP-4828
A
Alternating
logic input
(high-to-low
and low-to-high
VAB
D
49.9 + 1%
B
1.2Vss
Vss
0.9Vss
0.8Vss
VAB
VPH
0V Differential
VAB*
tUI
0.2Vss
0.1Vss
0Vss
VPL
tr
tf
-0.2Vss
Figure 10 - Driver output signal waveform.
4.1.7 Dynamic output signal balance, VOS(PP)
A difference in the magnitude of rate at which the voltage changes at the A and B
interchange points results in a time-varying common-mode signal. This is a source of
electromagnetic emissions from the media and must be constrained.
During transitions of the driver output between alternating binary states (High-to-Low
and Low-to-High), the peak-to-peak voltage change of the offset voltage (V OS) shall be
less than 150 mVP-P (peak-to-peak). VOS(P-P) shall be measured between 24.9 ±1%
resistors to circuit common (C) connected as shown in Figure 11. Measurement
equipment used for compliance testing shall provide a –3 dB bandwidth of 1 GHz
minimum.
11
SP-4828
A
Alternating
logic input
(high-to-low
and low-to-high
24.9 
D
24.9 
Vos
B
C
VOS(PP) < 150 mV
Figure 11 - Dynamic driver output balance measurement.
4.2
Receiver characteristics
A receiver indicates the logical state of the M-LVDS multipoint line as defined by the
differential voltage that exists at the interchange. The differential input voltage that a
receiver detects a bus state change is defined as the input threshold voltage. The
receiver must detect this difference over the allowable common-mode input voltage
range as determined by the driver output offset and ground difference voltages.
The requirements that follow define these characteristics in terms of the voltages and
currents defined in Figure 12. The logic function of the receiver is beyond the scope of
this Standard, and therefore is not defined.
IA
A
VID
(VA+VB)/2
VCM
R
IB
VA
VB
B
C
Figure 12 - Receiver voltage and current definitions.
4.2.1 Receiver input voltage threshold
Two types of differential receivers are specified below. Type 1 receivers include no
provisions for failsafe and have their differential input voltage thresholds near zero volts.
Type 2 receivers have their differential input voltage thresholds offset from zero volts to
12
SP-4828
detect the absence of voltage difference. Type-1 receivers maximize the differential
noise margin and are intended for the highest signaling rates. Type-2 receivers are
intended for control signals and slower signaling rates.
Both receiver types shall not require a steady-state differential input voltage (VID) of
more than the values listed in Table 1 (and shown graphically in Figure 13) to correctly
assume the intended binary state. The allowable steady-state input voltages are shown
graphically in Figure 14 for Type-1 and Figure 15 for Type-2 receivers.
Table 1 - Receiver Input Voltage Threshold Requirements
Low
Transition Region
(undefined)
High
Type 1
-2.4 V < VID < -0.05 V
-0.05 V < VID < 0.05 V
0.05 V < VID < 2.4 V
Type 2
-2.4 V < VID < 0.05 V
0.05 V < VID < 0.15 V
0.15 V < VID < 2.4 V
Receiver type
NOTE – The signaling rate and the minimum differential input signal for timevarying input conditions should be specified by the referencing standard. It is
recommended that receivers in compliance with this Standard be designed to
detect state transitions at the required rate with a magnitude 50 mV greater than
the maximum steady-state input voltage threshold.
Type 1
Type 2
High
High
2.4 V
150 mV
VID
50 mV
0V
-50 mV
Low
Low
-2.4 V
Transition Region
Figure 13 - Receiver differential input voltage threshold requirements.
13
SP-4828
VB
VA - VB = -2.4 V
3.8 V
Invalid
2.4 V
Transition Region
-50 mV < VA - VB < 50 mV
Low
VA - VB = 2.4 V
High
-1.4 V
3.8 V
0V
VA
2.4 V
Invalid
-1.4 V
0V
Figure 14 – Type-1 receiver input voltage range.
14
SP-4828
VB
VA - VB = -2.4 V
3.8 V
Invalid
2.4 V
Transition Region
50 mV < VA - VB < 150 mV
Low
High
VA - VB = 2.4 V
-1.4 V
3.8 V
0V
VA
2.4 V
Invalid
-1.4 V
0V
Figure 15 – Type-2 receiver input voltage range.
4.2.2 Receiver input current
The input current of a receiver shall meet the requirement of 4.3 Interchange input
impedance.
4.3
Interchange input impedance
The steady-state load presented to an M-LVDS multipoint line by a driver or a
transceiver that is Off or a receiver shall meet the following requirements under any
operating conditions. These conditions include power cycling of the equipment. All
requirements shall be met at the A or B interchange points with respect to the circuit
common, C.
NOTE - The cycling criteria for equipment power should be specified in the
referencing specification or by the manufacturer.
15
SP-4828
4.3.1 Non-terminating interchanges
The requirements of this section apply to circuits that do not include the transmission
line matching impedance.
4.3.1.1 Steady-state loading, IA and IB
The magnitude of the input current shall not exceed 32 A over an input voltage range
of –1.4 V to 3.8 V with the other input at 1.2 V (see Figure 16).
The magnitude of the input current shall not exceed 20 A over an input voltage range
of 0 V to 2.4 V with the other input at 1.2 V.
The voltage across a 10 M, or greater, resistance between A and C or B and C shall
be between 0 V and 2.4 V.
IA or IB
IA
32 A
A
M-LVDS
Circuit
IB
VA
VB
B
20 A
C
-1.4 V
VA or VB
0V
2.4 V
-20 A
3.8 V
Allowed
operating range
-32 A
Figure 16 - Allowed steady-state input current versus input voltage.
With a differential input voltage (VID) of 0 V, the magnitude of differential current I A – IB
shall be less than 4 A over a common-mode input voltage range of –1.4 V to 3.8 V
(see Figure 17).
16
SP-4828
IA – IB  < 4 A
IA
A
M-LVDS
Circuit
IB
+
-1.4 V
to 3.8 V
B
C
Figure 17 - Differential input current test.
4.3.1.2 Load with time-varying signals
4.3.1.2.1 Differential input impedance, ZIN
The input impedance of an M-LVDS circuit should be large enough that the apparent
characteristic impedance of a fully loaded M-LVDS multipoint line segment is greater
than 60. Specification of ZIN requires information on the electrical and physical
characteristics of the multipoint line.
With the minimum distance between interchanges (d), the distributed capacitance of
the interconnecting media (C0), and the minimum unit interval (tUI) specified by the
referencing standard; the input impedance magnitude of an M-LVDS circuit shall be
t UI
greater than
. (See Annex D for the derivation of this requirement.) ZIN shall
2.5dC0
1
be measured at the AB interchange for any measurement frequency below
Hz.
t UI
Equation 1 - Minimum input impedance of an M-LVDS circuit
ZIN 
tUI

2.5dC 0
NOTE - The interchange includes the connection from the balanced media to the
silicon, or stub. A stub that is long with respect to the signal transition time will
take on transmission line characteristics. This will make it difficult to maintain
sufficiently high input impedance for a useful multipoint line structure.
NOTE – Time-Delay Reflectrometry (TDR) is the recommended method for
testing of this requirement. The test set up requirements are under study and
will be addressed in a future Telecommunication Systems Bulletin (TSB).
EXAMPLE - Signaling at 100 Mb/s over 1 meter of twisted-pair cable with a distributed
capacitance of 40 pF/m between M-LVDS interchanges, the input impedance
requirement would be
17
SP-4828
tUI

2.5dC 0
10 8
.
ZIN 
2.5  3.1 1 40  10 12
ZIN  32
ZIN 
If the load is capacitive (as is normally the case), the differential input capacitance
1
would be found by substituting
for ZIN at f = 100 MHz and the maximum for
j 2fC AB
CAB found to be 50 pF. Using 0.1 m of printed-circuit board and 140 pF/m at the same
signaling rate yields a maximum differential input capacitance of 17.5 pF.
4.3.1.2.2 Input impedance balance
The input impedance magnitudes of an M-LVDS circuit measured at the AC and BC
interchanges with the other input at 1.2 V shall be within 1% for any measurement
1
frequency below
Hz.
t UI
NOTE – Time-Delay Reflectrometry (TDR) is the recommended method for
testing of this requirement. The test set up requirements are under study and
will be addressed in a future Telecommunication Systems Bulletin (TSB).
4.3.2 Terminating interchanges
The interchange circuit may provide the transmission line impedance matching
termination. When done, the definitions of Figure 18 and the following requirements
shall apply.
NOTE - The termination impedance may consist of discrete or integrated and
active or passive components. The exact structure of the termination impedance
is beyond the scope of this Standard.
IA
A
M-LVDS
Circuit
IB
VA
VB
B
C
Figure 18 - Voltage and current definitions for terminating interchanges.
18
SP-4828
4.3.2.1 Steady-state loading
The magnitude of the input current shall not exceed 64 A over an input voltage range
of –1.4 V to 3.8 V with the other input open circuit (> 10 M).
The magnitude of the input current shall not exceed 40 A over an input voltage range
of 0 V to 2.4 V with the other input open circuit (> 10 M).
The voltage across a 10 M, or greater, resistance between A and C or B and C shall
be between 0 V and 2.4 V.
With a differential input voltage (VID) of 0 V, the magnitude of differential current I A – IB
shall be less than 4 A over an input voltage range of –1.4 V to 3.8 V (see Figure 17).
The resistance measured between the A and B interchange shall be 99 to 101 with
an applied differential voltage of –800 mV to 800 mV and common-mode voltage from
-1 V to 3.4 V.
EXAMPLE Inputs, Volts
VA
VB
-1.40
-0.60
3.00
3.80
-0.60
-1.40
3.80
3.00
Resulting Voltages
VID
VCM
-0.80
-1.00
-0.80
3.40
0.80
-1.00
0.80
3.40
IA - IB, mA
Minimum Maximum
-7.92
-8.08
-7.92
-8.08
7.92
8.08
7.92
8.08
4.3.2.2 Load with time-varying signals
4.3.2.2.1 Differential input impedance, ZIN
With the minimum unit interval (tUI) specified by the referencing standard; the input
impedance magnitude measured between the A and B interchange shall be greater
than or equal to 95 and less than or equal to 105 with a measurement frequency of
1
Hz.
tUI
95 < ZIN < 105
NOTE – Time-Delay Reflectrometry (TDR) is the recommended method for
testing of this requirement. The test set up requirements are under study and
will be addressed in a future Telecommunication Systems Bulletin (TSB).
NOTE – Signal quality may be improved by reducing ZIN to near the
characteristic impedance of the fully loaded bus segment if required by the
19
SP-4828
referencing standard. This is not recommended for buses that will have variable
loading characteristics.
4.3.2.2.2 Input impedance balance
The input impedance magnitudes of an M-LVDS circuit measured at the AC and BC
interchanges with the other input at 1.2 V shall be within 1% for any measurement
1
frequency below
Hz.
tUI
NOTE – Time-Delay Reflectrometry (TDR) is the recommended method for
testing of this requirement. The test set up requirements are under study and
will be addressed in a future Telecommunication Systems Bulletin (TSB).
4.4
Interconnecting media electrical characteristics
The interconnecting media shall consist of paired metallic conductors in any
configuration that will meet the following electrical requirements. The actual media is
not specified and may be twisted-pair cable, twinaxial cable (parallel pair), flat-ribbon
cable, or printed-circuit board (PCB) traces.
Annex A to this Standard provides guidance on performance and cable length versus
data signaling rate and cable recommendations for typical cable applications.
4.4.1 Characteristic impedance
The differential characteristic impedance (Z0) of the unloaded balanced media shall be
100 +/- 10% from 10 MHz to the application signaling rate in Hertz.
NOTE – Time-Delay Reflectrometry (TDR) is the recommended method for
testing of this requirement. The test set up requirements are under study and
will be addressed in a future Telecommunication Systems Bulletin (TSB).
4.4.2 Attenuation
The sinusoidal signal loss through the unloaded interconnecting media shall be no
more than 6 dB. The measurement frequency shall be with a period of one-half the
minimum unit interval specified by the referencing standard.
5
5.1
SYSTEM CONSIDERATIONS
Failsafe operation
Other standards and specifications using the electrical characteristics of the M-LVDS
interface circuit should anticipate events that would remove a valid signal from an
interchange. These events may be faults or part of normal operation and may include
one or more of the following:
20
SP-4828
1) All drivers are in the Off or high-impedance condition.
2) A receiver becomes disconnected from the interconnecting media.
3) The interconnecting cable becomes open-circuited.
4) The interconnecting cable becomes short-circuited.
5) More than one driver contends for the bus.
All of the above conditions may cause the differential input signal to a load to remain
within the transition region for an abnormal period. When detection of one or more of
the above conditions is required, the following items should be determined and
specified:
1) Which interchange circuits require failsafe provisions?
2) What conditions must be detected?
3) What action must be taken when a condition is detected (i.e., the binary state that
the receiver assumes)?
The system response to failsafe conditions is beyond the scope of this Standard as the
logic function of the driver and the receiver or the communication protocol is not
defined. The bus states are defined in terms of the electrical characteristics on the bus
and not how they are indicated.
Type-2 receivers were included as an option to provide a valid bus state indication for
signals that are within the transition region of Type-1 receivers. Whether Type-2
receivers or other failsafe provisions are used, their impact on noise margin, system
timing, and compliance with all of the requirements of this Standard should be
considered.
NOTE - It is possible to construct a Wired-Or bus using Type-2 receivers by only
allowing driver outputs to be High or Off. When Off, the terminations will pull the
difference voltage to near zero volts and a valid bus state for the Type-2
receiver.
5.2
Transient protection
It is advisable that there be protection from electrical overstress from electromagnetic or
electrostatic transient noise to the M-LVDS interchange. The extent of which should be
determined and specified by the application.
5.3
Signal common (ground)
Proper operation of the M-LVDS interface circuits requires a signal return path between
the equipment along the interconnecting media. The signal common interchange lead C
21
SP-4828
shall be connected to the circuit common which should be connected to protective
ground by any of the methods shown in Figure 19, Figure 20, or Figure 21 as required
by the specific application.
The same configuration need not be used at all interconnections; however, care should
be exercised to prevent establishment of ground loops carrying high currents.
In configuration A of Figure 19, the circuit common of the equipment is connected to
protective ground, at one point only, by a 100  ±20% resistor with a power dissipation
rating of 0.5 W. An additional provision may be made for the resistor to be bypassed
with a strap to connect circuit common and protective ground directly together when
specific installation conditions necessitate.
NOTE - Under certain ground fault conditions in configuration A, high ground
currents may cause the resistor to fail; therefore, a provision should be made for
inspection and replacement of the resistor.
Optional shorting
strap
M-LVDS
Circuit 0
100 , ½ W
C0
M-LVDS
Circuit 1
C1
M-LVDS
Circuit n
Cn
Green- wire ground
Protective ground
or Frame ground
Circuit common
or circuit ground
Figure 19 - Optional grounding arrangement A.
In configuration B of Figure 20 and C of Figure 21, each signal common shall be
connected directly (or through a resistor) to protective ground.
22
SP-4828
M-LVDS
Circuit 0
GWG
M-LVDS
Circuit 1
M-LVDS
Circuit n
GWG
GWG
C0
C1
Cn
Protective ground
or Frame ground
100 , ½ W
(typical)
GWG= Green-wire ground of power system
Figure 20 - Optional grounding arrangement B.
M-LVDS
Circuit 0
GWG
M-LVDS
Circuit 1
GWG
M-LVDS
Circuit n
GWG
C0
C1
Cn
Protective ground
or Frame ground
GWG= Green-wire ground of power system
Figure 21 - Optional grounding arrangement C.
Some interface applications may require the use of shielded balanced interconnecting
media for system electromagnetic compatibility. When employed, the shield should be
connected only to frame or protective ground at one point to prevent ground loops. The
means of connection of the shield and any associated connector are beyond the scope
of this Standard.
5.4
Noise budgeting
Drivers that comply with this Standard will generate a differential voltage of at least
480 mV into a 49.9-ohm test load. Receivers that comply with this standard will
correctly detect the state of the bus with as little as a 50-mV difference voltage for
Type-1 receivers (or 150 mV for Type-2). The difference between the minimum driver
differential output voltage and the maximum receiver differential input threshold is the
differential signal noise margin.
The differential signal noise margin should be allocated to the noise sources expected
in an application to assure sufficient signal arrives at the destination and define a valid
logic state at any interchange. At the highest signaling rates, it is intended that Type-1
receivers and incident-wave switching is used and presents the most constrained
23
SP-4828
budget. The differential noise contributors considered in the development of this
Standard are shown in Table 2 along with a budgeted value. Since each application
may uniquely allocate the noise budget, these values can only be used as guidelines.
Table 2 - Type-1 receiver differential noise budget example.
Signal Noise Source
Budget
Media characteristic impedance tolerance
Minimum
Signal Level
48 mV
432 mV
6 mV
426 mV
Signal reflection
-1.9 dB
342 mV
Interconnecting media attenuation
-6 dB
171 mV
Interchange input imbalance
36 mV
135 mV
Input overdrive
50 mV
85 mV
Electromagnetic interference
35 mV
50 mV
Interchange input offset
Maximum Type-1 input voltage threshold
50 mV
The maximum differential input voltage threshold of a Type-2 receiver may be as high
as 150 mV. This leaves less noise margin to work with than the same system using a
Type-2 receiver and will generally require reflected-wave switching and lower signaling
rates to achieve a valid voltage difference on the bus. An example is shown in Table 3
with less margin budgeted to signal reflections and input overdrive.
Table 3 - Type-2 receiver differential noise budget example.
Signal Noise Source
Budget
Minimum
Signal Level
Termination impedance tolerance
9 mV
471 mV
Interchange input offset
6 mV
465 mV
Signal reflection
-0.4 dB
442 mV
Interconnecting media attenuation
-6 dB
221 mV
Interchange input imbalance
36 mV
185 mV
0 mV
185 mV
35 mV
150 mV
Input overdrive
Electromagnetic interference
Maximum Type-2 input voltage threshold
150 mV
NOTE – It is recommended that Type-2 receiver response time be limited to
avoid detecting noise prior to arrival of the reflected wave.
24
SP-4828
Along with the differential signal budget, there is a common-mode signal constraint. An
M-LVDS receiver is only required to detect the difference signal with a common-mode
input signal from –1 V to 3.4 V. The worst-case common-mode signal on an M-LVDS
bus can be 0 V to 2.4 V in the absence of any externally generated noise. This leaves
1 V below and above this range for common-mode noise coupling from external
sources.
25
PSP-4828
Annex A (informative)
GUIDELINES FOR CABLE APPLICATION
A.1 Interconnecting cable
The following section provides further information and guidance concerning operational
constraints imposed by the cable media characteristics.
Generally, if more than one signal transmission line is required for an interface, twisted
pairs are necessary to balance coupling reactance between individual conductors of
adjacent pairs and thus reduce crosstalk.
A.2 Additional characteristics
Additional cable characteristics not specified in the Standard that should be considered
are: Maximum Propagation Delay, Maximum Propagation Delay Skew, Maximum NearEnd Crosstalk (NEXT), and Maximum Far-End Crosstalk (FEXT). Crosstalk, skew, and
related pair balance parameters may impact applications with multiple signal
transmission lines.
A.3 Length
The maximum distance separating the driver and the load is based upon a maximum
signal attenuation of 6 dB at a frequency of 1/tUI Hz or a maximum one-way media
resistance of 50  in the steady state. The steady-state limit is the upper bound for
cable length. Typical values for the resistance of tin-coated copper stranded
conductors gives a maximum distance of 225 m for 28 AWG, 388 m for 26 AWG,
612 m for 24 AWG, and 983 m for 22 AWG.
A.4 Typical cable characteristics
Parallel interface cable
The following characteristics apply to common parallel interface cable (as used for
TIA/EIA-613, and other I/O interface standards) consisting of 25 twisted pairs
surrounded by an overall shield:
Parallel cable, physical characteristics
Conductor: 28 AWG, 7 strands of 36 AWG, tinned annealed copper, nominal
diameter 0.38 mm (0.015 inch)
Insulation: Polyethylene or polypropylene; 0.24 mm (0.0095 inch) nominal wall
thickness; 0.86 mm (0.034 inch) outside diameter
26
SP-4828
Foil Shield: 0.051 mm (0.002 inch) nominal thickness aluminum or polyester
laminated tape helical wrapped around the core
Braid Shield: braided 36 AWG, tinned copper with 80% minimum coverage, in
electrical contact with the aluminum surface of the foil shield
Diameter: nominal overall cable diameter 9.5 mm (0.375 inch)
Parallel cable, electrical characteristics
DC Resistance: 221 /km (67.5 /1000 feet)
Mutual Capacitance: 43 pF/m (13 pF/ft) at 1 kHz
Impedance: (characteristic, differential mode) 110  nominal at 50 MHz
Propagation Delay: 4.8 ns/m (1.46 ns/ft)
Attenuation: 0.28 dB/m (0.085 dB/ft) at 50 MHz
Skew: (propagation delay) 0.115 ns/m (0.035 ns/ft)
Maximum Crosstalk: (Near End, NEXT) 30 dB at 50 MHz
Serial interface cable
The following characteristics apply to a common Category 5 serial interface cable (as
used for TIA/EIA-422-B, and other I/O interface standards) consisting of 4 unshielded
twisted pairs surrounded by an overall jacket:
Serial cable, physical characteristics
Conductor: 24 AWG, 7 strands of 32 AWG, tinned annealed copper, nominal
diameter 0.61 mm (0.024 inch)
Insulation: Polyethylene or polypropylene; 0.18 mm (0.007 inch) nominal wall
thickness; 0.97 mm (0.038 inch) outside diameter
Foil Shield: optional
Braid Shield: optional
Diameter: nominal overall cable diameter 5.6 mm (0.22 inch)
Serial cable, electrical characteristics
DC Resistance: 84.2  / km (25.7 /1000 feet)
Mutual Capacitance: 48 pF/m (14.5 pF/ft) at 1 kHz
27
SP-4828
Impedance: (characteristic, differential mode) 100  nominal at 50 MHz
Propagation Delay: 4.8 ns/m (1.46 ns/ft)
Attenuation: 0.17 dB/m (0.051 dB/ft) at 50 MHz
Maximum Crosstalk: (Near End, NEXT) 36.8 dB at 50 MHz
A.5 Cable length vs. signaling rate guidelines
The maximum length of cable separating the driver and the load is primarily constrained
by signal distortion and common-mode noise. Some guidelines for predicting signal
distortion will be provided but predicting the common-mode noise coupling is
impossible. It is recommended that measurement of the common-mode noise be
performed at the installation.
To determine the maximum signaling rate for a particular cable length the following
calculations or testing is recommended (ordered in decreasing accuracy).
Eye-pattern measurement – Eye-patterns are recommended to determine the amount
of jitter at the load at the application signaling rate and comparing that to system
requirements. This testing should be done in the actual application or in a test system
that models the actual application as close as possible. The protocol and coding
scheme should be reproduced or worst-case data pattern used.
Figure 22 shows the signaling rate versus line length for some typical cables in an
uncomplicated point-to-point connection and 5% eye-pattern jitter. The eye-pattern jitter
was determined by using a pseudo-random code with a run length of 32,768.
28
SP-4828
280
Cable D: CAT 5, braided over-all shield and taped shielded pairs, 0.64 mm
260
Signaling Rate, Mbps
240
Cable C: CAT 5, taped over all shield, 0.52 mm
220
200
180
160
Cable B: CAT 5, no shield, 0.52 mm
140
120
100
0
2
4
6
8
10
12
Distance, meters
Figure 22 - Signaling rate versus cable length for a 5% eye-pattern jitter.
NOTE – This graph contains a limited range of possible M-LVDS line lengths and
signaling rates. Do not interpret it to be the only possible operating points.
Signal rise and fall time measurement – Generally a transmission circuit will exhibit
less than a 5% eye-pattern jitter if the 10%-to-90% rise time of the signal from the
steady state and at the end of the cable is less than one-half of the unit interval.
Attenuation at 1/tUI Hz – An interface circuit is generally useful if the sinusoidal
attenuation at the application signaling rate in Hertz is less than 6 dB.
Steady-state attenuation – An M-LVDS interface circuit is not considered useful if the
one-way resistance of the conductor is more than 50 .
29
SP-4828
Annex B (informative)
GENERAL PCB GUIDELINES FOR M-LVDS APPLICATIONS
B.1 Configurations
The M-LVDS standard is very versatile. Many different bus configurations are possible.
The exact details of the M-LVDS bus configuration are left up to the referencing
standard or application to fully specify. In regards to stub length, two basic bus
configurations exist and differ mainly in stub length. These are referred to as T-type
and Daisy Chain busses.
T-Type. This connection creates a stub of length "L" that includes the connector pins
and the trace on the PCB (see Figure 23). It has the advantage of a single connector
and supports a hot-plug into an active bus. The limitation of this configuration is the
overall stub length (L) tends to be longer than in the case of a Daisy Chain.
Connector
A0 B0
Stub Length, L
M-LVDS
Circuit
PCB
Figure 23 – T-type connection to bus backbone.
Daisy Chain. This connection uses a pass through bus to minimize the true stub
length. In this case, the connectors and pass-through line are considered part of the
main line and not stub (see Figure 24). The actual stub length is the distance from the
connection point to the device pins only. The main advantage of this configuration is
the short stub length. The major limitations of this configuration are the requirement of
two connectors and that a re-configure of the bus breaks the main line halting
communication.
30
SP-4828
Connector
B0
A0
Stub Length, L
M-LVDS
Circuit
PCB
Figure 24 – Daisy-chain bus connection.
B.2 Differential Traces
Closely coupled differential pairs are recommended for M-LVDS circuits. The close
coupling has multiple benefits that enhance system performance. Closely coupled lines
tend to have less radiation, and they help to insure that noise picked up is commonmode and not differential in nature. Also having the traces closely coupled tends to
keep them in balance and minimizes asymmetrical loading issues. Traces may be
edge-coupled or broadside pairs.
Differential Impedance. The target media impedance for an M-LVDS circuit is
nominally 100 Ohm. This is well suited for a variety of cable constructions and the use
of standard dimensions of differential pairs on printed circuit boards.
Board stack. Board stack is not specified by this standard and is considered
implementation specific. However, a four or greater layer stack up is recommended to
provide a solid power and ground system and impedance reference. Fast single-ended
signals should be kept away from the M-LVDS pairs or on a different layer to avoid
coupling.
Stub-Trace Skew. Trace length should be controlled and matched as close as
possible. A general guideline is to match electrical length of the lines that compose the
pair to within 1 mm (39 mils). Skew between the pair causes a phase difference
between these signals and generates increased common-mode modulation and more
noise.
31
SP-4828
Feed Through (via). The use of via along the interconnect should be minimized. Give
priority to the routing of the high-speed M-LVDS lines. A via structure adds capacitance
to the line and reduces the effective impedance which could lower noise margins.
Stub Lengths. The stub length is a critical element of the system and should be
minimized whenever possible. Locate the interface devices close to the connectors to
help minimize the resulting stub length. The goal is to ensure that they act as a lumped
element and not as a separate transmission line. Note that the most critical stub length
is located closest to the source where the rise time of the signal is the fastest.
Termination. Termination is required at the two extreme ends of the bus only.
Nominally, it is 100 Ohm across the pair. It may be lower to match the effective
differential impedance of certain applications. The termination value should not be less
than 60 Ohms. Note that a driver on the bus sees both termination resistors in parallel,
thus the nominal bus load is actually 50 Ohms and may be as low as 30 Ohms.
Surface mount resistors are recommended due to their compact size and lower
parasitics than leaded components. Internal termination is also allowed in the interface
devices that are located at the ends of the bus.
32
SP-4828
Annex C (informative)
COMPATIBILITY WITH OTHER INTERFACE STANDARDS
Compliance to the minimum requirements of this standard will not be ensure
interoperability with other differential interface standards such as TIA/EIA-422, TIA/EIA485, or their ITU-T/ISO equivalents. Interoperation with these interfaces may be
possible with proper signal conditioning or use of circuits that exceed the minimum
requirements of this Standard. Generally, the signal levels of these standards are
higher than those of M-LVDS circuits and must be attenuated to levels within the
allowed range of operation (see
Figure 25).
15
12
12
485
10
10
10
422
5
3.8
M-LVDS
3.8
2.4
VB, volts
644
0
-15
-10
-5
0
0
-1.4
5
-1.4
10
15
-5
-7
-10
-15
VA, volts
33
SP-4828
Figure 25 - Voltage ranges of differential interface standards.
Inter-operability also requires detection of the difference signal. The minimum receiver
input voltage threshold is 50 mV for a Type-1 M-LVDS receiver, 100 mV for a TIA/EIA644 receiver, and 200 mV for a TIA/EIA-422 or –485 receiver.
C.1 Related TIA/EIA standards
TIA/EIA-422 Electrical Characteristics of Balanced Voltage Digital Interface Circuits
TIA/EIA-485 Standard for Electrical Characteristics of Drivers and Receivers for use in
Balanced Digital Multipoint Systems
TIA/EIA-644 Electrical Characteristics of Low Voltage Differential Signaling (LVDS)
Interface Circuits
C.2 Other related interface standards
IEEE 1596.3 SCI-LVDS Low Voltage Differential Signals Specifications and Packet
Encoding
ITU-T (formerly CCITT) Recommendation V.11 Electrical characteristics for balanced
double-current interchange circuits for general use with integrated circuit equipment in
the field of data communications
ISO8482 Information processing systems – Data communication – Twisted pair
multipoint interconnections
X3.302:1999 SCSI Parallel Interface - 2 (SPI-2)
34
SP-4828
Annex D (informative)
BUS LOADING DERIVATION
The characteristic impedance of the M-LVDS balanced media is specified (par. 4.4.1)
as 100  + 10% [90  to 110 ]. An unloaded M-LVDS bus therefore, appears as a
nominal 50- load to a driver circuit (50  = 100 ||100 ). The steady-state
magnitude of the differential output voltage (V AB) delivered to this 50- load, is
specified (par. 4.1.1) as:
480 mV < VAB  < 650 mV.
An M-LVDS receiver correctly identifies the input signal (par. 4.2) when a differential
voltage of at least 50 mV exists at the receiver input. This receiver threshold allows for
a 19.6-dB loss in signal for the lowest driver output voltage [loss = 20 log (0.050/0.480)].
The design of an M-LVDS network must account for all signal losses between a
network driver and receiver. The budgeted signal loss allocated to network reflections
is –1.9 dB. Signal losses due to network reflections will occur whenever the transmitted
signal from a driver encounters a change in impedance of the interconnecting media.
The signal loss due to network reflections is calculated as follows:
Vloss  20 log( Vtransmit / Vincident ) (1)
where Vtransmit is the signal propagated beyond the impedance mismatch and
Vincident is the incident voltage signal.
Using equation (1) above and setting Vloss equal to –1.9 dB, the ratio of transmitted to
incident voltage is found 0.80.
When a voltage wave propagates down a transmission line and encounters an
impedance mismatch, the transmitted and incident voltage waves are related through
equation (2) below:
Vtransmit / Vincident  (1   ) (2)
where  is the reflection coefficient, and the reflection coefficient is determined from the
following:

Z ' Z 0
(3)
Z ' Z 0
where Z0 is the characteristic impedance of the incident media and Z’ is the impedance
of the secondary media (in this case the loaded impedance of the M-LVDS bus).
35
SP-4828
Using equation (2) to solve for  results in  = -0.20. Using this in equation (3), and
taking the characteristic impedance of the balanced transmission line at its minimum
value of 90 , results in a limitation that Z’ be greater than 60 .
With this value of Z’  60 , the effective loading of the M-LVDS bus by transceivers
can now be determined.
If the M-LVDS bus is evenly loaded with capacitive loads of CL F, and that a uniform
spacing of d cm exists between loads, the effective impedance of a loaded bus can be
calculated. Recalling that the characteristic impedance of a lossless line is given as
shown below:
L0
(4)
C0
Z0 
where L0 is the inductance per unit length (H/cm)
and C0 is the capacitance per unit length (F/cm)
Then the characteristic impedance of the loaded line can be calculated by noting that
the capacitive loading effectively changes the capacitance per unit length to
C ' eff  C 0 
CL
(5)
d
which leads to
Z'
L0
C 0  CL
d
 Z0
1
(6)
1  CL
C 0d
Squaring both sides of equation (6), rearranging terms, and setting Z ’ = 60 , Z0 = 90 ,
leads to
CL  1.25dC0 (7)
Limiting the effective distributed capacitance presented by the bus loads to the value
given in equation (7) allows one to calculate the effective impedance of each
transceiver. Allowing UI to represent the minimum unit interval at the signaling rate, the
impedance of a purely capacitive load is given below:
Z min 
1
(8)
jCL
and taking the magnitude of this impedance leads to
36
SP-4828
| Z min |
1
UI
(9)

2f  1.25dC 0 2.5dC 0
where UI=1/f has been used.
37