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Practical Logic Characteristics
1.1 Practical Logic Characteristics
In practical logic and switching circuits the performance is not ideal.
Hence parameters must be established which measure how close to
ideal the circuit performance is with regard to important features such
as speed, drive capability and noise immunity. Some such parameters
are as follows:
(a) Logic Voltages
These are defined as voltage levels in the logic family that, if
maintained throughout, will guarantee correct operation of a logic
circuit.
ViL MAX = maximum voltage acceptable as a logic LO input
ViHMIN = minimum voltage acceptable as a logic HI input.
VOL MAX = maximum voltage acceptable as a logic LO output.
VOHMIN = minimum voltage acceptable as a logic HI output.
These limiting voltages are shown in Fig. 1.1. These voltages are
defined from the coordinates on the input-output transfer
characteristic where the slope is –1. This is done on the basis of the
effect on the circuit which applies to noise and interference
components superimposed on the logic signal.
Consider slowly changing the input voltage from one logic state to
another. Increasing Vi from 0V, the output voltage falls slowly at first
until the point at which the slope = -1. After this, the output falls at a
faster rate than the input rises. In the fast transition region of the
characteristic in Fig. 1.1, the small signal gain is much greater than
unity. This means that any noise superimposed on the input as shown
in Fig.1.2 will be amplified and may cause a change of state at the
output. In the upper part of the curve, this does not happen. A similar
process applies to decreasing the input voltage from VCC .
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VCC
Input
Logic Voltages
Output
Valid high output
Valid high
input
VOH MIN
NMH
ViH MIN
ViL MAX
NML
Valid
low input
VOL MAX
Valid low output
VO
VOH MIN
Tangents at
slope = -1
Transfer Characteristic
VOL MAX
Vi
ViL MAX ViH MIN
VO
VO
Sourcing
current
Sinking
current
VOH MIN
Drive Capabilities
VOL MAX
I OH MAX
Fig. 1.1
IO
Practical Static Logic Characteristic
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I OL MAX
IO
VO
Output
noise
generated
Vi
Fig. 1.2
VCC
Noise
superimposed on
input
Effect of Noise Superimposed on a Logic Input
(b) Noise Immunity
The transfer characteristic shown in Fig. 1.1 is deliberately shaped so
that:
ViHMIN  VOHMIN
and
ViL MAX  VOL MAX
This allows a margin in the voltage levels so that an amount of noise
can be superimposed on the output voltage of one gate before the
logic level is misinterpreted at the input of another gate that it is
driving. This can be seen in Fig. 1.3 below. Noise Margins are defined
as:
NMH  VOHMIN  ViHMIN
and
NML  ViL MAX  VOLMAX
VOH MIN
VIH
Fig. 1.3
MIN
Benefit of Allowing a Noise Margin
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(c)
Drive Capability
There is a limit to the number of gates that can be connected as load
to the output of a single gate which will allow correct voltage levels to
be maintained. The current that the driving gate can source or sink is
limited and the gate also has finite output impedance. Output voltage
vs current characteristics are shown in Fig. 1.1.
I IL MAX
I OL MAX
I OH MAX
I IH MAX
Figure 1.4
Input and Output Load Currents in Logic Gates
With reference to Figure 1.4 Fan-out is the maximum number of
similar gates that can be connected to a gate output and is defined as:
F
IOHMAX
IiHMAX
or
IOL MAX
IiL MAX
whichever is the lowest
(d) Switching Times
The figures of merit used to characterize the speed of operation of
logic gates are its switching times shown in Fig. 1.5. The rise and fall
times are measured between the 10% and 90% points on the voltage
waveform transitions at the gate output. The propagation delays are
the delays resulting in a change of state taking place at the output of a
gate in response to a change of state applied to one of its inputs.
These are measured between the 50% points on the input and output
voltage waveforms.
(e) Dynamic Noise Immunity
A noise spike, which temporarily brings the input voltage across a
switching threshold can often be tolerated, without a consequential
change of state at the output, if there is not enough energy in the
pulse to cause a change of state. In general, this is the case if the
duration of the spike is less than the gate propagation delay as seen in
Fig. 1.5
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Switching Times
VH
Vi (t)
50
50
VL
t PLH
t PHL
VH
90
90
VO (t)
50
50
10
10
VL
tF
tR
t PLH
=
propagation time for a low-to-high output transition
t PHL
=
propagation time for a high-to-low output transition
tR
=
10%-to-90% rise time of output voltage
tF
=
90%-to-10% fall time of output voltage
Dynamic Noise Performance
Vi
VCC
Vi
ViH
ViL
MIN
MAX
t
t
t noise  t PLH
t noise  t PHL
VO
VCC
VOH
MIN
VOL MAX
t
Fig. 1.5
t
Practical Dynamic Logic Characteristics
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1.2 Limitations of Single Transistor Switching Circuits
(a) Finite Gain
The limited gain provided by a single transistor limits the steepness of
the transfer characteristic in the transition region between HI and LO
output voltages.
(b) Logic Voltage Dependence on Load
When the transistor in the simple bipolar inverter circuit shown in Fig.
1.6 is OFF, the output Logic HI voltage is given as:
VH 
RL
VCC
RL  R C
This is heavily dependent on R L . Clearly this situation is totally
undesirable and in practice the output voltage should be as
independent of the load as possible within the boundaries of
operation, i.e the fan-out specification. A means must be found of
better defining the output logic HI voltage.
VCC
RC
RL
RB
VO
Fig. 1.6 Voltage Dependence on Load of Simple Bipolar Logic Gates
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(c) Slow Transistor Turn-Off
When Vi 0V, the transistor in the simple bipolar inverter circuit of Fig.
1.7 turns OFF. To accomplish this, the overdrive charge stored in the
base region in saturation must be removed. This is done by a small
V
discharge current in the base IB   BE which makes the process quite
RB
slow. In addition, any load capacitance present must be charged up
through the collector resistor, R C , which further delays the output
transition from logic LO to logic HI. A means of removing the charge
stored in the base of the transistor must be found, as well as a means
of charging up load capacitance more rapidly.
RC
RB
CL
IB -ive
Fig. 1.7
Speed Limitation of Simple Bipolar Logic Gates
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