EP OPTIMA Synopsis - CORDIS
advertisement
European Commission ESPRIT Information Technologies RTD Programme Domain 2: Technologies for Components and Subsystems Summaries of projects Fourth Framework Programme March 1998 Directorate-General III Industry Legal notice Neither the European Commission nor any person acting on behalf of the Commission is responsible for the use which might be made of the information in this document This document was edited by Colette Maloney Esprit contact point Esprit Information Desk N-105 8/94 Avenue de Nerviens / Nerviërslaan 105 B-1040 Brussels tel +32 / 2-296-8596 — fax +32 / 2-296-8388 e-mail esprit@dg3.cec.be Web http://www.cordis.lu/esprit/home.html Check for updates to this document on the Web http://www.cordis.lu/esprit/src/projects.htm TCS 98 - i Contents Introduction iii Acronym index v Synopses Application Competences and Design 1-1 Enhancement of Technology and Manufacturing Base 2-1 Microsystems 3-1 Peripherals 4-1 ESD Best Practice and Cooperative R&D 5-1 Design Clusters 6-1 Equipment Assessment (SEA) 7-1 Basic Services and First Users Action 8-1 Networks and Working Groups 9-1 TCS 98 - ii Introduction The present volume contains synopses of projects launched since 1995 under the ESPRIT programme (Fourth Framework Programme) in Technologies for Components and Subsystems. The synopses provide brief summaries of the projects, their objectives and a list of the partners involved. Technical contact points, start dates and duration are also provided. The layout of this volume follows the thematic headings outlined below. R&D projects for components and subsystems are structured around the following technical themes: Semiconductor components and subsystems - Application competences and design The objective is to provide electronic system manufacturers with innovative microelectronics components and subsystems for their future products. Adaptation of existing technologies through close cooperation of users and suppliers to provide new features or increased functionality (portability, endurance, performance, etc.) is the primary approach to broadening microelectronics applications. Semiconductor components and subsystems - Enhancement of technology and manufacturing base By the beginning of the next century, ICs will employ upwards of 50 million transistors, 5 to 6 layers of metal wiring and clock rates of over 1 GHz. Coupled with the move towards 300 mm wafers and critical dimensions of 0.18 microns, this poses challenges to all aspects of IC technology and manufacturing. At a process level, development of equipment and advanced process modules are among the activities addressed. At a system/subsystem level, packaging issues such as fine line multilayer PCBs, semiconductor area array packages and MCMs are covered, the focus being on cost and manufacturability rather than on performance. Microsystems A microsystem is defined as an intelligent, miniaturised system comprising sensing, processing and/or actuating functions, normally combining two or more of electrical, mechanical or other properties on a single chip or a multichip hybrid. Activities in microsystems aim to stimulate the establishment of an industrial microsystems supply, to expand the application potential of microsystems components and to foster the uptake of microengineering technologies in larger systems. Application areas include the automotive, medical, environmental, industrial and consumer sectors. Peripherals Peripherals technologies cover components and subsystems for displays and mass-storage systems. In display technologies, the approach is to focus on flat slim displays; mass storage concentrates on magneto-optical systems. The following preparatory, support and transfer activities are undertaken: ESD Best practice, cooperative R&D Ongoing best practice activities in electronic systems design (ESD) aim at promoting use of state-of-the-art commercial design and validation of prototype tools to ensure the availability of future generations of design tools. Cooperative research in ESD aims at the provision of tools, methodologies and services (with emphasis on system level and mixed signal design) to industrial user companies. Design Clusters The emergence of high volume applications, in particular communications systems, that can support the development of dedicated ICs poses challenges for designers in terms of achieving increased power savings and increased integration. Added to this, efficient TCS 98 - iii design methodologies are required to ensure product development within increasingly shorter time-to-market constraints. The Design Clusters activity addresses both low power design and mixed-signal design, and focuses on methodology. Design experiments (which constitute either the low power cluster or the mixed-signal cluster) aim at developing or improving design and test methodologies for application in products. Equipment assessment The semiconductor industry is facing an ever-growing demand for components with decreasing critical device dimensions and an increasing wafer size. Up to 80% of the costs of a leading-edge wafer fab are due to manufacturing equipment alone. The Semiconductor Equipment Assessment (SEA) initiative is supporting European equipment suppliers by facilitating close links between them and global IC manufacturers. The activities include assessment of front-end, back-end, metrology, and FPD equipment. SEA 300 A new action, called SEA300, has been launched to support 300 mm equipment Demonstration Tests at European suppliers' sites by providing 300 mm wafers (blank and preprocessed) and metrology services. Basic Services and First Users action Basic Services (EUROPRACTICE) offers a cost-effective and flexible means of accessing ASICs, MCMs and microsystems technologies through the provision of consultancy, training, software tools, design support and low-volume production runs. The costs of developing ASICs for dedicated applications with low-volume production are often prohibitively high, especially for SMEs. Multi Project Wafer (MPW) runs offer a cost-effective route to ASIC design and fabrication. The First Users action (FUSE) aims to stimulate the take up of microelectronics technologies by enterprises in all sectors of industry. The application areas are many and diverse, often with niche markets. Through participation in FUSE, enterprises, in particular SMEs, learn that the implementation of microelectronics technologies provides an economically viable route to increased competitiveness. Through dissemination of actual case studies drawn from participants in FUSE, this message should be relayed to enterprises in all sectors of industry throughout Europe. Networks and working groups Networks and working groups have been set up to promote the use of advanced design technologies both in large enterprises and SMEs. In packaging and microsystems technologies, networks provide an infrastructure to facilitate the industrial cooperation needed to firmly establish design and manufacturing in these areas. TCS 98 - iv Acronym Index Acronym ABACUS ABEL ACE ACID-WG ACS ADEQUAT+ ADTV ALBATROS ALPINS AMADEUS AMIED AMITY APC APPLE ASIC4PMR AUDICO AUTOWET AWARE BAGINEA BATEL BETA BLUE BIRD CAME CATG CICDIP COCLICO Number Title 26530 Active Bus Adaptor and Controller for remote UnitS 23218 Automated Back-End European Line 24115 Advanced CMOS for Europe 21949 Working Group on Asynchronous Circuit Design 25296 Microsensor system for automatic process control in a food industry 21752 Advanced Developments for CMOS for 0.25 micron and Below 22249 ASIC Design Transfer using VHDL 22826 A Logistic Bi-directional Asyncrhonous Tagsystem for Retail OperationS 25485 Analogue Low Power Design for Communications Systems 21812 Analogue Modelling and Design using a Symbolic Environment 25249 Asynchronous Low-Power Methodology and Implementation of an Encryption/Decryption System 21261 Analogue mixed-signal sub-micron Design Test System 24030 Advanced Photomask Cleaning 21981 Advanced Polishing and Planarization Equipment 23989 Architecture for Single Chip for Private Mobile Radio 21570 Multi-chip module Automotive Digital Core for Electronics Control Unit 20757 Automated Wet Bench for critical pre-oxidation Treatments for sub-half micron Applications 22966 Anti-Collision Warning and Avoidance Radar Equipment 24364 Ball grid array inspection equipment assessment 24366 Ball Grid Array Technologies for Advanced Telecom Applications 23229 Bipolar Epitaxial Si/SiGe Technologies for RF Applications 21657 High Capacity blue source based magneto-optical disc drive dedicated to network integration 20445 Cleaning Assessment in a Mini-fab Environment 23104 Coverage Analysis and Test Generation 20628 Hot Cluster for Integrated Vapour Phases Cleaning and Processing of Dielectrics and in-situ doped Polysilicon 23246 COntact/ContactLess Interoperable microCOntroller based Smart Card system Page 6-19 2-10 2-5 8-0 3-11 2-3 5-10 1-4 6-11 1-25 6-4 1-22 7-12 7-14 1-7 1-13 7-13 3-7 7-25 2-15 2-20 4-3 7-4 5-34 7-5 1-6 TCS 98 - v COLOPODS 25475 COOL-LOGOS 25279 CORE 23237 COTRED 22350 CRAFT 25710 CUMULUS 23769 DABLP 25518 DAMASCENE 25220 DEEMO DEMOMAG 20342 22253 DESCALE 25519 DRIVE EARNEST 22103 21972 ECAM III ECU 20310 22408 EDGE EDUSA EESD 21404 20747 20702 ELDISP 22575 ELDS 23166 ELECLINE 21314 ELLIPSE 21760 EMCLO 22409 Design of a Cochlear Hearing Aid Low-Power DSP System Power Reduction through the Use of Local don’t Care Conditions and Global Gate Resizing Techniques : An Experimental Evaluation Core Processor Implementation for ADSL Telecom Applications Cost of Test Reduction: Assessment of IC Tester for High Volume and Digitized Analogue Applications CMOS Radio Frequency Circuit Design for Wireless Application Development of a generic, low cost MCM-L technology for use in portable consumer, automotive and industrial applications Low Power Exploration for Mapping DAP Applications to Multi-Processors Damascene Architecture for Multilevel Interconnections Dry Etching, Electroplating and Moulding Design and Modelling improvement of Magnetic Components in Power Electronics for Aerospace Applications Design Experiment on a Smart Card Application for Low Energy Design for Electronic Drive Control ECSI Awareness Reflection Network for ESD Technology Standards European Consortium Active Matrix III Design and Product Development of New Generation of ECU Enhanced Design of GaAs in Europe European Deep UV Stepper Assessment Enhancement of Electronic System Design by EMC Adviser System Next Generation Colour Electroluminescent Displays L-STRIPPER - Assessment of an excimer laser based tool to achieve perfect dry single step resist and polymer stripping for sub-micron technology Electrical Line for Competitive and full Compatible Household Goods, Communications and Utility Equipment Excimer Laser Lithography Project for sub-quarter micron Era EMC Design Methodologies for PCB Layout Optimisation 6-9 6-6 5-36 7-24 6-17 2-12 6-12 2-6 3-1 5-11 6-13 5-5 9-5 4-1 5-31 1-23 7-7 5-27 4-4 7-11 4-12 2-7 5-12 TCS 98 - vi EMCPCB EMMEA 20755 22206 EMW 20305 ENPROCO 22169 ESAMA 22205 ESCAPE-NET 20580 ESCHETA 26245 ESDEM 23643 EUROPRACTICE 21101 FANETA FASTTRACC FED FIPSOC FLASH PT 300 26233 20378 22659 21625 25991 FLINT FLIPAC FORCE FILL 23261 26280 20390 FORSITE FUSE GAMMA 23037 21963 21315 GAP GERTRUDE 21667 22415 GOOD-DIE 20797 GOOD-DIE NETWORK HARCODA 20796 HEARMASTER HIPERPRINT 20482 24363 HIPOCRAT 23199 20413 Using new Concepts to obtain EMC on PCBs Electromigration Monitoring Equipment Assessment Evaluation of a Highly Productive, ComputerControlled Microwave Barrel Ash System for IC Fabrication Enhanced Processor-based System for Electronic Control Applications European Scanning Acoustic Microscope Assessment Total Environment Fab Waste Gas Management via Networked and Monitored Escape Disposal Systems European Sources of Chip Scales Packages for Harsh Environment, Telecom & Automotive ESD Protection Design Methodology Promoting Access to Microelectronics Technologies for Industrial Competitiveness in Europe Failure Analysis plasma etch equipment assessment Formal Design Validation Development of a 5.2 " FED Colour Display Field Programmable System on Chip Future Leadership through assessment of high quality production tool for 300 mm Wafers Fine Line Interconnect Fine Line Interconnection an Packaging Sigma 204 Force Fill Assessment for 0.5 micron contact/via (Al/0.5 %Cu) Plug Technology in a High Volume Production Environment FORMAT Software in an Industrial Environment First Users Action Gallium Arsenide Material for Microwave Applications Gas based EHS Products for Existing Dwellings Printed Circuit Board CAD/CAM data Transfer using EDIF Get Organised Our Dissemination of Die Information in Europe Get Organised Our Dissemination of Die Information in Europe Hardware Realisation of Communication Coding Algorithms Advanced Hearing Aid Test Tools in OTICON High Performance Printed Boards and Subassemblies for Telecom and RF Applications Human implantable prosthesis offering cardiac rhythm assistance therapy 5-3 7-23 7-1 5-8 7-22 7-15 2-16 1-27 9-1 7-26 5-19 4-6 1-24 7-28 2-11 2-18 7-3 5-16 8-2 2-19 4-14 5-13 2-9 9-2 5-22 5-1 2-14 1-16 TCS 98 - vii HRAS ILETIC IMALP 20649 22072 21245 I-MODE 25702 IMPASS IMPROVE 23910 20379 IN-RAM 26320 INTACT 25190 IRMA 21796 LAMPADY LAP 25498 26261 LAPS 23929 LAYSYN LIPP 20508 20771 LOVO 25248 LP-DSP 21482 LPGD 25256 MAGIC 20360 MCC MEDID 22818 21807 METEOR 22158 MIRS MISIDESY 20679 20816 MLS 20385 MOSAREL 25340 NETPACK 21468 NEW EMPHASIS 23222 High Resolution Analytical REM In-line Ellipsometer for Thickness Control Implantable Microsystems for Augmented Liver Perfusion Low Power RF to Baseband Interface for MultiMode Portable Phones Integration of Magnetics and Passive Components In-line Monitor for Process Optimisation and Verification Intelligent RAM Component for Streaming Applications Intelligent Automotive Actuator Control & Communication Techniques Integrated Resonant accelerometer Microsystems for Automotive applications Large Multimedia Plasma Display Low cost Large Area Panel Processing of MCM-D Substrates and packages Large Area Synthetic Fused Silica Photomask Substrates for 0.18 µm CMOS Technology Physical Design Synthesis Very large flat Plasma Display Panel for Industrial Process Control Low Output Voltage DC/DC Converters for low Power Applications Low Power and cost DSP subsystems for portable products A Low-Power Design Methodology/Flow and its Application to the Implementation of a DCS1800GSM/DECT Modulator/Demodulator Magnetic Integrated Circuits for Industrial Switch and Sensor Applications Design of Motion Control Chip Microelectronics for large area, high resolution, real-time, flat, Digital Image Detectors Metrology Equipment Test for Overlay Reading for sub-half micron Technology Micromachined Integrated Relay System Closed front to back end mixed-signal ASIC Design System Design of an Interface ASIC for RISC Systems using a VHDL based "Independent" Environment Monocrystalline Silicon Active Matrix Reflective Valve Light Network for Packaging Enhanced Mobile Phone with Application Specific Memory System 7-19 7-20 3-13 6-16 2-13 7-18 1-14 3-8 3-5 4-10 2-17 7-10 1-21 4-2 6-3 1-1 6-5 3-2 5-32 1-15 7-21 3-3 5-4 5-20 4-7 9-3 1-5 TCS 98 - viii NEXUS 20713 NICE 22982 OCMP 24123 OLMO 22889 OPTIMA 23928 OPTISSIMO 22821 OSIM CHIPSET 21227 OSIM-AHSII 21499 OSSWLAN PAPRICA 23181 25476 PARFUM 20848 PARIS 22105 PASCALE 25558 PCASIC 20605 PCBIT PHOSPAP 25716 22615 PLASMON 25470 PLUTO 22106 PODSIM PREST PROSAFE 20883 25242 24097 PROXIMA 23224 QESDI QUANTUM 20455 21152 RETIMATIC 22207 Network of Excellence in Multifunctional Microsystems Real-time 3d ultrasound imaging system with advanced transducer arrays One-Chip Low Power Transceiver for Multi-Mode Portable Phones On-vehicle Laser Microsystem for Obstacle Detection Optical Proximity Techniques in Microelectronics Applications Evaluation and Demonstration of the Optical Proximity Correction and Simulation Tool OPTISSIMO Open and Scaleable Intelligent Metering System Chipset Open and Scaleable Intelligent Metering System for Advanced Home Services II Optimized Spread Spectrum Wireless - LAN Power and Part Count Reduction innovate Communication Architecture Process control and Air cleaner applications with Recognition of gases and Flavours Using a smart Microsystem Usability, Optimisation and Productivity Enhancement of the Integrated Layout Tool PARIS Parasitic Substrate Coupling Analysis by Layout Extraction Personal Computer tools for the Design of Application Specific Integrated Circuits Low Power ISDN Interface for Portable PC’s Development of Vacuum Ultraviolet (VUV) Phosphors for Large Plasma Display Panels Assessment of Advanced Plasma diagnostic tools for in-situ process Control and Monitoring Reduced Design Time using PLUTO Demonstrator Vehicle Simulator Pod supporting multiple S2m Links Power Reduction for System Technologies 6-1 Software-supported Prototyping and Real-time Implementation of Intelligent Multisensor-based Safety Control Systems Programmable Maximum Integrated Electronic Trip Quantification of ESD Economic Impact for SMEs Sensors for Chemical Species based on Luminescence Decay Time Measurement Dual Carousel semi-automatic Reticle Stocker 9-6 3-14 1-9 3-6 7-8 5-14 1-18 4-13 5-35 6-10 3-9 5-6 5-37 5-26 6-18 4-5 7-6 5-29 5-28 6-2 5-17 1-19 5-23 3-12 7-17 TCS 98 - ix ROBAS SALOMON 24359 25615 SB-USB SCARF 25599 24315 SCHINET SCOTSMAN 23223 21674 SEA SE-BN-LCD 23657 25187 SECOND SEED SEED 21680 22797 22133 SEM-A-HDL 20548 SHAPE 20763 SI_GYRO 21458 SIDOSI 20331 SIFGEN SMOG SOFLOPO 26698 21428 25403 SOGROUTE 20491 SPACE 24006 STARLIGHT 21587 STAY ON SUMMIT 20509 20492 SUPREGE 25400 SYNC 20388 SYSLINK TACTIC 20307 24268 TARDIS 25213 TIBIA-II 20485 ROBust ASICs for automotive System-level analog-digital trade-off analysis for low power Software Based Universal Serial Bus Smart Communicating Applications using Radio Frequency Single Chip ISDN Network Termination Strategic Components, Technologies and Systems in Magnetic Storage SEA 300 Surface Effect Bistable Nematic Liquid Crystal Displays Single ended Channel Conditioning Device Supplier Evaluation and Exploitation of DELPHI Software/Hardware Exploration: a European Demonstration Project Smart Energy Meter Design using novel CAD tools that support Analogue HDL modelling techniques Sub-half micron CMOS Process for European Users Silicon Surface Micromachined Gyroscope for Mass Market Applications Single Wafer highly n+ and p+ doped Amorphous and Polysilicon Deposition Software Interface Function Generator Smart Air Pollution Monitoring Network Low Power Software Development for Embedded Applications Physical Design Automation on mixed semicustom Arrays SOI for Portable Applications and Consumer Electronics The Starlight Core for Express Disk Drive Controllers ASIC Solution for Dedicated TV Camera Silicon Substrate multi-chip modules for Innovative Products A low power SUPerREGEnerative transceiver for wireless data transmission at short distances High level Synthesis of a Remote I/O for a Numerical Control System Euro-Syslink Test Applications concerted for Telecom Industry Challenges Design Clusters Technical Coordination and Dissemination Technology Initiative in BiCMOS Applications 1-17 6-15 6-14 1-20 1-11 4-11 7-27 4-8 1-2 1-26 5-7 5-25 2-2 3-4 7-2 5-38 3-10 6-8 5-2 1-8 1-10 5-24 2-8 6-7 5-21 9-4 5-18 6-1 2-1 TCS 98 - x TRAMST TRIO 25644 23042 TWICS 21785 TWIST 24137 ULTRA VISUFLEX 23806 25224 VITALISE 22203 VMUSB 23051 VSDSE 22342 YETI 22979 Transformers using MicroSystems Technology Optimally integrated vacuum/abatement/monitoring equipment for demanding semiconductor manufacturing processes (TRIO-VAMP) Technological Solutions for Wireless Communications Subsystems Twin Carrier Single Transceiver Base Station for PCS Ulsi mosT Research Activity Bistable Reflective FLC Displays on Plastic Substrates for smart cards VXI Industrial Test Applications for Liaison with IEEE 1149.1 System Environments VHDL Model of Universal Serial Bus to ISA Bus Adapter VHDL-based System Design and Simulation Environment Yield simulation and enhancement Tool YETI 3-15 7-16 1-3 1-12 2-4 4-9 5-9 5-33 5-30 5-15 TCS 98 - xi Application Competences and Design EP 21482 LP-DSP Low Power and Cost DSP Subsystems for Portable Products Summary The LP-DSP project aims at creating a capability to develop low power and low cost IC implementations of DSP applications. The capability will consist of an integrated design system, the necessary module/cell libraries and the target silicon process. The design system will be based on a state-of-the-art architectural synthesis tool that will be further developed in the project for power optimisation. The capability will be demonstrated by designing and implementing a subsystem for a mobile/cordless phone product. Objectives An ASIC hard macro implementation of a DSP subsystem of a DECT mobile phone product featuring very low power consumption, dense layout (low cost) and adequate performance. A prototype chip containing the developed ASIC hard macro and associated measurement results. A high level architectural synthesis tool capable of power consumption optimisation and allowing the use of a wide variety of application specific execution units. A library of DSP modules that can be used as application specific execution units in the above mentioned synthesis tool. A library of standard cells for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption. A library of macros and layout generators for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption. Interfaces that are needed between the developed/existing tools/libraries to provide a seamless design path for ASICs. Participants NOKIA (SF), SGS-THOMSON MICROELECTRONICS (F), EUROPEAN DEVELOPMENT CENTRE N.V. (B), TAMPERE UNIV. OF TECHNOLOGY (SF) Contact Point Klaus KRONLOF Nokia Research Center P.O. Box 45 Fin-00211 Helsinki (Finland) Duration 30 months from 15.02.96 tel: +358 0 4376 6510 fax: +358 0 4376 6857 E-mail: klaus.kronlof@research.nokia.com 1-1 1. Application Competences and Design TCS 98 EP 21680 SECOND Single Ended Channel Conditioning Device Summary The continuous growth of the subscriber base in current mobile systems, i.e. Digital European Cordless Telecommunication, (DECT), system provides a motive to seek new ways of increasing the capacity on offer. One approach is to improve signal quality by using advanced signal processing techniques. The added value of this approach with respect to already existing solutions, namely HDSL and ADSL, is that the signal processing will only be done at one line termination of the digital local line. This contrasts with HDSL that requires signal processing at both line terminations of the digital local line. The outcome of these activities will be a connector-like module attachable between Base Station (BS) and the wire towards the Base Station Controller (BSC). Improvement of the air interface of DECT with the same single-ended concept to make it robust against multipath propagation will also be addressed. Objectives The main objective is to develop a self-contained, very low volume, remotely powered signal conditioning subsystem to improve, for current DECT picocell system, the link quality in both directions of the communication in the wire interface between BS and BSC. The ultimate goal is to integrate this conditioning mechanism in a connector-like module for BS to BSC links allowing wire links up to 3 km. To demonstrate in field trials the performance and feasibility of the device. Secondary goals whose achievement is crucial for accomplishment of the main goals are: To develop an ASIC capable of performing, in one single location, channel conditioning for bidirectional end-to-end links. To develop a high density DC/DC conversion module, incorporating advanced packaging of magnetic devices, to be included in the connector-like solution to allow remote powering for both functions in the conditioning device and BS from BSC. To demonstrate the signal conditioning architecture by means of a suitable feasibility model for the radio link, to achieve BER=10-3 at 200 ns of delay spread. Participants ALCATEL SESA (E); UPM (E); IMEC (B); ALCATEL MIETEC (B); NMRC (IRL); CETECOM (E) Contact Point Mariano Perez ABADIA ALCATEL SESA Ramirez de Prado 5 28045 Madrid (Spain) Duration 24 months from 01.03.96 tel: +34 1 3304792 fax: +34 1 3305089 E-mail: abadia@seiv10.rpi.ses.alcatel.es 1-2 1. Application Competences and Design TCS 98 EP 21785 TWICS Technological Solutions for Wireless Communications Subsystems Summary Micro miniature radio hardware solutions are to be developed for mobile phone and Wireless Local Area Network (W-LAN) applications. Existing advanced IC, MCM, interconnection and subsystem integration technologies will be modified and optimised to provide reduced cost, smaller size and lower weight, portable communications product components. The integration of the TWICS technologies will be demonstrated in a set of wireless communications hardware functions. Objectives The modification and unification of existing advanced IC, MCM, interconnection and subsystem integration technologies to realise lower cost, smaller size and lower weight wireless communications subsystems hardware. The generation of integrated design rules for the optimised IC, RF MCM-D, circuit card and assembly integration technologies. The design and manufacture of cellular radio function components, using MCM-D technology for RF integration, chip sized IC packaging and advanced circuit card technologies. The design and manufacture of a flip chip MCM technology demonstrator for a 5.2 GHz W-LAN application. Participants GPS (UK); ERICSSON MOBILE COMMUNICATIONS (S); STP ELEKTRONISCHE SYSTEME (D); GMMT (UK); BULL (F) Contact Point Professor David J. PEDDER GEC Plessey Semiconductors Cheney Manor Swindon Wilts SN2 2QW (United Kingdom) Duration 24 months from 01.02.96 tel: +44 1 793 518398 fax: +44 1 793 518401 E-mail: dpedder@lincoln.gpsemi.com 1-3 1. Application Competences and Design TCS 98 EP 22826 ALBATROS A Logistic Bi-directional Asyncrhonous Tag-system for Retail OperationS Summary Retail Business is involves three different type of operations, all of them strongly based on product identification systems: * Logistic operations (control of the different states that items can pass through) * Sales operations (computer aided check-out, goods returns, money refund,...) * Security operations (basically Electronic Article Surveillance, EAS systems) Nowadays, the most popular method for goods identification is the bar-code system. This method requires the alignment of individual goods in front of an optical reader. It is prone to errors due to label abrasion or misalignment with the reader and does not provide a solution for the three operational problems above mentioned. New technology is required to implement a cost-effective identification system for goods and products that can offer functionalities which satisfy three operation areas of the retail business; allowing: * Identification with high reliability for logistic operations * Automatic check-out for sales operations * EAS System for security operations The technology developed in ALBATROS will enable retailers to put in place tag electronic identification systems which will greatly improve many aspects of the retail business. Objectives The aim of ALBATROS is the development of a new identification system for goods and products that can be used in the areas where product identification is needed and using just one tag independently of the type of identification required. The objective of the unique tag to be developed under this project is to provide higher reliability in the logistic operations, enable automatic check out in our stores and make the EAS system more efficient. The tag will use RF/ID technology. The areas covered will be ASIC, Tag, R/W equipment and the Information System. The project results will be shown in a pilot installation which will be set up in a selected department of ECI’s Department Stores. The results will be applied in different steps, starting from products of higher value in the garment area to reach the ultimate goal of the project that is to identify all products in the supermarket. Participants INFORMATICA EL CORTE INGLES (E), MIKRON (A), EL CORTE INGLES (E), PHILIPS (D) Contact Point Rodrigo BECERRA Informatica El Corte Inglés, S.A. Travesia Costa Brava, 4 28034 MADRID (Spain) Duration 24 months from 01.11.1996 tel: +34 1 387 47 00 fax: +34 1 734 47 76 E-mail: 101356.3430@compuserve.com 1-4 1. Application Competences and Design TCS 98 EP 23222 NEW EMPHASIS Enhanced Mobile Phone with Application Specific Memory System Summary The aim of the project is the development of an application specific memory integrating flash and EEPROM functions on the same chip for use, amongst others, in cellular phone applications. This innovative semiconductor device will be developed by the semiconductor company, SGS-Thomson, to the specifications determined by cellular phone manufacturer Nokia who will include the device in a phone demonstrator. Characterisation and process reliability studies will be undertaken at the IMEL research institute. A new non-volatile memory cell concept will be developed in order to integrate both flash and EEPROM memory structures on the same chip without any increase in manufacturing complexity. Objectives The main objective of the project is to deliver a full featured 1.8GHz GSM phone incorporating a prototype of the integrated embedded applications specific memory system developed in the project. The prototype phone will be tested with the Nokia standard validation procedure which includes, amongst others, durability testing at high and low temperatures; The application specific memory will be initially manufactured in 0.6 µm technology and be shrinkable to 0.5 µm. The successful completion of the project will provide the opportunity for SGS-Thomson customers to have developed application specific memories combining customisable quantities of flash and EEPROM function for use in a very broad range of market sectors. Participants SGS-THOMSON (I), NOKIA NMP (SF), SGS-THOMSON (F), IMEL (GR) Contact Point Dr. Giulio IANNUZZI SGS-Thomson Microelectronics via Olivetti, 2 20041 Agrate Brianza, (Italy) Duration 18 months from 01.10.96 Tel: +39 39 603 5028 Fax: +39 39 603 5233 E-mail: giulio.iannuzzi@st.com 1-5 1. Application Competences and Design TCS 98 EP 23246 COCLICO COntact/ContactLess Interoperable microCOntroller based Smart Card system Summary The COCLICO project aims at the development of an interoperable bi-compatible contact/contactless Smart Card system based on a secure single chip microcontroller. The main target application is a combined Transport Ticketing and Electronic Payment card. The COCLICO project will develop a Smart Card System that combines ISO7816 contact with “remote coupling” (10 cm distance) contactless operation. The COCLICO microcontroller IC and its tailored microcode will provide the high security level required for banking applications, with the necessary programmable flexibility to adapt the security algorithms to national regulations or specific application needs. It will also feature the contactless operation required for public transport ticketing applications with a fast transaction time. The COCLICO terminal interface IC and its associated control software will assure Card-toTerminal and Terminal-to-Card compatibility established in this system specification for contactless operation. Objectives Specification and performance that meet world-wide market needs and standards R&D and design of a contactless/contact secure microcontroller chip R&D and design of a companion terminal Interface chip Development of a cost effective Smart Card assembly process Break-through in low-cost Terminal architecture Stable and secure microcode for the contactless functions of the Smart Card and Terminal Subsystem Scientific contributions to the emerging ISO 14443 standard for contactless type 2 systems Participants GEMPLUS (F), MOTOROLA (CH, UK, F), AMEX (UK), SISTEMA 4B (E) Contact Point Olivier TREBUCQ GEMPLUS rue Guynemer, 34 92447 ISSY LES MOULINEAUX CEDEX (France) Duration 24 months from 01.09. 96 tel: +33 1 46 48 20 32 fax: +33 1 46 48 20 03 E-mail: olivier.trebucq@ccmail.edt.fr 1-6 1. Application Competences and Design TCS 98 EP 23989 ASIC4PMR Architecture for Single Chip for Private Mobile Radio Summary The project will provide telecommunication equipment manufacturers with the capability to integrate using a single ASIC all the baseband and control circuitry of a digital radio terminal compliant with the TETRA and TETRAPOL standards. These terminals represent 30% of the private mobile radio (PMR) market, and this projects enables lightweight terminals with long battery life to be realised. Key analogue elements of the project are the Mixed-Signal Cells, I/Q RF Codec and CCITT Voice Codec. The analogue work will build on the design know how and the cells produced in ALCD Project, ESPRIT 8030 which now form part of ATMEL’s pre-characterised standard cells library. Digital design will focus on integrating the ARM7TDSP combined controller/DSP (Thumb/Picollo) core which provides a state-of-the-art performance and low power dissipation for implementing the control and baseband processing functions. This work will also include further development of the real-time operating systems and high level language programming tools to enable optimised algorithmic-level DSP compilation. Objectives Realisation of analogue and digital building blocks targeted to ASIC implementation of control and baseband processing for TETRA/TETRAPOL private mobile radio systems; Realisation of single chip control and baseband processing ASIC integrating analogue, embedded controller and digital signal processing function blocks; Development and demonstration of an enhanced real-time operating system and debugger for the target applications; Development and demonstration of an optimising compiler for the Picollo DSP core; Development of user development boards; Partners, Matracom and OTE, will incorporate the ASICs into terminal demonstrators for the TETRAPOL and TETRA systems respectively. Participants ATMEL (F), ARM (UK), THERA (I), IST (P), MATRACOM (F), OTE (I) Contact Point Ben ALTIERI, ATMEL/ES2 13106 Rousset Cedex, (France) Duration 24 months from 01.12.96 Tel: +33 4 4253 6194 Fax: +33 4 4253 6323 E-mail: b-altieri@es2.fr 1-7 1. Application Competences and Design TCS 98 EP 24006 SPACE SOI for Portable Applications and Consumer Electronics Summary A cost effective production process developed by LETI to produce SOI (Silicon on Insulator) wafers, with very low defect density, is at the origin of this project. In the SOI approach, the oxide layer under the drain and the source of the MOS transistors considerably reduces the parasitic capacitance of inverters and gates, especially at low supply voltages (below 1V) where the junction capacitance starts to increase exponentially. So below 1V the low power advantage of SOI is dominant and the cost per SOI transistor will be equal to the cost of a bulk CMOS-epitaxial transistor. The reduced parasitics also give SOI technology superior RF capabilities to bulk CMOS. The objective of the project is to develop the 0.25m SOI technology at LETI in Grenoble and to transfer it to the production fab of ST in Crolles. The capabilities of the technology will be demonstrated with a GSM receiver -from RF to a serial digital I/Q baseband interface- by Alcatel, with some design activities subcontrated to Dolphin and Swindon Silicon Systems.UCL will contribute to the project with modelling of transistors and passives. Objectives Perform a technical demonstration of the core CMOS/SOI technology at 1.8V supply voltage on a 200mm wafer. Develop passive components (resistors, capacitors, inductors) on SOI for analogue functions. Measure HF characteristics of the technology and the dynamic performance in terms of speed, maximum frequency, power consumption and crosstalk. Develop a complete design kit for mixed A/D applications. Design the specific building blocks for a single chip GSM receiver. Prepare the industrialisation and study the cost of ownership, reliability, quality, cost and volume production conditions of 200mm SOI. Demonstrate full integration of the 0.25m mixed A/D CMOS/SOI technology at the IC manufacturer site. Perform the demonstration of feasibility of a single chip radio-telephone function for the 900MHz GSM portable telephone applications. Participants ALCATEL (B), SGS-THOMSON (F), LETI (F), UCL (B) Contact Point Jan SEVENHANS ALCATEL BELL Francis Wellesplein 1 2018 ANTWERPEN (Belgium) Duration 30 months from 01.01. 97 tel: +32 3 240 87 52 fax: +32 3 240 99 47 E-mail: jsev@sh.bel.alcatel.be 1-8 1. Application Competences and Design TCS 98 EP 24123 OCMP One-Chip Low Power Transceiver for Multi-Mode Portable Phones Summary The OCMP project will apply proven analog low power design techniques to develop a single chip radio frontend for multi-mode (DCS1800 & DECT standards) hand portable terminal. It will include frequency synthesizer components, up/down converter blocks and amplifier blocks, such as LNA and prepower amplifier. The aim of the project is to prepare the way for the commercial availability of such an innovative component assisting significantly the small system companies which manufacture portable terminals and wish to enter the multi-mode terminal market. Objectives The main objective of the OCMP project is to provide the market with a highly integrated low power transceiver chip, which addresses two modes of operation, DCS1800 and DECT, and can be used in future generation multi-mode terminals. The chip will contain high frequency bipolar circuits including frequency synthesizer components, up/down converting mixers, 900 phase shifters, LNA, etc. The direct conversion architecture will be adopted for the transceiver, thus allowing the maximum possible integration and, compared to the classical heterodyne approach, requiring fewer external components. A single mode DECT transceiver chip with direct conversion architecture will also be developed. This development, combined with existing partners’ research results in a DCS1800 transceiver test chip development, will contribute to the definition of the multimode transceiver chip specifications. Compliance to DECT and DCS1800 modes will be demonstrated using the multi-mode transceiver chip in a multi-mode terminal demonstrator by verifying proper operation in each individual mode. The extension of the transceiver chip to the GSM standard will be studied. Participants INTRACOM (GR); SGS-THOMSON MICROELECTRONICS (I), TELITAL (I), SWINDON SILICON SYSTEMS (UK) Contact Point Mr. Dimitris DERVENIS INTRACOM S.A. 19,5 km Markopoulou Ave 19002 Peania, (Greece) Duration 30 months from 01.01.97 Tel: +30 1 6860456 Fax: +30 1 6860312 E-mail: dder@intranet.gr 1-9 1. Application Competences and Design TCS 98 EP 21587 STARLIGHT The Starlight Core for Express Disk Drive Controllers Summary The trend in the drive industry is towards higher integration of disk functions into fewer monolithic devices. Current drive designs use 16-bit micros; in multiple high-density devices, performing drive functions such as servo control, disk control, host control and read/write data transfer. In the move towards a 'drive-on-a-chip', these micros cannot deliver the processing bandwidth necessary to carry out these real-time functions. New 32-bit architectures such as the ST20 have five to ten times the processing power of the current micro solutions being used. In addition, the integration of DSP-type functions such as hardware multipliers further relieves the processing burden on the micro-core. By upgrading to machines such as the ST20, the disk architect benefits from MIP increases due to more efficient instruction sets; greater data bandwidth and DSP functionality. The processing benefits of a 32-bit move have been evident for some time. The drive industry has applied pressure on microprocessor architects to provide the functionality described above, but at a cost in die area that was not feasible in the industry. STARLIGHT is to demonstrate that these issues can be successfully addressed by the ST20 and that the time is now right for this 32-bit move. Objectives Design and manufacture a reduced-size micro-core (STARLIGHT core) optimised for disk drive applications. Develop a family of disk drive subsystems to enable silicon integration for customer specific solutions. Produce an integrated simulation model (VHDL) of the STARLIGHT core family with application specific subsystems developed for the disk drive controller. This will provide a prototype to demonstrate the state-of-the-art 32-bit solution to potential customers. Development of software support for STARLIGHT core applications. Suitable software support to allow systems to be developed and debugged together with the necessary compiler development to target the reduced instruction set core. Participants SGS-THOMSON MICROELECTRONICS (F), SILICON SYSTEMS DESIGNS (IRL) Contact Point Victoria GRIFFITHS SGS Thomson Microelectronics Ltd 1000 Aztec West Almondsbury Bristol BS12 4SQ (United Kingdom) Duration 18 months from 15.04.96 tel: +44 1454 616616 fax: +44 1454 617910 1 - 10 1. Application Competences and Design TCS 98 EP 23223 SCHINET Single Chip ISDN Network Termination Summary ISDN constitutes an important step in providing links which connect society to the information highway by expanding the bandwidth of the standard telephone gateway to a rate of four times higher than a sophisticated modem. In this project Alcatel Mietec and Quante will join forces to develop circuit techniques and macroblocks which can be used to create a high performance single chip ISDN Network Terminator. The resulting chips will cut costs and power dissipation down to the level required for open market proliferation. This mixed-mode ASIC will contain advanced design techniques that combine complex digital circuit of up to 300,000 transistors including embedded data processors together with high performance analogue circuits delivering 12 bit accuracy at 15MHz sampling speeds. Objectives Development of a single-chip Network Terminator for ISDN with minimum pincount and external components incorporating the following characteristics. - fully ANSI and ETSI compliant U interface - fully ITU compliant S interface - two wire transmission NRZ 2B1Q 64 and 144 kbits/sec - maintenance and service information signalling, possibility to read out the state and coefficients - automatic polarity adaptation, automatic gain control - DSP with adaptive echo cancellation and decision feedback equalisation - evaluation of the sampling instant by digital phase-locked-loop - fast return to operation after line seizure due to data storage during power down state, activation and deactivation including loop-control - GCI interface for extended applications (NT plus mode) Key macroblocks developed within the project will be accessible to third parties via the Alcatel-Mietec design library. Participants ALCATEL MIETEC (B), QUANTE (D) Contact Point Dr. Edmond JANSSENS Alcatel Mietec Westerring 15 B 9700 Oudenaarde (Belgium) Duration 18 months from 01.10.96 Tel: +32 55 33 22 11 Fax: +32 55 33 26 47 E-mail: ed_janssens@mietec.be EP 24137 TWIST 1 - 11 1. Application Competences and Design TCS 98 Twin Carrier Single Transceiver Base Station for PCS Summary In radio local-loop (RLL) applications for dense scenarios, traffic is the most demanding parameter. This is in contrast to a low density scenario where coverage is of paramount importance. The maximum amount of traffic handled in a cell site is limited by the handling capabilities of the installed equipment and by the level of interference caused by users in the cell or adjacent cells. Analysis of cost/traffic ratios leads to the conclusion that an optimal configuration corresponds to the colocation of two transceivers per sector. The TWIST project intends to further improve this solution. The goal of the project TWIST is to develop the core device of a novel DECT transceiver architecture capable of supporting two simultaneous communications (in TDD systems) requiring one single RF front-end. The architecture is based on the principle of image separation. Objectives There are two objectives : To develop the core component for a double channel single transceiver base station. To demonstrate the functionalities of the device as well as the feasibility of the concept. A demonstrator will be built and laboratory measurements will be carried-out and reported. Participants ALCATEL STANDARD ELÉCTRICA S.A. (E); UNIVERSIDAD POLITÉCNICA SWINDON SILICON SYSTEMS LTD (UK); ALCATEL MIETEC (B). Contact Point Alfonso FERNÁNDEZ-DURÁN, Alcatel Standard Eléctrica S. A. Ramírez de Prado, 5 Madrid 28045 (Spain) DE MADRID (E); Duration 24 months from 01.01.97 Tel: +34 1 330 4792 Fax: +34 1 330 5090 e-mail: afd @alcatel.es 1 - 12 1. Application Competences and Design TCS 98 EP 26320 IN-RAM Intelligent RAM Component for Streaming Applications Summary The IN-RAM project (INtelligent RAM component for streaming applications) is aimed at providing a high performance IC component, optimized for interfacing and buffering multiple high bandwidth streaming data (e.g. video streams, high speed telecommunication data, computer I/O, etc.). Based on the features of IN-RAM and the resulting simplifications in system design, it is expected that commercial realizations of IN-RAM will capture a significant market share in the area of custom memory and interface components. Moreover, IN-RAM plans to improve the current state-of-the-art in building efficient technology to incorporate large regular structures (DRAM) together with complex high speed logic in a way that minimizes die size as well as manufacturing cost. The focus regarding this objective is not only in the VLSI manufacturing process, but also in the design approach and the utilized CAE tools. The IN-RAM approach will offer the following innovative characteristics: i) Integrated single chip solution, manufactured using state of the art VLSI technology. ii) A scaleable IN-RAM architecture will lead to the development of a family of IN-RAM compliant components. The project developments will be supported by a complete exploitation roadmap by the industrial partners and in particular by the semiconductor vendor (SGS Thomson). Objectives Design and develop a highly competitive IN-RAM component, using state of the art tools and technology. Define the overall specifications and architecture of the IN-RAM component based on the requirements of potential users and applications. Minimize the development risk of the component. This goal will be pursued mainly during design time, investigating implementation alternatives. Demonstrate the feasibility and usability of the component by embedding it into high performance subsystems. The IN-RAM component’s capabilities will be verified and demonstrated within the project. The IN-RAM component will be integrated in two application systems. Participants ITALTEL (I), INTRACOM (GR), NTUA (GR), SGS-THOMSON (I), SOLINET (D) Contact Point Duration Luigi VERRI ITALTEL, Central R&D Palazzo Laboratori, C02 I-20019 Settimo Milanese (Italy) 24 months from 1.1.1998 tel.: +39.2.4388.8299 fax.: +39.2.4388.7989 E-mail: Luigi.Verri@italtel.it 1 - 13 1. Application Competences and Design TCS 98 EP 21570 AUDICO Multi-chip Module Automotive Digital Core for Electronics Control Unit Summary A low cost existing MCM technology, based on laminated substrate (MCM-L) has been developed for telecom and computer applications. The main content of the work will consist in adapting this technology to meet automotive harsh environment requirements. The packaging and assembly techniques will be exploited to the high volumes series. Other topics addressed in this project include reliability, testability, modelling (thermomechanical and power dissipation) and implementation of a KGD technology for automotive cost and reliability requirements. Integration of passive components and MCM compatibility with insulated Metallic Substrate (Automotive Mother Board Substrate) are critical issues which are also addressed by AUDICO. The demonstration of this approach will be achieved by realising the digital core of an Electronic Control Unit including microprocessor, associated memory and the interface circuit. Objectives To make available MCM technologies for automotive subsystems in order to solve the integration problem common to future electronics automotive systems with cost efficiency. To transfer the results of the programme into production on a short time-scale. To open Known Good Die availability in a flip chip configuration. Participants SAGEM (F); ROVER (UK); BULL (F); MOTOROLA (D); TU-B (D). Contact Point Jean-Paul ROUET SAGEM SA 27 rue Leblanc 75512 Paris Cedex 15 (France) Duration 24 months from 01.02.96 tel: +33 1 40 70 62 96 fax: +33 1 40 70 66 64 1 - 14 1. Application Competences and Design TCS 98 EP 21807 MEDID Microelectronics for Large Area, High Resolution, Real-Time, Flat, Digital Image Detectors Summary Professional markets (medical, factory automation, etc.) have increasing need for real-time direct digital image sensors, of large area, small thickness, high resolution and high reliability, for operation in specific environments. Present sensors do not meet all these requirements. MEDID aims to develop a high sensitivity flat panel detector prototype of large area (~40x40 cm), high resolution (pixel pitch ~ 140 micron) and high image processing capability (> 1 GOPS). The detector will meet user/end-user needs for digital real-time radiography, including the high reliability and endurance required by medical and industrial environments. This detector subsystem will allow significant application innovation including the possibility of radiological film substitution, lower irradiation dose and exploitation costs, and immediate electronic image availability. Objectives The proposed high resolution detector subsystem will build on existing expertise and prototypes. It will be based on an active matrix sensor where each pixel is made of thin film amorphous silicon photodiodes acting as sensitive elements coupled to switching diodes. Silicon Sensor Panel Technology taking advantage of microelectronic technologies is actually the best candidate to fulfil advanced real-time digital imaging requirements with cost-effective solutions. High data volume/real-time pre-processing electronics will be also developed. These components will be integrated in a digital detector which will be tested under working conditions to meet application needs. Marketing of the resulting detector is expected within one year after project completion. Results after one year Design is complete and full size prototypes are in progress. A small demonstrator provides a high quality radiological image. Participants THOMSON TUBES ELECTRONICS (F); SIEMENS (D) Contact Point J. CHABBAL Thomson Tubes Electronics 18, Avenue du Maréchal Juin 92366 MEUDON LA FORÊT (France) Duration 24 months from 01.03.96 tel: +33 76574023 fax: +33 76574048 1 - 15 1. Application Competences and Design TCS 98 EP 23199 HIPOCRAT Human implantable prosthesis offering cardiac rhythm assistance therapy Summary The project is aiming to develop a miniature low power hybrid circuit devoted to human implantable cardiac prostheses (pacemakers and defibrillators) which are light weight, highly reliable, battery powered systems. A family of three integrated circuits using the most advanced technologies based on submicronic mixed ANALOG/DIGITAL BiCMOS and HIGH VOLTAGE protection processes will be designed. The size reduction is achieved implementing a plastic chip scale packaging process. Objectives Design of a complete highly reliable, low power, hybrid electronic circuit implying the development of three ASICs and a substrate encompassing the packaged dies and required external components. Two ASICs will be designed using low voltage "BiCMOS5" process from ST: a mixed chip integrating all the specific prostheses functions and a 8 bit microcontroller with fast telemetry function. A protection and interface circuit will be realised using the high voltage "CBZ" process from AMS. Adaptation of 0.5µm BiCMOS process design kit: new devices generators and cells in MENTOR GRAPHICS environment; characterisation of the digital library at 1.5V instead of 3.3V for low power design. Integration of the high voltage "CBZ" process in MENTOR GRAPHICS environment with specific devices and adaptation to low power requirements. Implementation of a chip scale plastic packaging at wafer level suitable for ASICs and silicon microsensors. Participants ELA MEDICAL (F); SGS-THOMSON (F); AMS (A); SYNDESIS (GR) Contact Point Thierry LEGAY ELA RECHERCHE Centre d'Affaires La Boursidière 92357 LE PLESSIS ROBINSON (France) Duration 24 months from 01.10.96 tel: + 33 1 46013457 fax: + 33 1 46013355 E-mail: 100634.3435@compuserve.com 1 - 16 1. Application Competences and Design TCS 98 EP 24359 ROBAS ROBust ASICs for automotive Summary Increased functionality in automotive safety, performance/economy, and comfort requires an ever increasing electronic content in modern motor vehicles. Additionally bus-wiring systems and increase integration level often push the electronic functionality temperature, humidity and electrical disturbance signals. On the other hand customers demand improved reliability, with component failure rates at the ppm level, simultaneously with the increased complexity. ROBAS addresses the issue of improved reliability in the hostile environment and describes improvements at all levels in the ASIC design and manufacturing chain. Objectives ROBAS partners will further “ruggedise” automotive ASICs with regard to handling and use, by improving ASIC specification and actual performance in the areas of ESD protection, sensitivity and emission of Electromagnetic Disturbances (EMC) and insilicon disturbances by substrate coupling and transmission effects. Reliability levels of less than 10ppm failures without expensive burn-in screening will be sought by “designing-in” and “building-in” reliability with such measures as wafer-levelreliability (WLR) practised in manufacturing and improved fault simulation and built-in test features during design. Operation and performance at increased ambient temperature, form the present 85°C up to 135°C will be targeted and implemented. Two robust ASIC demonstrators will be developed to demonstrate the improvements achieved by the project. These will be a radio-security-key and a general purpose chassis ASIC with µP core for security applications. Participants LUCAS AUTOMOTIVE (UK), BMW (D), LAND-ROVER (UK), ELMOS (D), DOLPHIN INTEGRATION (F), PES (D) Contact Point Ms Gail PERRINS LUCAS Windrush Park Road Witney OX8 5EX OXON (United Kingdom) Duration 24 months from 15.01. 97 tel: +44 1993 776900 fax: +44 1993 776420 E-mail: gail@lisspwit.li.cu.uk 1 - 17 1. Application Competences and Design TCS 98 EP 21227 OSIM-CHIPSET Open and Scaleable Intelligent Metering System Chipset Summary The chipset developed in the OSIM chipset project will provide a cost effective way of implementing communication between the electricity utilities and their customers. This project will run in close cooperation with the OSIM AHSII project that treats the development of equipment for the communication gateway. The project includes the development of three integrated circuits namely the Power Line Carrier Modem, the line driver and a generalised interface to a metering device. Objectives The project is aimed at the development of a chipset that will consist of three devices: The PLC Modem This modem chip formats data sent or received via the power line. The modulation type is Spread-Frequency Shift Key in the 50 kHz to 100 kHz frequency band, with a baud rate of 1200 baud. The protocol will be handled via an external microprocessor. Frame synchronisation, deframing and error correction will be done internally by embedded logic. It will comply with the Cenelec standards EN 500651. The Metering Device Interface Will provide the electrical interface with the electricity, gas, water and heat meters within the cost constraints. It has to fulfil the major standards IEC 1107, IEC 1142 and DIN 43.864 or 50 interface. The circuit should also contain the necessary driver, signal conditioning circuitry and protection against disturbances. The Driver Circuit Will provide the high driving current (250 mA) and signal conditioning of the output and input signals such as amplitude limiting and AGC for the input signals. Participants ALCATEL MIETEC (B); LANDIS & GYR (CH); ALCATEL SESA (E) Contact Point dr. Edmond JANSSENS Alcatel Mietec Westerring 15 9700 Oudenaarde (Belgium) Duration 24 months from 01.01.96 tel: +32 55 332211 fax: +32 55 332647 E-mail: ed_janssens@mietec.be 1 - 18 1. Application Competences and Design TCS 98 EP 23224 PROXIMA Programmable Maximum Integrated Electronic Trip Summary Actuator trip units of an electricity circuit power breaker suffer from lack of accuracy which limits their installation and exploitation. The use of electronic actuator trip units consisting of a single mixed mode ASIC would not only allow an economical implementation of the required accuracy, it would also allow additional functionality such as programmability for greater flexibility and remote monitoring of individual loads via the EMS TP0 Home Systems Communication interface. The biggest challenge for the circuit is the design of a high sensitivity front end for equipment that switches currents of several thousands of amperes. Objectives To realise an electronic trip unit based on a single ASIC with the following specification - current range 200A to 200 000A - 0.1% relative accuracy - fully compliant with EMC, mechanical and climatic standards - protection modes: instantaneous, short time, long time, ground fault. To develop an ASIC that contains the analogue interface for the trip unit and includes the required functionality. To design an analogue front end with 12 bit accuracy and low offset 50-100µV. Participants ALCATEL MIETEC (B), SCHNEIDER ELECTRIC (F) Contact Point dr Edmond JANSSENS Alcatel Mietec Westerring 15 B 9700 Oudenaarde (Belgium) Duration 24 months from 01.10.96 Tel: +32 55 33 22 07 Fax: +32 55 33 26 47 E-mail: ed_janssens@mietec.be 1 - 19 1. Application Competences and Design TCS 98 EP 24315 SCARF Smart Communicating Applications using Radio Frequency Summary A low-cost, single-chip RF IC transceiver suitable for consumer as well as industrial and commercial applications is to be developed. This component will be accompanied by development tools (in the form of ready-to-use demonstration circuits and software libraries for standard microcontrollers) enabling the development, testing and validation of low power RF applications. The component will be integrated and validated in a commercial application, Automatic Meter Reading, and will demonstrate its viability in the domain of Home Systems in the process. The goal is to reduce the cost and performance barriers to the mass scale implementation of low-power RF applications. Objectives A highly-integrated, low-cost bidirectional RF transceiver developed using an advanced BiCMOS4 technology, ensuring low power consumption and operation at high frequency. Tools for RF hardware and application design in the form of development kits and software libraries for a range of microcontrollers. Equipment and methods for conformance testing in accordance with established standards, to ensure that the RF medium and resulting applications developed on the basis of the RFIC conform with established norms. A commercial application utilising the new RFIC as its hardware base and providing a means to automate meter reading in the utility industries (electricity, gas, water and heat) and entry into the Home Automation (HA) segments in Europe. Participants ITRON SA (F); SGS-THOMSON MICROELECTRONICS (F); TRIALOG SA (F); ITRON LTD (UK); UNIVERSITY OF BRISTOL (CENTRE FOR COMMUNICATIONS RESEARCH) (UK). Contact Point Joseph GRANT Itron SA Immeuble Merblanc 1, rue du Port au Prince F-38200 Vienne (France) Duration 24 months from 06.01.97 tel: +33 04 74 31 51 63 fax: +33 04 74 85 36 64 E-mail: 73423.1111@compuserve.com 1 - 20 1. Application Competences and Design TCS 98 EP 20508 LAYSYN Physical Design Synthesis Summary The challenges of high density, complex circuitry and the demands of new substrate and packaging technologies impose progressively greater pressures on PCB and MCM designers. In addition, the pressure to reduce time-to-market is a constant requirement. These demands require new developments in CAD tools to allow designers not only to take into account a huge set of constraints imposed by circuit speed, manufacturing requirements, thermal performance, and the specifications of reliability and EM interference, but also to perform the design function in shorter time frames on the way to achieving complete design "compilation" or "synthesis". Objectives To provide tools which support the effective design of PCB/MCMs using current and newly emerging technologies. To provide a unified environment in which the placement and routing activities can be considered together, with constraints and design rules from either discipline being obeyed simultaneously. To increase the productivity of PCB/MCM designers to allow demands of decreasing time to market targets to be met. The project will validate the tools and work practices in commercial design environments. The users are committed to using the tools developed on real production designs and, if successful, to adopt them into their design departments. The results will be progressively delivered to the market by the EDA vendor partner. Participants ZUKEN REDAC (UK); ICL (UK); THOMSON MULTIMEDIA (F); BULL (F), SNI (D). Contact Point Roy DAVIES Redac Systems Ltd. Green Lane Tewkesbury GLOS GL20 8HE (United Kingdom) Duration 36 months from 02.01.96 tel: +44 1684 294161 fax: +44 1684 850873 E-mail: roy_davies@redac.co.uk 1 - 21 1. Application Competences and Design TCS 98 EP 21261 AMITY Analogue/Mixed-Signal Sub-Micron Design Test Bench System Summary The software tools and methods developed in the project will be defined in a close collaboration between a leading mixed-signal application user company in the automotive and communications electronics sector (Robert Bosch GmbH) and a leading vendor in mixed-signal design verification (MicroLEX Systems A/S). The toolset developed will include software (virtual) instrumentation for the verification and test of mixed-signal ASICs and will be presented and accessible through a user friendly engineering interface. The project will focus on the development of a number of specific automotive and communications systems tools, however, the use of virtual instrumentation methods will enable rapid adaptation of the solutions to suit related circuit functions. Objectives The objectives of the project are to develop and demonstrate innovative analogue and mixed-signal test techniques and tools including novel implementations of advanced algorithms for digital signal processing type testing. The project will assess the viability of alternative methodologies and tools for analogue and mixed-signal test and verification of CMOS and bipolar technologies, in particular for sub-micron CMOS based ICs and subsystems. The first set of solutions will be focused on circuit structures typically found in automotive and communication electronics. A ß-release of the design test-bench tools will take place during the project and ß-type testing of these prototype tools will be undertaken using several in-house electronic subsystem demonstrators. The project results will form the basis for a commercial release of the tools after the end of the project. Participants ROBERT BOSCH GMBH (D); MICROLEX SYSTEMS A/S (DK). Contact Point Dr. Wilfried TENTEN Robert Bosch GmbH K8/EIS2 Postfach 13 42 72703 Reutlingen (Germany) Duration 34 months from 01.12.95 tel: +49 71 21 35 29 86 fax: +49 71 21 35 17 46 E-mail: wilfried.tenten@rt.bosch.de 1 - 22 1. Application Competences and Design TCS 98 EP 21404 EDGE Enhanced Design for GaAs/Si in Europe Summary The overall objective of EDGE is to provide a new, user-oriented and commercially-driven CAD resource to support high-frequency analogue design in Europe, specifically targeting linear and non-linear MMICs, as well as interconnect structures, for operation from 0.1 GHz to 100 GHz and beyond. The project’s main outside industrial impact will be through enabling shorter time-to-market and reduced cost for successful circuit realisation in several key application sectors with major growth potential in the microwave, RF and mm-wave area, especially those related to Si- and GaAs-based components for wireless communications. Objectives Demonstration of effective, working, user-friendly links between existing different European CAD tools, to be exploited commercially as new product enhancements. The project will allow users to complement their existing investments in CAD products from US vendors (in particular from HP-EEsof) with a set of easy-to-use extensions and links to European CAD tools/models offering added user value. Major enhancements to existing CAD interface formats will be demonstrated through the provision of direct access to MMIC foundry library modules. Furthermore, the consortium intend to work towards a common European style of user interface. New analysis techniques will be provided for MMICs which are complex, multi-function and operating in strongly non-linear and/or low-power regimes. An advanced, standardised, non-linear FET model will be delivered for at least two of the foundry processes represented in the consortium, using a synthesis of the best available research ideas, including a unified, physics-constrained model. Participants UCD (IRL); BML (UK); DASSAULT ELECTRONIQUE (F); GAASCODE (UK); GMMT (UK); JANSEN MICROWAVE GMBH (D); PML (F); UNIV. OF ROME II (I). Contact Point Thomas J. BRAZIL Department of Electronic Engineering University College Dublin DUBLIN 4 (Ireland) Duration 24 months from 15.03.96 tel: +353 1 706 1929 fax: +353 1 283 0921 E-mail: tom.brazil@ucd.ie 1 - 23 1. Application Competences and Design TCS 98 EP 21625 FIPSOC Field Programmable System on Chip Summary The aim is to develop the first member of a family of Field Programmable System-On-aChip (FIPSOC) devices. These circuits will integrate combinational logic blocks, programmable analogue cells for signal conditioning and data acquisition, and an on-board microprocessor. Configuration and control data will be stored in on-chip RAM memory. The on-board 8051 based microprocessor will be able to access both the configuration and the actual signals within the logic cells, providing a strong interaction between hardware and software. Standard, off-the-shelf FIPSOC devices will be configurable to a wide variety of tasks including analogue and digital data acquisition and processing as typically required by the electronic instrumentation and industrial process control sectors. Users can develop their own applications by implementing (programming) both hardware and software functions in the same device. The chip will be ideally suited as an easy-to-use system prototyping workbench as well as in low to medium volume product applications. Objectives To develop a set of programmable analogue cells and routing resources. Cells will include analogue interfaces, DACs and ADC, amplifiers, filters. This function library will include a bridge to commercial standard-cell libraries to enable migration from programmed FIPSOC prototypes to classical ASIC solutions in case of large production volumes. The project will develop the first member of the FIPSOC family in a 0.5 micron CMOS process. It will integrate analogue functionality, ~5k programmable digital gates, an 8051 based microprocessor core, and programme/control memory. The project will develop a software toolkit to enable programming of both digital and analogue functionality as well as data processing and control functions undertaken by the on-board microprocessor. The toolkit will be PC based and include schematic capture, routing and chip interface capture and design functions. In order to demonstrate versatility, level of system integration and performance, the partners will use FIPSOC-1 in a number of industrial demonstrators including a coin recogniser for vending machines and a smart battery charger. Participants SIDSA (E); MIKRON GMBH (D); WARWICK MICROSYSTEMS (UK); JOFEMAR (E); UNIVERSITAT POLITECNICA DE CATALUÑA (E); AICIA (E) Contact Point Dr. José Maria INSENSER SIDSA Parque Tecnológico de Madrid, c/ Isaac Newton 1 28760 Tres Cantos, Madrid (Spain) Duration 36 months from 01.01.96 tel: +34 1 803 5052 fax: +34 1 803 9557 E-mail: jmi@sidsa.es 1 - 24 1. Application Competences and Design TCS 98 EP 21812 AMADEUS Analogue modelling and design using a symbolic environment Summary An interactive circuit design environment will be provided combining advanced symbolic, numerical and graphical techniques that allow the modelling, characterisation and design of analogue circuits. Symbolic techniques will further be explored in tolerance analysis and design centering. The environment will be developed for exploitation as a commercial CAD tool. An AMADEUS interest group will be established to involve potential external users in definition of requirements and assessment of results. Objectives Available algorithms for the symbolic analysis of linear circuits will be made more robust, gaps will be closed and the application range will be widened. A first product release for linear circuit analysis is planned at the project midterm. Non-linear problems like DC large-signal behaviour as well as modelling approaches will be tackled in the second half of the project. Furthermore, methods of application will be developed, and application to product design will be demonstrated. Commercial figures will be provided to show benefit and returnon-investment to users. Participants ROBERT BOSCH GMBH (D); SGS-THOMSON MICROELECTRONICS (F); ANACAD EES (D); CNM SEVILLA (E); KU LEUVEN (B). Contact Point Claus BAUMGARTNER Robert Bosch GmbH P.O. Box 1342 D-72703 Reutlingen (Germany) Duration 48 months from 01.03.96 tel: +49 7121 35 1734 fax: +49 7121 35 2687 E-mail: Claus.Baumgartner@rt.bosch.de 1 - 25 1. Application Competences and Design TCS 98 EP 22797 SEED Supplier Evaluation and Exploitation of DELPHI Summary The thermal precision needed to design out the functional and reliability failures that can result from component overheating requires accurate, validated thermal models of the critical electronic parts used in the design. The DELPHI project (ESPRIT 9197) has therefore developed a technology for the characterisation of the thermal behaviour of single chip packages. In the SEED project three electronic component manufacturers (Philips Semiconductors, Siemens and SGS Thomson) will evaluate this technology. The results will be disseminated on a wider scale, and steps will be initiated for the industrial adoption of the new methodology. The co-ordinating partner Flomerics is an SME tool vendor that develops and markets software (FLOTHERM) for thermal analysis at package-, board- and system-level. Objectives Mathematical Reduction techniques will be evaluated, i.e. methods for generating ‘compact’ thermal resistor networks by mathematical reduction of a ‘detailed’ finiteelement or finite-volume thermal model of the part. The ‘detailed’ thermal models are itself experimentally validated by the following methods for measuring the junction temperature of a chip package under well-defined boundary conditions: - Double Cold Plate Method - a measuring system where the part is clamped between two temperature-controlled cold plates. - Submerged Double Jet Impingement Method - a measuring system where the part is immersed in a fluid and subjected, on both sides, to impinging fluid jet streams. The ultimate beneficiaries of SEED are the equipment manufacturers, who can build more reliable electronic equipment if the component manufacturers supply validated thermal models of their parts. Participants FLOMERICS LIMITED (UK); PHILIPS SEMICONDUCTOR (NL); SGS-THOMSON (I); SIEMENS SEMICONDUCTOR (D); ALCATEL BELL (B); THOMSON-CSF RCM (F). Contact Point John PARRY Flomerics Limited 81 Bridge Road Hampton Court, KT8 9HH (United Kingdom) Duration 36 months from 01.03.97 tel: +44 181 941 8810 fax: +44 181 941 8730 E-mail: john@flomerics.co.uk 1 - 26 1. Application Competences and Design TCS 98 EP 23643 ESDEM ESD Protection Design Methodology Summary A design methodology will be developed that employs device and circuit simulators to devise and to optimize integrated circuit ESD protection structures. The design methodology for production will change from the current largely-empirical approach, based on extensive destructive testing, to TCAD-guided critical parameter evaluation, validated by a relatively small number of specific high current measurements. Objectives To gain insight in ESD-problems and to investigate possible design options for a wellestablished smart power technology, as well as design and processing options for an advanced VSLI technology with the aim of a robust ESD performance; To investigate and optimize the behaviour of protection devices under different ESD stress models, including Human-Body Model and Charged Device Model, To provide basic physical models that are still lacking and that are relevant for ESDmodelling, To develop respective TCAD code and make it commercially available. Participants R. BOSCH GMBH (D); SGS-THOMSON MICROELECTRONICS (I); IMEC (B); UNIVERSITY BOLOGNA (I); ISE AG, (CH); FEDERAL INSTITUTE OF TECHNOLOGY ZURICH (CH). Contact Point Wolfgang WILKENING Robert Bosch GmbH P.O. Box 1342 D-72703 Reutlingen, (Germany) OF Duration 24 months from 01.01.97 tel: +49 7121 35-1533 fax: +49 7121 35-2687 E-mail: Wolfgang.Wilkening@rt.bosch.de 1 - 27 1. Application Competences and Design TCS 98 Enhancement of Technology and Manufacturing Base EP 20485 TIBIA II Technology Initiative in BICMOS for Applications Summary The objective of this project is to satisfy the systems needs of the electronic equipment markets for Bipolar and BICMOS ICs. This will be achieved by developing and establishing BICMOS and Bipolar technologies at the 0.5 micron generation together with the design and CAD expertise to exploit these bipolar technologies. This project will be focused on three subprojects: demonstrators, process assembly and process support. Objectives Initial release of 0.5 micron BICMOS processes (4Q1996). Verified and updated design rules. Model parameters available for simulations of the designs. List of available options in the process: resistors, capacitors, etc. Minimum and maximum range of typically achieved parameters describing the electrical behaviour of the transistors. Key library cells available. Results (status December 1996) Demonstrator IC’s have been successfully produced in 0.5 micron BICMOS processes Results are according to expectations mentioned in the project plan for TIBIA II. All partners reached the milestone : Initial release for design Co-operation has been especially successful on the emitter-base module Participants PHILIPS SC (NL); SIEMENS (D); SGS THOMSON (F); GEC PLESSEY (E); MATRA-MHS (F); ALCATEL MIETEC (B); PHILIPS CE (NL); SEMICONDUCTORES (E); EZM VILLACH (A); ATHENS UNIV. (GR); EPFL (CH); TELEFONICA (E); ALCATEL SEL (D); PAVIA UNIV. (I); IMEC (B). Contact Point Fokke POSTMA Philips Semiconductors Gerstweg 2 6534 AE Nijmegen (The Netherlands) Duration 15 months from 01.10.95 tel: +31 24 3533351 fax: +31 24 3533602 E-mail: fokke.postma@nym.sc.philips.com 2-1 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 20763 SHAPE Sub HAlf micron cmos Process for European users Summary SHAPE is concerned with development of the next generation of 0.35 micron CMOS logic technology. The new technology will be demonstrated by processing innovative VLSI circuits designed in cooperation with major European end-users. The project contains a first phase aiming at implementation and characterisation of process steps, followed by integration of a full CMOS process, targeting the most advanced performances needed by the semiconductor market. At a very early stage, design rules and processing capabilities will be offered to selected users in order to allow advanced system developments in Europe. The developments provide the opportunity for a close and focused cooperation among European semiconductor companies, electronic equipment manufacturers and research institutes to establish in Europe, within a competitive time frame, an early sub-half-micron processing and design capability. Objectives Availability of prototype processing capability in industrial pilot lines by 1996 of a true 0.35 micron CMOS, 3-4 metal, 3.3V process based on the next generation of lithographic tools offering process capability for complex products requiring high density of integration (10K gates/mm2) and high performances (> 0.5 mA/micron for NMOS and > 0.25 mA/micron for PMOS) with reduced power consumption. Process specifications and target design rules will be agreed with major end-users with reference to key applications. The 0.35 micron base process will be designed to provide also the base-line for further process developments such as analogue addressing specific markets and for an extension later to BICMOS. Participants SGS-THOMSON (F), PHILIPS SC (NL), SIEMENS SC (D), ALCATEL-MIETEC (B), GEC-PLESSEY (UK), MATRA-MHS (F), AMS (A), BULL (F), MATRA-COMMUNICATION (F), ALCATEL-BELL (B). Contact Point M. MONTIER SGS - Thomson Microelectronics Rue Jean Monnet BP16 38921 Crolles, (France) Duration 16 months from 01.09.95 tel: +33 76926327 fax: +33 76926444 E-mail: michel.montier@st.com 2-2 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 21752 ADEQUAT+ Advanced developments for CMOS for 0.25 micron and below Summary The priorities of the European semiconductor industry will be supported through the assessment of key options for advanced CMOS process modules. The project is in phase with the most advanced world-wide efforts currently addressing 0.18 m device architectures and defining 0.25 m interconnect schemes. Target device specifications and lay-out rules for these technological modules have been defined in close interaction with industrial representatives. The results will be assessed and later exploited by the industrial partners in order to reduce their development costs (maximising the utilisation and minimising the risk). The 0.25 m CMOS front-end process modules developed in ADEQUAT-2 (EP 8002) have been modified for low-voltage applications. Progress and results • Back-end processing steps and modules for 0.25 m CMOS were developed by 4Q96. • The implications of using a low supply voltage (0.9 -1.2 V) for 0.25 m CMOS have been assessed through the fabrication of specific test circuits and measurement data will be available by 1Q97. • Based upon the work of the NOVA-project (E 9159) concepts for 0.18 m CMOS frontend modules are investigated through the fabrication and testing of NMOST and PMOST devices. A lateral isolation module for 0.18 m CMOS will be developed by 1Q97. • Various techniques were tested for the extension of 248 nm DUV lithography and the feasibility of 0.18 m CMOS front-end patterning has been demonstrated. • Insight has been provided in the key process parameters affecting device performance and reliability. Benchmarking with respect to competitive results obtained world-wide has been performed. Participants IMEC (B); DIMES (NL); FHG (D); GPS (UK); GRESSI (F); PHILIPS (NL); SGS THOMSON (F); SIEMENS (D); CNRS-UNIV.NANTES (F); GCIS-LAAS (F); NCSR DEMOKRITOS (GR); NMRC (IRL); SGS THOMSON (I); TU VIENNA (A); UNIV. BOLOGNA (I); UNIV. WARWICK (UK); UNIV.YORK (UK). Contact Point Roger DE KEERSMAECKER IMEC vzw Kapeldreef 75 3001 LEUVEN (Belgium) Duration 15 months from 01.12.95 tel: +32 16 281326 fax: +32 16 281576 E-mail: rdk@imec.be 2-3 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 23806 ULTRA ULsi mosT Research Activity (ULTRA) Summary This project is an exploratory work on advanced MOSFET architectures suitable for the 0.13 micron CMOS generation. Technically speaking, this project focuses on the optimisation of the device architecture (e.g. Ground Plane), the emerging new materials (e.g. SiGe, TiN, Ta2O5, etc.) and the evaluation of various technological solutions against the end-user defined specifications. The project is divided into four workpackages: Channel Engineering, Gate Engineering, S/D Engineering and Device Specifications. Objectives to perform exploratory work on new device architectures suitable for the 0.13 micron CMOS generation to consider the introduction of new materials in a standard CMOS process flow to compare the various technological solutions against the target specifications Participants SGS-THOMSON MICROELECTRONICS (F), SIEMENS (D), PHILIPS (NL), IMEC (B) GRESSI (F) Contact Point Dr. Constantin PAPADAS Central R&D Technology SGS-Thomson Microelectronics 850 rue Jean Monnet BP 16 38921 Crolles Cedex (France) Duration 24 months from 01.01.1997 tel: +33 47676 4481 (also voice mail) fax: +33 47676 4299 e-mail: papadas@cns.cnet.fr 2-4 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 24115 ACE Advanced CMOS for Europe Summary ACE aims at developing Front-end and Back-end process steps and modules for 0.18µm CMOS logic. The workplan is strongly application-driven addressing two generic market segments : high performance and low power applications. The first results of a process validation module for device modules will be available at the end of 97. This will allow processing of first 0.18µm silicon in 1998. First results for the interconnects test structures will be available by 3Q98. The timing of project is in line both with the most advanced world-wide competition (well ahead of the 1994 SIA roadmap) and with the advanced European industrial roadmaps. The concurrent development of Front-end and Back-end modules for the same generation will allow the assessment and optimization of the impact of Back-end process steps on device characteristics and the fabrication of relevant test circuits with critical dimensions of 0.18µm. The project relies on inputs from the feasibility studes and early development work done within the ADEQUAT+ project on lithography and device architectures for 0.18µm CMOS. It will establish links with downstream projects on process development and with upstream innovative projects on lithography (such as ELLIPSE) and other advanced projects on process and device architectures (such as ULTRA for Front-end and DAMASCENE for interconnects). Objectives To develop the patterning techniques (lithograhy and etching) required for fabrication of 0.18µm CMOS devices and based on 248 nm optical lithography To fabricate high performance 0.18µm CMOS devices To develop process steps and modules for multilevel metallisation architectures of up to 5 to 6 levels of metal for 0.18µm CMOS technologies To validate appropriate developed modules by industrial partners Participants IMEC (B); DIMES (NL); FhG ISiT/IIS-B (D); GPS (UK); GRESSI (F); PHILIPS (NL); SIEMENS (D); SGS-THOMSON (F); NMRC (IRL) Contact Point H.E. MAES IMEC Kapeldreef 75 B-3001 Leuven (Belgium) Duration 21 months from 01.03.97 Tel: +32-16-281283 Fax: +32-16-281501 e-mail : maesh@imec.be 2-5 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 25220 DAMASCENE DAMASCENE ARCHITECTURE FOR MULTILEVEL INTERCONNECTIONS Summary Circuit performance is becoming dramatically limited by the interconnection. The resulting demand on interconnect technology requires the exploitation of all development possibilities: materials, basic processes, interconnect architecture and design. Driven and lead by industry, this project proposes, in a top-down approach from product needs to technology choices, investigation of advanced alternative materials and architecture for interconnection in subquarter-micron technology. The objective is to achieve significant improvement on interconnection reliability and cost, high signal propagation speed, low power consumption and crosstalk between the nearest interconnection lines. Innovative solutions for interconnection will be carried out by simultaneous consideration of: DAMASCENE architecture in order to achieve simpler interconnect fabrication, better yield and higher density of integration, Low resistivity COPPER for metallisation with improvement in electromigration and stressmigration, Low permittivity polymers as dielectrics. Objectives The final project target is to bring the European expertise up to international level in: Manufacturable deposition and patterning for Cu and Al lines and vias in Damascene architecture: Choice of architecture, Al and Cu deposition process (PVD, CVD, electroplating and electroless), Al and Cu Chemical Mechanical Polishing (C.M.P.). Manufacturable deposition and patterning processes for advanced dielectric, materials in Damascene architecture: Integration of silicon-based low k dielectrics, Studies of carbon-based polymer dielectrics. Integration feasability for these materials and processes in vias and lines Damascene interconnect structures. Participants SGS-THOMSON MICROELECTRONICS (F); SIEMENS (B); PHILIPS (NL); IMEC (B); GRESSI (F); TU-C (B); NMRC (IRL). Contact Point Mr Pierre BICHON SGS-THOMSON MICROELECTRONICS Central R&D – Joint Program ST/GRESSI CEA/DTA-LETI – CEA/Grenoble – 17, rue des Martyrs F -38054 GRENOBLE CEDEX 9 (France) Duration 18 months from 09.09.97 Tel: 33.(0)4.76.58.55.56 Fax: 33.(0)4.76.88.50.54 Email: pbichon@sorbier.cea.fr or p.bichon@st.com 2-6 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 21760 ELLIPSE Excimer Laser Lithography Project for Sub-Quarter Micron Era Summary The project links leading European materials and equipment suppliers and research institutes in the area of advanced lithography, being the first phase of a combined European effort to provide 193 nm lithography tools and resists for the Gigabit DRAM technology generations, i.e. for 0.18 and 0.12 micron feature sizes. The two main workpackages will focus on production exposure tool design and predevelopment and on a litho cell for 193 nm process development. The ultimate goal is to make available a European optical exposure tool and resist processes compatible with 0.18/0.12 micron manufacturing requirements by the year 2000. Objectives Provision of concepts for a 193 nm lithography tool. Development of a 193 nm excimer laser. Selection of optical materials for use in and predevelopment of a 193 nm projection system. Definition of user requirements for a production exposure tool. Resists predevelopment and evaluation. Participants GRESSI (F); ASML (NL); CARL ZEISS (D); EXITECH (UK); HEREAUS (D); IMEC (B); KORTH (D); LAMBDA PHYSIK (D); OCG (CH); RAL (UK). Contact Point Jean-Marc TEMERSON GRESSI rue des Martyrs 17 F-38054 Grenoble (France) Duration 18 months from 01.02.96 tel: +33 76 764240 fax: +33 76 903443 E-mail: temerson@cns.cnet.fr 2-7 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 20492 SUMMIT Silicon substrate multi-chip modules for innovative products Summary A cost-efficient, commercial manufacturing base is to be established in silicon-based multichip modules (MCMs) with active substrates and ball grid array interconnects. The new feature of this technology is the integration of passive and active components in the substrate which would otherwise be connected to an MCM via wirebonding. The first level connection of the standard ICs to the substrate is done using a flip chip interconnect. Development of a commercial source for wafer rerouting to facilitate flip chip interconnects also constitutes a major project goal. Objectives Industrial production procedures for the manufacture of marketable products are to be developed from the basic technology. Special substrates and MCMs will be produced to evaluate the parameters of this technology. Cost optimisation of both the MCM architecture and the MCM manufacturing process will be performed throughout. Cell libraries for both active and passive components to be used in the design of substrates will be made available. Various built in test structures are to be designed and integrated on to silicon substrates. In this way the testability of MCMs can be improved by the use of active substrates. A set of analogue and digital simulation cells is to be designed and made available for simulation of the substrate system before production. Operative MCMs demonstrating the tools and technologies developed are to be produced. These will undergo a full characterisation to ensure that they comply with the requirements of specific applications in terms of reliability and quality. Participants DICRYL SA (E); CNM (E); DASSAULT ELECTRONIQUE (F); SIBET GMBH (D); NMRC (IRL); ETH ZÜRICH (CH); D+T (E) IN2P3 (F). Contact Point CARLOS LÓPEZ REQUEIJO Dicryl SA Parque Technológico de Boecillo Boecillo 47151 VALLADOLID (España) Duration 36 months from 01.12.95 tel: +34 83 548086 fax: +34 83 548012 E-mail: 100530.1074@compuserve.com 2-8 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 20797 GOOD-DIE Get Organised Our Dissemination of Die Information in Europe Summary For large scale MCM manufacture with high assembly yields, an infrastructure is required for KGD sourcing as well as a means for the design and simulation of MCMs before committing them to hardware. This project will create an international electronic database with all the necessary components of bare die. An on-line database will be generated for the location of bare die of all types to carry out the initial selection for components for MCM or hybrid design. A second part of the database will be for design of MCMs or hybrids by downloading electronically the footprints, signal identities, wire bond positions etc. to CAD design workstations for the physical layout of MCMs. Also to be downloaded, if appropriate, will be the device simulation models such as IBIS, VHDL, BHDL, SPICE etc. the database will include all assembly technologies such as wire bond, TAB, flip-chip and chip size package (CSP), if available. Levels of Goodness will be identified from wafer probed to fully burnt-in KGD. (See also EP 20796 GOOD-DIE NETWORK.) Objectives To generate an electronic selection database for the sourcing of KGD. To generate an electronic design database for the design of MCMs using KGD by downloading data of die footprints, test data etc. to CAD MCM design and layout workstations. This will include an assessment of the standards and norms regarding KGDs in Europe and the RoW. A definition of the requirements of a database for KGD through assessing standards, manufacturer and user requirements for KGD. A database for the selection of KGD for MCM design. A detailed KGD database for the design, manufacture and test of MCMs. Participants CODUS (UK), IMEC (B), PHILIPS (CH), ELTEK (UK), ROOD TECHNOLOGY (NL), GPS (UK), MATRA MHS (F), TEMIC (D), ALCATEL-MIETEC (B), SIEMENS (D) Contact Point Mike G. ROUGHTON CODUS 142 Colebrook Road Sharley Solihull B90 1BX (United Kingdom) Duration 30 months from 01.11.95 tel: +44 121 693 3116 fax: +44 121 693 3116 E-mail: mroughton@fdgroup.co.uk 2-9 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 23218 ABEL Automated Back-End European Line Summary The current state of the art for silicon packaging is to use automatic stand alone machines for each process step. Driven by a better customer service and manufacturing optimisation, a partial integration of a few processes steps is proposed by some back-end equipment and manufacturers. The goal of ABEL is to achieve a complete automated and CAM controlled back-end line (Die and wire bounders, moulding, dambar cutting and laser marking systems, trim and form machine). Objectives To develop the hardware interfaces and software tools which are needed for integration of a fully automatic back-end line, with a particular emphasis on scheduling, flexibility, traceability, SPC, equipment data logging. To improve the stand alone equipment reliability (up-time) and calibration tools to the level necessary for a successful line integration. The processes and materials will be developed to meet the short cycle time of the automated line concept. To develop tools for process control and auto-correction of critical process parameters. Partners SGS-THOMSON SA (F); SGS-THOMSON SRL (I); FICO (NL); ESEC SA (CH); SGSTHOMSON LTD (M) Contact point Juan EXPOSITO SGS-THOMSON Microelectronics 38019 Grenoble Cedex (France) Duration 36 months from 01/11/96 tel: +33-47658791 fax: +33-476585529 E-mail: juan.exposito@st.com 2 - 10 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 23261 FLINT Fine Line Interconnect Summary The principle objective of the project is to provide advanced laminate substrate technologies for use in the rapidly emerging market for high-density electronic products such as lap-top computers, portable phones, as well as MCM-L (multi-chip-module-laminate) for desktop products. These new substrate technologies utilise new hole formation approaches such as laser drilling, plasma etching, photo formation, and are vital for a cost-effective and highdensity solution necessary for further miniaturisation. By designing, building and testing functional demonstrators, enhanced packaging technologies for manufacture and assembly are to be developed in the field of advanced printed circuit boards and laminated organic MCMs. The demonstrators are designed to serve as electronic building blocks in real products in communications applications. Furthermore, the technology is considered to be suitable for the design of subsystems in the market segments of consumer products, automotive and other industrial applications. Objectives Advanced PCB and MCM-L technology comprising circuitry with fine tracks and gaps in high volume manufacturing at competitive prices; Reduced track widths down to 50µm; Micro-vias utilising laser, plasma and photolithography with diameters down to 50µm; Assembly techniques on PCB and MCM-L carriers for flip-chip, wirebond and mixed SMT; Integrated resistors and capacitors; cost modelling and technology roadmaps based on assessing application requirements for future products; Functional demonstrators based on applications for communications. Participants STP (D), SOLECTRON (F), GEC-MARCONI (UK), INTRACOM (GR), NMRC (IRL), BPA(UK) Contact Point Dr. Peter FINK, STP Elektronische Systeme GmbH P.O.Box 560, D-71047 Sindelfingen, (Germany) Duration 36 months from 01.10.96 Tel: +49 7031 612 3877 Fax: +49 7031 612 2122 E-mail: 101356.1712@compuserve.com 2 - 11 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 23769 CUMULUS Development of a generic, low cost MCM-L technology for use in portable consumer, automotive and industrial applications Summary The Multi-Chip Module (MCM) technology will be made more attractive for use in communications, automotive, industrial and consumer electronics applications. This will be realised by the development of a highly miniaturised and low overall cost MCM technology. It comprises innovative and low cost production processes at all levelscomponents, first level interconnect, substrates, second level interconnect- of the MCM architecture. The goals can be achieved through: Objectives Components: Usage of flip chip with pitch down to 150 m or with redistributed pitch down to 250 m as well as Chip Scale or Chip Size Packages (CSP), peripheral pitch down to 200 m or grid array pitch down to 300 m. First level interconnect: Mounting onto filled and tented vias. Reflow soldering for fine pitch flip chip, combined with underfill. Flip chip and SMD on flexible substrates combined using adhesive technology. Substrates: Fine line multilayer substrates with lines and spacing down to 50 µm, both in rigid and flex form with via in pad technology realised by photo imaging or laser drilling. Second level interconnect: Interconnect to the outer world, through a moulded injection device ( MID). Participants PHILIPS CFT (NL); COMBITECH ELECTRONICS (S); IMEC (B); IVF (S); SIEMENS (D); TU BERLIN (D); CICOREL (CH); STP (D); SHELLCASE (ISR). Contact Point Co VAN VEEN Philips CFT-SAQ p246 P.O. Box 218 5600 MD Eindhoven (The Netherlands) Duration 36 months from 01.01.97 Tel: +31-40-2733364 Fax: +31-40-2859229 E-mail: veen_nja@nlcftccmail.cft.philips.nl 2 - 12 2. Enhancement of Technology and Manufacturing Base TCS 98 ESPRIT 23910 INTEGRATION OF MAGNETICS AND PASSIVE COMPONENTS Summary The project is oriented towards the development of high power integration, low voltage and low cost miniaturised DC/DC power converter modules for Telecom applications. The main objective is to achieve an integrated converter by the innovative use of multilayer technology and suitable electrical conversion topology. New multilayer technology permits the integration of most of the passive components, tracks and interconnections, of low voltage (3,3 V output) and low power ( 10 W ) DC/DC converter. Objectives High efficiency (more than 83% ) DC/DC converter modules by using integrated passive components to give both reduced surface area and small volume: 20x20x4mm To develop cost effective processes and technologies in order to integrate the passive components (Magnetics, capacitors and resistors) used in low power DC/DC converters. Develop advanced topologies to maximise energy conversion performance in DC/DC converters. Produce a design and develop the structure for a DC/DC converter module demonstrator of high reliability with improved volumetric efficiency. SMD devices Resistors Capacitors Magnetics DC/DC converter module view with IMPASS technology Participants ALCATEL (E); AVX (UK); UNIVERSIDAD DE OVIEDO (E) Contact Point Carlos QUIÑONES Alcatel Alsthom Corporate Research Center Ramirez de Prado,5 Madrid 28045-SPAIN Duration 24 months from 01.03.97 Tel: +34 1 330 4953 Fax: +34 1 330 5060 E-mail: quinones@alcatel.es 2 - 13 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 24363 HIPERPRINT High Performance Printed Boards and Subassemblies for Telelcom and Rf Applications Hiperprint Summary In Hiperprint a cost-effective modular, high volume, high frequency technology for printed subassemblies will be developed. The core of the technology is oriented towards advanced digital circuits operating at frequencies up to 622 Mbits/sec. The technology to be developed uses the latest improvements in cost-effective flip chip, µBGA and multilayer fine line technology. Assembly will cope with silicon ICs, GaAs MMICs and mixed assemblies (cfr. SMT components). The technology will be validated by means of high volume digital telecom circuits and high-end RF demonstrators. The project results will be made available to other users through the exploitation plans of the consortium partners. Objectives advanced high density multilayer board technology: 2 layer fan-out capability > 500 I/O with 0.2 mm array component path, 50 µm line width and spacing including microvias, integrated resistors and capacitors. reworkable low cost assembly technology for flip chip and µBGA, using high melting metal bumps or elevated solderpads on the board side for flip chip and µBGA. development of a digital telecom demonstrator for high volume telecom access circuits (frequency range up to 3GHz) development of a RF analogue demonstrator operating in the frequency range 12,75-14,5 GHz. further improvement of design tools and characterisation methods for process modelling, electrical modelling, thermomechanical modelling and devolpment of physical models and libraries tools for fine line printed circuit boards. Participants DESIGN TO DISTRIBUTION (UK), ALCATEL BELL (B), SOLECTRON (UK), ALCATEL ESPACE (F), ALCATEL MIETEC (B), IMEC (B) Contact Point Brian SMITH D2D West Avenue, Kidsgrove Stoke on Trent, Staffs ST7 1TL 5 (United Kingdom) Duration 36 months tel: +44 1782 771000 fax: +44 1782 787259 2 - 14 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 24366 BATEL Ball grid array technologies for advanced telecom applications Summary In the BATEL project plastic ball grid array (BGA) packages, which are currently the best choice with respect to high pincount, high density, high performance and SMT capabilities, will be developed to meet a number of stringent telecom application requirements, such as the need for thinner packages with high pincounts and reduced grid pitches. Medium ballcount (± 200 balls) thin BGA’s with a grid pitch down to 0.5 mm and a reduced profile down to 1.4 mm total thickness with chip scale potential will be developed. The developed BGA packages will be validated by means of an advanced GSM telecom demonstrator, processed in 0.35 µm CMOS. Objectives To develop a thin chip scale BGA package of medium ball count, with a grid pitch of 0.5 mm and a thickness of 1.4 mm To fully characterise the developed BGA packages and make them available for reliability assessment, surface mounting on PCB and product validation. To develop suitable systems for the handling and inspection of thin BGA packages. To develop specific printed circuit board assembly techniques for the developed high density array packages. To perform a thorough evaluation of the related plastic packaging enhanced reliability problems through advanced test vehicles and characterisation methods. To qualify the developed thin chip scale BGA packages by product validation techniques using a selected telecom demonstrator circuit. To monitor the cost-effectiveness of the developed BGA packages. To issue guidelines for exploitation of the developed BGA packages in typical telecom system applications. Participants ALCATEL MIETEC (B); SGS-THOMSON MICROELECTRONICS (F); ALCATEL MOBILE PHONES (F); SCI FRANCE (F); ALCATEL BELL (B); NMRC (IRL); SGS-THOMSON MICROELECTRONICS (I); MULTITEST (D); ICOS (B). Contact Point Dr Gust SCHOLS Alcatel Mietec Westerring 15 B-9700 Oudenaarde (Belgium) Duration 36 months from 01.01.97 Tel: +32-55-332342 Fax: +32-55-332647 E-mail: gu_schols@mietec.be 2 - 15 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 26245 ESCHETA European Sources of Chip Scale Packages for Harsh Environment, Telecom & Automotive Summary The project targets the development, qualification and industrialisation of different European Chip Scale Package (CSP) sources with respect to their applicability in various environmental conditions such as telecom and automotive (Harsh Environment). Three distinct approaches of chip scale package type constructions based on wafer level, flexible tape and rigid carrier redistribution will be followed, capable to meet ball pitches from 1.0 mm down to 0.5 mm depending on the application’s needs. The developed packages will be characterised by simulation and fully qualified under conditions required for telecom and automotive applications. In addition to single chip package long-term reliability, industrialisation processes such as solder joint reliability, surface mount assembly compatibility, PCB layout & design rules, repair & rework are addressed. In parallel, the developed European CSP approaches will be benchmarked, in the same application contexts, against commercially available CSP packages. The applicability and industrialisation of the CSPs will be validated by means of two demonstrators covering the automotive volume market for harsh environment and complex telecom systems with high power requirements. Objectives to develop and establish various CSPs which will be provided by European sources. to qualify the CSPs for usage under telecom and automotive conditions. to validate the feasibility and manufacturability in a standard SMT process by setting up fully functional demonstrators for automotive and telecom switching (high power) application. Participants ALCATEL SEL (D), BULL (F), MATRA BAE (F), SIEMENS-HL (D), SIEMENS-AT (F), TU BERLIN (D), EM MICROELECTRONIC MARIN (CH), PACTECH (D) Contact Point Dr.Thomas Solleder Alcatel SEL AG Lorenzstr. 10 , D-70435 Stuttgart, Germany Tel: +49 711 821 44812 Fax: +49 711 821 45551 E-mail: t.solleder@alcatel.de Duration 36 months from 01.02.98 2 - 16 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 26261 LAP Low cost Large Area Panel Processing of MCM-D substrates and packages Summary The main LAP objective is the development and demonstration of low cost high-density substrate manufacturing technology for first level die assemblies. The cost target for high volume production of this high density interconnect substrates is as low as 1 US$/in² and shall be obtained by increasing panel size of today to panel areas up to 24 x 24 in² - the maximum practical panel size of today. While this largest thinkable panel size will probably remain an object of studies and experiments, 8 in , 12 x 12 in², and 16 x 16 in² are candidates for HDI production in the year 2000. The substrate technologies developed will allow for a wide range of packaging options from inserted substrates into transfer-molded packages to integrated MCM-L/D and MCM-M/D (M=metal) area array packages. The suitability of the LAP technology will be demonstrated with three products from the communication, instrumentation and telecommunication sectors. Objectives High density / low cost substrate technology (capable for interconnecting 1000 I/O /in² by use of standard 1st level assembly processes) with a production cost target of 1US$ / in². Development of a high performance MCM-D technology with 50 µm line pitch and 50 µm via/land to be verified by prototyping (cost will definitely be higher than 1US$/in²). Verification of the technical target by prototyping on a LAP pilot line and verification of the cost target by appropriate cost modelling for a high volume production facility. Qualification of the LAP technologies for semiconductor assembly into QFP and BGA. Compatibility of the LAP technologies of the three manufacturers within a specified range of design rules and qualification requirements (to be specified during the project). Verification of the LAP technologies developed by three product demonstrators. Participants SIEMENS (D), CAEN (I), HIRSCHMANN (D), STRAND (S), THOMSON (F), ETH (CH), IMC (S), NMRC (IRL) Cooperative link with FLIPAC Consortium Contact point Dr. Peter Demmer Siemens AG, ZT ME 6 Otto-Hahn Ring 6, D-81739 München Duration 30 months from 01.01.98 Tel: +49 89 636 45554 Fax: +49 89 636 48555 E-mail: peter.demmer@mchp.siemens.de 2 - 17 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 26280 FLIPAC Fine Line Interconnection and Packaging Summary As advances in semiconductor technology create larger devices with more contacts, greater functionality, higher speed and greater power dissipation, appropriate packaging is essential for proper application in electronic systems. The FLIPAC project aims at developing higher density interconnections and packaging solutions in order to build printed circuit boards and MCM-L/D substrates to address the needs of advanced data processing and telecom applications. An increased level of integration will be reached through the assembly of large bare die using flip-chip, TAB, wire bonding and CSP technologies. Potential applications include also robotics and automation, transport (land, sea and air), medical electronics and consumer products. Within the project, build-up printed circuit boards using enhanced processes and materials, will be developed and compared. Functional MCM-L/D demonstrators for Data Processing and Telecommunication industry solutions will be designed, built and tested. Industrial capability and cost are also addressed. Objectives capability to build advanced organic substrates for the interconnection of large size bare dies (flip-chip, wire-bonding, TAB) and area components (BGA, CSP) ; enhancement of thermomechanical properties and reliability of MCM-L substrates by the use of new organic core material ; extension of results to a new cost effective high density printed circuit board technology on large substrate size (large area processing) ; cost reduction of printed circuit boards by reduction of the number of layers ; definition of design rules ; capability to build advanced modules for Data Processing and Telecommunication industries ; achievement of a cost / performance ratio competing with existing multilayer PCB technologies, as well as with existing MCM-C and MCM-D solutions ; Participants BULL (F), BULL (I), CIMULEC (F), DICRYL (E), IMC (S), IMEC (B), ITALTEL (I), LINLAM (NL), TU BERLIN (D) Cooperative link with LAP consortium Contact Point Dr KAREL KURZWEIL, Bull SA Rue Jean Jaurès 68 78340 Les Clayes Sous Bois (France) Duration 30 months from 01.01.98 Tel: +33 1 30807048 Fax: +33 1 30807833 E-mail: K.Kurzweil@frcl.bull.fr 2 - 18 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 21315 GAMMA Gallium Arsenide Materials for Microwave Applications Summary GaAs technology for both discrete and IC components has proved to be indispensable for advanced telecommunication and automotive systems. The use of GaAs clearly starts where the silicon ends i.e. in meeting system requirements such as the RF front-end of mobile communication equipment, broadband radio links and anti-collision systems. The main interest of this project is to develop and qualify semi-insulating bulk GaAs and epitaxial material for three major microwave applications: MESFETs, pseudomorphic HEMTs and GaInP-HBTs; and to establish competitive European production facilities in those domains. Objectives Establishing a reliable European source for 4" semi-insulating GaAs substrate fabrication, optimised for ion implantation applications. Comparison of 3" and 4" state-of-the-art world market material. Epi-ready wafers directly usable for an MBE process. Attention will be paid to the requirements on geometry and surface conditions. Production and qualification of high performance 4" MBE-grown P-HEMT epiwafers. Tests will be performed by a device supplier (SIE) to evaluate the material quality. Comparison of the P-HEMT structures grown by MOVPE and MBE processes. In addition, application and quality as factors in production will be addressed. Establishing a European commercial source of GaInP/GaAs HBT epitaxial wafers. Evaluation and characterisation of materials developed by EPI and IAF by the industrial users in their standard production lines. Participants LEP (F), EPI (UK), DAIMLER-BENZ (D), THOMSON-CSF (F), GMMT (UK), FERDINAND BRAUN INSTITUT (D), FREIBERGER (D), PICOGIGA (F), SIEMENS (D), THOMSON LCR (F), FHG (D), FORTH (GR). Contact Point J-P ANDRE Laboratoires d'Electronique Philips 22 avenue Descartes - BP 15 94453 Limeil Brévannes Cedex (France) Duration 21 months from 01.05.96 tel: +33 1 45 10 68 04 fax: +33 1 45 10 69 53 E-mail: andre@lep-philips.fr 2 - 19 2. Enhancement of Technology and Manufacturing Base TCS 98 EP 23229 BETA Bipolar Epitaxial Si/SiGe Technologies for RF Applications Summary The aim of the project is to establish the added value of bipolar SiGe ICs with respect to Sibased and III-V solutions by both developing the required process technology and by demonstrating the manufacturability in application specific designs. Objectives Several application specific circuits based on the bipolar SiGe technology (time division multiplexer, divider, broad-band amplifier, LNA). These circuits will be state-of-the-art in terms of complexity (design and technology) and performance. Establish the technological targets which are expected to be necessary to realise these circuits. A technical and economical benchmark of the SiGe based circuitry as compared with Sibased and III-V based equivalents. A process technology available for selected key customers. Participants PHILIPS (NL), SIEMENS (D), TEMIC (D), ERICSSON (S). Contact Point Carel J. VAN DER POEL Philips Research Prof. Holstlaan 4 (WAG14) 5656 AA EINDHOVEN (The Netherlands) Duration 36 months from 01.01.96 tel: +31 40 2743685 fax: +31 40 2743390 e-mail: poelc@natlab.ressearch.philips.com 2 - 20 2. Enhancement of Technology and Manufacturing Base TCS 98 Microsystems EP 20342 DEEMO Dry-Etching, Electroplating and Moulding Summary A LIGA-like microsystem process to produce 3-dimensional microstructures with high aspect ratios will be developed. The development is based on an inexpensive fabrication process for microstructuring of different materials using high aspect ratio dry etching and reproduction in plastic microstructures with IC tolerances. Microassembly of the structures will also form part of the project. The technology will be suited for economical fast prototyping as well as production of certain products. Objectives Development of fast and versatile fabrication processes for mould inserts by means of high aspect ratio dry etching of silicon and metals. The silicon moulds can be used for an electroplating process, resulting in metal mould inserts for production of microstructures by means of moulding and embossing. The aspect ratios to be expected are 10 to 20 typically at diameters in the range of microns with profile control for releasing the structures. Development of a rapid prototyping process for microstructures with IC accuracy by means of e-beam lithography, dry etching and embossing. Demonstration of the process by selecting a pilot customer and fabricating the customer specific microstructures. Within this pilot production, a reduction of assembly costs and time will be demonstrated. Participants MICROPARTS (D); MICRO*MONTAGE (D); MESA (NL). Contact Point Dr. K. KADEL Microparts Hauert 7 44227 Dortmund (Germany) Duration 30 months from 01.11.95 tel: +49 231 9799130 fax: +49 231 9799100 E-mail: kadel@microparts .de 3-1 3. Microsystems TCS 98 EP 20360 MAGIC Magnetic Integrated Circuits for Industrial Switch and Sensor Applications Summary The goal of the project is to deliver packaged and tested evaluation samples of several specific CMOS integrated magnetic microsystems for a variety of attractive high volume applications as well as high-end safety products. The main objective is to elaborate, consolidate and to transfer to the industrial environment the know-how for mass production of versatile integrated microsystems based on magnetic sensors. The common ground is the design and test of CMOS based magnetic sensor and interface circuit prototypes by ETH Zürich and the University of Pavia, and their manufacturing by AMS. Objectives The work is centred around four demonstrators: Magnetic microswitch based on magnetic integrated circuits for automotive applications, to be exploited mainly by SAIA. The need to introduce a new technology for low current applications is dictated by SAIA's customers in view of potential Far Eastern and North American competition. Programmable rotary switch based on integrated magnetic sensors for consumer applications, to be exploited mainly by Seuffer. By mid 1996, a demand for engineering samples of electronic switchboards is anticipated, in order to replace the present electromechanical products. Current monitor based on integrated magnetic sensors for high-voltage power supplies and commercial vehicles, to be exploited mainly by CAEN and Seuffer. Three-dimensional magnetic badge to record exposure to magnetic fields based on integrated magnetic vector sensors, to be exploited primarily by CAEN. The targeted high-end product might be favoured by legislation in the medium term. Participants CAEN SPA (I), AMS (A), ETH ZÜRICH (CH), SAIA (CH), SEUFFER (D), PAVIA UNIV. (I) Contact Point Fabrizio CATARSI CAEN S.p.A. Via Vetraia 11 55049 VIAREGGIO (Italy) Duration 36 months from 01.01.96 tel: +39 584 388398 fax: +39 584 388959 E-mail: info@caen.it or catarsi@caen.it 3-2 3. Microsystems TCS 98 EP 20679 MIRS Micromachined Integrated Relay System Summary A cost-effective micromachined integrated relay is to be developed. The new feature of this relay is that it combines a hard-metal contact, electromagnetic actuation, as well as electronic circuitry on the same silicon substrate. The relay will be manufactured in a batch process in a way similar to IC fabrication. The feasibility of electromagnetic principles that are commonly employed in conventional reed relays for actuation of the relay will be investigated. Furthermore, special attention will be given to the development of reliable electrical contacts and of a suitable packaging technology. The actuator (e.g. a coil), the electrical contacts and the moving mechanical parts will be fabricated in an integrated process sequence using micromachining technologies. Objectives Development of a novel, low-cost, high quality switching technology, which combines the switching advantages of solid-state relays with those of hard-metal-contact relays where added value electronics can be implemented on a single silicon substrate. The microrelay must be small, display a low and stable contact resistance, a high offresistance and be low-cost. Development of a cost-effective fabrication process based on micromachining technologies for hard-contact relays with integrated electronic circuitry. Development of a contact technology that guarantees the required contact characteristics for life and which is fully compatible and integrated with the actuator technology and movable mechanical parts. Development of a low-cost packaging technology. Operative microrelays demonstrating the tools, features and technologies developed are to be produced. These will undergo full reliability testing in real user applications. Participants CP CLARE (B); CSEM (CH); IMEC (B); ARITECH (NL); SPEA (I). Contact Point Harrie A. C. TILMANS CP Clare Corporation Overhaamlaan 40 B-3700 Tongeren, (Belgium) Duration 29 months from 15.11.95 tel: +32 12 390 404 fax: +32 12 235 754 E-mail: tilmans@imec.be 3-3 3. Microsystems TCS 98 EP 21458 Si-GYRO Silicon Surface Micromachined Gyroscope for Mass Market Applications Summary A surface micromachined one-axis gyroscope mainly for automotive applications with strong market penetration is to be developed based on Thick Polysilicon Surface Micromachining (TPSM) technology. The basic process will be improved to meet the stringent requirements of the gyroscope application with respect to critical material and process parameters (control of active polysilicon layer stress and stress gradients, surface roughness, inclusion of a buried polysilicon contact layer, accuracy and aspect ratio of the microstructuring process, sacrificial etching techniques, housing and vacuum encapsulation of the sensor elements). Driving and evaluation circuitry will be realised on a separate chip and combined with the sensing device by hybrid mounting. Objectives Installation of a club of (automotive) end users to agree on a broadly based specification. Development of a surface micromachined gyroscope device for automotive applications with high resolution angular rotation (0.5 °/sec) and offset stability (0.1...1°/sec), based on the TPSM process. Reduction of thick polysilicon stress, stress gradients and surface roughness to extend the application of the TPSM process to the gyroscope. Introduction of a buried polysilicon layer with low electrical resistivity into the TPSM process. This layer is needed for capacitor fields underneath the moving gyroscope structures which provide the sensor signal, and for electrical contacting. Improvement of the high density plasma etching process. This is the key process for silicon surface micromachining and determines the quality of the sensor structures. Development of electronic circuitry to drive the sensor oscillation and detect the yaw rate signal. A breadboard version of the evaluation electronics will be debugged and optimised, serving as the basis for a monolithically integrated circuit chip. Fabrication of a demonstrator with sensor element and electronic circuit chip mounted together in a metal housing which will be evacuated and hermetically sealed. Participants ROBERT BOSCH GMBH (D), STS LTD. (UK), CNM (E), VOLVO (S) Contact Point Franz LAERMER Robert Bosch GmbH, FV/FLD Postfach 10 60 50 70049 Stuttgart (Germany) Duration 36 months from 01.03.96 tel: +49 711 811 7671 fax: +49 711 811 7042 E-mail: frlaerme@si0694.am.bosch.de 3-4 3. Microsystems TCS 98 EP 21796 IRMA Integrated Resonant Accelerometer Microsystems for Automotive Applications Summary A family of accelerometer microsystems will be developed for automotive applications based upon the following two types accelerometers; Crash sensors for frontal impacts and airbag applications range around 50g Crash sensors for side impacts and airbag applications range around 500g. The project will focus on the development of key process technologies including assembly and testing, product designs and manufacture and test of functional prototypes in coordination with the establishment of high volume production capabilities. Objectives Development of a 50g accelerometer sensor based on a bulk micromachined silicon resonator. Development of a 500g accelerometer sensor based on a bulk micromachined silicon resonator. Development of accompanying ASICs for integration with 50g accelerometer in a hybrid integrated microsystem for frontal impact airbag applications. Development of accompanying ASICs for integration with 500g accelerometer in a hybrid integrated microsystem for side impact airbag applications. Test and demonstration of the microsystems in the airbag application by Autoliv. Development and installation of the mass fabrication of silicon microsystems, glasssilicon-glass bonding, assembly and test. Participants SENSONOR (N), AUTOLIV (D), SINTEF (N) Contact Point Per OHLCKERS SensoNor Knutsrodveien 7 Horten, Vestfold County N-1392 (Norway) Duration 24 months from 01.01.96 tel: +47 33 035179 fax: +47 33 044098 E-mail: Per.Ohlckers@si.intef.no 3-5 3. Microsystems TCS 98 EP 22889 OLMO On-Vehicle Laser Microsystem For Obstacle Detection Summary A functional prototype of a compact laser-based system for obstacle detection on-vehicles is to be developed. New microsystem technologies are to be used to address the requirements of reliability, detection performance in adverse visibility, eye safety, and cost effectiveness. The key technologies are an eye-safe microchip laser at 1,5 m wavelength, and a beamscanning system based on micromachined lenses and flexure structures for actuation. Original signal processing circuits will be developed, where time-of-flight and correlation techniques are integrated, aiming to improve the operation in bad atmospheric conditions. A technical evaluation, including real-field tests, and an overall assessment of the solution will be performed. The system for obstacle detection will be the core component for driver support functions, with an high impact on safety, traffic efficiency and driving comfort. New application areas are also anticipated such as instrumentation, industrial automation and security systems. Objectives To demonstrate the feasibility of a miniaturized and integrated obstacle detection system based on laser technology, to be used for automotive applications, particularly Intelligent Cruise Control and Anticollision. To develop and make available the technology of small,eye-safe, solid-state microchip lasers with fast risetime and high peak power. To develop solutions for efficient laser beam scanning, which can withstand vibrations and guarantee long lifetime, integrating microoptics and micromechanics. To support the industrial evaluation of technologies for driver support functions, by a comparative assessment of the developed solution, and a review of application trends. Participants C.R.F. (CENTRO RICERCHE FIAT) (I), LETI (CEA- DIRECTION DES TECHNOLOGIES AVANCEES) (F), JENOPTIK LASERDIODE (D), MAGNETI MARELLI (I), RENAULT (F), CSEM (CENTRE SUISSE D’ELECTRONIQUE ET DE MICROTECHNIQUE) (CH). Contact Point Giancarlo ALESSANDRETTI Fiat Research Center Strada Torino 50 - 10043 Orbassano (TO) (Italy) Duration 21 months from 01.11.96 tel: +39-11-9023.595 fax: +39-11-9023.673 E-mail: gc.alessandretti@crf.it 3-6 3. Microsystems TCS 98 EP 22966 AWARE Anti-Collision Warning and Avoidance Radar Equipment Summary The AWARE project will specify and develop a 77 GHz scanning radar Collision Warning and Avoidance (CW/A) vehicle system. The CW/A system is intended to be applicable in motor- and highway traffic. (Dense city traffic and lateral manoeuvres are not covered at this stage). Moving and stationary obstacles in front of the vehicle are detected by the CW/A radar. Post-processing modules analyse the radar data, and when necessary the driver is alerted. In critical situations (when driver reaction is too slow) the brakes can automatically be applied. The starting point is to consolidate experiences and developed technologies regarding Adaptive Cruise Control vehicle systems (a system adapting speed and distance to the preceding vehicle). The stricter requirements by the users (drivers), the automotive manufacturers and the market on the CW/A system regarding among others functionality, reliability and cost, will be met through a MMIC based radar front-end, advanced antenna and signal processing for horizontal and vertical resolution, modules for evaluation of risk of collision, and strategies for informing the driver and braking the vehicle. Prototypes of CW/A radar and vehicle systems will be realised for evaluation and “marketing” of results. Plans for exploitation of the developed CW/A system are included. Project Objectives Requirements and specifications on 77 GHz radar sensor for automotive CW/A applications, feasible w.r.t. users/drivers needs and expectation on function and price. Technology, components, complete prototypes of radar sensor and vehicle system proven feasible w.r.t. requirements, functionality and volume production. Evaluation results of prototype CW/A radar and system. Plans and results (functional, technological, collaborative) for industrialisation and commercial marketing of the developed CW/A radar. Participants: AB VOLVO (S), CELSIUSTECH ELECTRONICS (S), CENTRO RICERCHE FIAT (I) UNITED MONOLITHIC SEMICONDUCTORS (F). Contact Point Ulf PALMQUIST AB Volvo, Tech. Dev. Chalmers Science Park S-412 88 Göteborg, (Sweden) Duration 30 months from 01.07.1997 tel: + 46 708 44 46 09 fax: + 46 31 772 40 86 E-mail: ulfp@vtd.volvo.se 3-7 3. Microsystems TCS 98 EP 25190 INTACT Intelligent Automotive Actuator Control & Communication Techniques Summary INTACT will develop an intelligent vehicle rear light system capable of automatically controlling its brightness dependent on the environmental conditions and the state of the rear light lens which will also be fault tolerant related to lamp failures by incorporating dual role functions in each light source. This new generation of rear lights will be based on LED illumination technology with the intelligence an control being achieved by utilizing the latest integrated micro-systems combination with CAN communication as well as new innovations in the miniaturization of existing weather sensors. Objectives Design of an intelligent rear light that can be marketed at an acceptable price to be fitted into a production car within a few years. Utilising existing applications of microprocessor control, CAN communication and MOSFET technology to enable the control and intelligence requirements. Research and model the characteristics of the physical weather variants that exist around the rear light which includes rain, fog, mist sunlight and dirt. Miniaturisation of existing weather visibility sensors to enable them to be integrated into a final prototype rear light system. Intelligent environmental sensor fusion including self-diagnosis of fault conditions. High volume assembly of LEDs, sensors and microprocessor components into the rear light cluster. LED light performance twice that of a conventional filament bulb to allow automatic brightness control. Participants REITTER&SCHEFENACKER (G), STEINBEIS STA (G), PRESSAC (UK), JL-AUTOMATION (UK), JENOPTIK (G), UNIVERSITY OF DUNDEE (UK) Contact Point Helmut HAF Reitter&Schefenacker GmbH & Co.KG Advanced Development Eckenerstr. 2 73730 Esslingen (Germany) Duration 30 months from 01.09.1997 tel: + 49 711 3154 166 fax: + 49 711 3154 256 e-mail: helmut_haf.rus@t-online.de 3-8 3. Microsystems TCS 98 EP 20848 PARFUM Process control and Air cleaner applications with Recognition of gases and Flavours Using a smart Microsystem Summary The objective of the project is to demonstrate and implement smart microsystems for gas analysis and odour recognition based on state-of-the-art sensor technologies, data processing and analysis techniques. The project will be strongly application driven and address two areas: domestic appliances (air cleaner) for gas detection (CO, NOx, SO2, HCHO) process and quality control in food industry applications (detection of off-flavours and volatile based raw material defects and product classification). Objectives Design and development of thin-film semiconductor oxide gas sensors on a silicon substrate. Miniaturisation and high integration techniques will be used to achieve low production cost, large number of sensors per wafer and performance reproducibility. Specific development of a new generation of gas sensors by integrating them on the same chip, resulting in a monolithic multisensor array. Unique combination of expertise in process knowledge, sensor technology and data analysis for implementation of smart gas-odour detection microsystems. Advanced neural network algorithms for adaptivity, robustness of measurements and error-free analysis. Application of such gas detection microsystems into the next generation of domestic air cleaners of the Product Division of Philips DAP. Application of the odour recognition system to process (or quality) monitoring in the field of off-flavour and contaminant detection related to packaging. Participants LEP (F); DAP (NL); NESTEC LTD (CH); MICROSENS (CH); CSEM (CH); NEOTRONICS SCIENTIFIC (UK); IPC (D). Contact Point Serge GOURRIER Laboratoires d'Electronique PHILIPS S.A.S. 22 av. Descartes, BP 15, F-94453 Limeil-Brevannes (France) Duration 36 months from 01.12.95 tel: +33 1 45 10 68 94 fax: +33 1 45 10 67 43 E-mail: gourrier@lep-philips.fr 3-9 3. Microsystems TCS 98 EP 21428 SMOG Smart Air Pollution Monitoring Network Summary A miniaturised air quality monitoring station for use in urban environments, capable of detecting a range of important air pollutant species (e.g. CO, NOx, O3), produced by road traffic, will be developed using a novel system architecture. The heart of the SMOG demonstrator will be an array of miniaturised silicon-integrated metal-oxide gas sensors that will allow a drastic reduction in volume and power consumption of the monitoring station. Selective detection of the individual target gases will be enabled by state-of-the-art pattern recognition techniques. To reduce dead volumes, the development of a miniaturised actuator system will constitute an important goal of the project. Objectives Substrate heater elements characterised by low power consumption, improved thermal and mechanical stability; membranes made of either amorphous or crystalline silicon carbide, or porous silicon, will be the core of the new advanced substrates. Miniaturised and silicon-integrated gas sensor integrated into a system of actuator components; the sensor arrays will consist of micromachined gas sensor elements which incorporate advanced metal-oxide-semiconductor films as gas sensitive materials. Gas handling system with integrated silicon microactuators and sensor components; the basic and most innovative devices of the gas handling system will be microvalves and micropumps realised by silicon micromachining (extended feasibility study). Advanced techniques for sensor control, signal conditioning and pattern recognition; in particular, they will include sophisticated approaches for sensor calibration and signal evaluation; the latter will be performed using artificial neural networks and logic techniques. Miniaturised gas monitoring station characterised by small dimension, reduced power consumption, low investment cost, easy exchange of subsystem components, self calibration and testing of sensor units, long service-free operational periods. Participants PHILIPS AUTOMATION (I), DAIMLER-BENZ (D), CNR-LAMEL (I), INFM-TFL (I), IMSAS (D), ENVIRONNEMENT (F) Contact Point Massimo NINI Philips Automation S.p.a. Via Casati 23 20052 Monza (Mi) (Italy) Duration 36 months from 15.05.96 tel: +39 39 2036882 fax: +39 39 2036724 3 - 10 3. Microsystems TCS 98 EP 25296.ACS Microsensor system for automatic process control in a food industry Summary The aim is the development of a chemical microsensor-based modular system for chemical control and monitoring in an industrial environment and its application into an automatic process control system (ACS) for the dairy industry. The system will make measurements in-line or at-line during production, transmit the data to a processing system which compares them with pre-defined values, and controls the process via an interface to the plant’s control systems. The plant control system is used to download the required process parameters to the ACS. ACS is will give closer control of the process based on real-time measurements, and reduce wastage and reliance on skilled operators. Objectives Design and develop an encapsulated ISFET sensor module for pH, Ca2+ with a temperature sensor module suitable for use in at line automated sampling and measurement Develop microfabricated conductivity sensors for measurement in liquids with encapsulation to withstand cleaning in place Redesign transducer to be able to process a minimum of 100 channels of NIR spectral data from 2 NIR probes, at data rates appropriate for real-time process and to simultaneously control and receive data from 8 chemical sensor modules Increase the capability of the cell controller to process the data received from a number of transducers, and display the results from all the sensors and NIR probes Derive an algorithm which corrects NIR readings of fat and protein content for variation in pH, temperature and conductivity Design and develop a NIR probe for in-line measurements in milk, suitable for use in a production plant environment, with CANBUS communication to the transducer. Install the ACS in a production plant of an end-user partner Participants CENTRAL RESEARCH LABORATORIES LTD (GB); K.A.T. GMBH (D); KERRY INGREDIENTS (IRELAND) LTD (IE); NATIONAL MICROELECTRONICS RESEARCH CENTRE (IE); CENTRO NACIONAL DE MICROELECTRÓNICA (ES); PDV UNTERNEHMENSBERATUNG GMBH (D), GRUP FIBOSA, S.A. (ES), UNIVERSITAT AUTÒNOMA DE BARCELONA (ES) Contact Point Stephanie Dyson HEIDRICH CENTRAL RESEARCH LABORATORIES LTD Dawley Road HAYES Middlesex UB3 1HH (United Kingdom) Duration 34 months from 15.11.97 tel: +44 (0)181 848 6417 fax: +44 (0)181 848 6442 E-mail: sheidrich@crl.co.uk 3 - 11 3. Microsystems TCS 98 EP 21152 QUANTUM Sensors for Chemical Species Based on Luminescence Decay Time Measurement Summary QUANTUM aims to develop portable instruments for the measurement of oxygen in water analysis and during blood gas analysis. The instruments will be based on luminescence decay time measurement rather than luminescence intensity measurement. The project encompasses the development of two complete systems including opto-chemical sensors, optics, opto-electronics and instrumentation assembly. The high stability of sensors based on luminescence decay time measurement can be exploited to eliminate field calibration or to restrict this calibration to a one point test, reducing the cost and widening the application range of these sensors in industry and for environmental monitoring. Objectives To start from the existing technology base in intensity-based optical oxygen sensors and measurement systems, and to introduce the luminescence decay time measurement into these systems. To investigate new oxygen sensitive luminescent dyes, Pt and Pd complexes of porphyrin-ketones, suitable for sensors and their application in the measurement systems. To develop, based on the new sensors, simplified optics and new production techniques for the mass production of cheap measurement units and to characterise these units to fulfil the specifications under all environmental conditions. To design an integrated circuit for signal generation, acquisition and processing which together with an Analogue to Digital Converter and a microcontroller can implement all processing required for a vector time measurement system. The preparation of the commercialisation of opto-chemical sensors in blood gas analysis and in water analysis in industrial and environmental applications Participants JOANNEUM RESEARCH (A), AVL LIST (A), WTW (D), UNIV. OF KENT (UK). Contact Point DI. Franz REININGER Joanneum Research, Steyrergasse 17, A-8010 Graz, (Austria) Duration 36 months from 01.01.96 tel: + 43 876 223 fax: +43 876 181 E-mail: reininger@joanneum.pbox.ac.at 3 - 12 3. Microsystems TCS 98 EP 21245 IMALP Implantable Liver Pump Summary The IMALP project develops a microsystem incorporating a blood pump to improve functions in patients with liver cirrhosis. The proposed system will comprise a fully implantable electric micromotor driven micropump incorporating 'smart' flow, pressure and temperature sensors based on CMOS technology. By employing state-of-the-art ASICs, sensing and electrical processing of sensor signals will be performed on ICs installed within the motor/pump housing, which will be small enough to be implanted into the portal vein of the liver using minimally invasive procedures. Objectives Development of an implantable blood pump system capable of delivering a flow rate of 1 to 2 litres/minute against a back pressure of up to 50 mm Hg with a maximum diameter of 8 mm and maximum length of 30 mm. Development of efficient sensing and control functions to the implanted motor/pump system and transmission of power and data by 'leadless' electromagnetic transmission through sub-cutaneous tissue. Development of a compact, efficient, high energy, rechargeable battery which can be implanted just below the skin. In vitro liver test models for testing the implantable pump system. Participants GUIDANT BELGIUM (B), ETEL (S), FHG IMSS (D), HAMMERSMITH HOSPITAL (UK), HELMHOLTZ INSTITUT FÜR BIOMEDIZIN (D), HERIOT-WATT UNIV. (UK), IMEC (B), KATHOLIEKE UNIV. LEUVEN (B), ST ANDREWS UNIV. (UK), ULTRALIFE BATTERIES (UK). Contact Point Dr. Rolf SAMMLER Guidant Belgium, Excelsiorlaan 37, 1930 Zaventem, (Belgium) Duration 36 months from 01.01.96 tel: +32 2714 1461 fax: +32 2714 1414 3 - 13 3. Microsystems TCS 98 EP 22982 NICE Real-time 3d ultrasound imaging system with advanced transducer arrays Summary The aim is to lay the foundation for a 3D ultrasound imaging system where the emphasis is on real-time data acquisition and near real-time data visualization. New features of this system are: i) two-dimensionnal transducer arrays using advanced microstructuring and interconnect techniques; ii) compact front-end electronics (beam former) combining rescaled ASICs and multi-chip modules. Prototype probes will be developed and implemented on a down-scaled beamformer prototype. Image quality evaluation will be performed using tissuemimicking phantoms. Objectives Definition of a scanning strategy with the aim of minimizing the number of channels, based on sparse array methods. The goal is to be able to find the best, sparse array layout pattern for a 2000-3000 element array, leading to optimum image quality with respect to the clinical application. Design of electroacoustic structures taking into account specific issues of high density 2d arrays operating at high frequencies. Establishment of key technologies for the transducer array manufacturing: especially controlled microstructuring, high density interconnects and micropackaging techniques. Development of a compact beamformer to support enough channels. Size, consumption and cost reduction will be achieved by scaling and integration of A/D converters and Focusor ASICs, and by tighter integration of analogue front-end electronics with the use of multi-chip modules. Integration of probe and beamformer prototypes. Data acquisition, processing and evaluation using tissue-mimicking phantoms, with respect to image quality. Participants THOMSON MICROSONICS (F); VINGMED SOUND A/S (N); UNIV. OF OSLO (N); THOMSONCSF/LCR (F); CRANFIELD UNIV. (UK); FRAUNHOFER INSTITUTE/IBMT (D). Contact Point Jean-Marc BUREAU Thomson Microsonics 399 Route des Crêtes 06904 SOPHIA ANTIPOLIS (France) Duration 30 months from 01.10.96 tel: +33 (0)4 92 96 32 95 fax: +33 (0)4 92 96 40 80 E-mail: bureau@tmx.thomson.fr 3 - 14 3. Microsystems TCS 98 EP 25644 TRAnsformers using MicroSystems Technology Summary During the last years, a clear trend to miniaturise electronic equipment has been detected world-wide. This trend is especially clear in the case of portable terminals for mobile communications. TRAMST aims to achieve a significant reduction in size and weight of the low power AC/DC adapters used for mobile phones. This can be achieved by replacing the classical transformer which is built with commercial magnetic cores that not only limit the miniaturisation of the converter but are also EMI sources, by an alternative piezoelectric transformer, which features very low profile, very high power density (10 times higher than magnetic ones) and low EMI generation. Piezoelectric transformers transmit energy from its input to its output through mechanical vibration of the ceramic layers from which it is made. This technology can also be used in other applications such as DC/DC converters for telecommunications applications, power converters for PCs, displays, portable equipment, etc. Objectives The main goal of this project is to reduce the size and weight of low power AC adapters used in portable equipment for mobile communications. Further objectives are: Develop a high power density AC adapter demonstrator (6 W/in3), featuring low size, low profile and reduced weight. Increase the power density of the power transformers for low power applications to achieve power densities 10 times higher (85 W/in3) as with conventional magnetic transformers . Develop cost effective processes to develop ceramic materials that enable the use of piezoelectric devices as power transformers. Develop new electrical and mathematical models that describe the functioning of piezoelectric transformers. Test and design new power topologies and control schemes that make suitable the use of piezoelectric transformers in power electronics. Extend this technology to other applications (power converters for Telecommunications, for PCs, portable terminals...) Participants ALCATEL ESPAÑA S.A. (E); FERROPERM (DK); UNIV POLITÉCNICA DE MADRID (E); UNIV. DE OVIEDO (E) Contact point SALVADOR OLLERO Alcatel España S.A. - Ramirez de Prado 5, MADRID 28045 (España) Duration 24 months from 01.07.97 Tel: 34 - 1 - 330 43 61 Fax: 34 - 1 - 330 50 60 e-mail: ollero@alcatel.es 3 - 15 3. Microsystems TCS 98 Peripherals EP 20310 ECAM III European Consortium Active Matrix LCD Summary ECAM III follows ECAM I and II, and aims at enhancing the existing European capability in flat panel display production. The ECAM III project focuses on the development and demonstration of state-of-the-art active matrix liquid crystal displays for low cost applications in business, consumer and industry. Project targets are 1.4" high resolution displays for projection, and industrialisation and fabrication with high yield of VGA and SVGA graphic data displays. Efforts will also be devoted to reducing the operating power of the graphic data displays, development of digital signal processing capabilities, module assembly development and continued research in polysilicon, especially geared towards low cost projection. Objectives Manufacturing Science and Technology for improving the production capability and performance of AMLCDs is a major part of the work in this project. Improvement of yield, of manufacturing equipment and of methodologies receive particular attention. A TFT technology suitable for low cost, small pitch, projection light valves and key components such as micro-lenses, lamps and screens will be developed further. The development of reflective polarisers as part of an efficient backlight system for use in active matrix TN displays. The creation of the know-how and infrastructure for the assembly of high quality low cost LCD modules will enhance existing, or create new capabilities, in this domain. Participants FPD (NL), THOMSON LCD (F), MERCK (UK), SAGEM (F), CIBA (CH), THOMSON MM (F), BARCO (B), PRL (UK), THOMSON LCR (F), CORNING (F), REXHAM (UK), CNR (I) Contact Point Dr Wanter REINTS-BOK FPD B.V. Building WAY-2 Prof. Holstaan 4 5656 AA Eindhoven (The Netherlands) Duration 24 months from 01.01.96 tel: +31 40 274 43 71 fax: +31 40 274 22 23 4-1 4. Peripherals TCS 98 EP 20771 LIPP Very Large Flat Plasma Display Panel for Industrial Process Control Summary Industrial markets (factory and office automation, air traffic control, public information boards, etc.) present a demand for high resolution, large area, flat, colour displays to improve data visualisation and concentrate multiple information on a single screen of large size and limited volume. These displays will be the core of the factory of tomorrow, and are not yet available. Plasma Display Panel (PDP) is a strong candidate technology to fulfil these requirements. It is expected to produce 20" to 40" or greater, flat, colour displays within the next 5 to 10 years thanks to the particular operating behaviour (memory effect), simple manufacturing process and production tooling used. An industrial process display monitor is under development at THOMSON TUBE ELECTRONIQUES, the only European PDP manufacturer. Technology innovation is ongoing in the area of panel processing, large area masks, driver electronics and full digital interface. The Automation Department of SIEMENS will integrate the developed PDP in an existing control system and test it in a real application environment. TERAPIXEL, is involved in the development of large area masks for PDP photolithography. ELDIM is developing the interface electronics (with the capability of fully digital data exchange) between the panel and the computer. Objectives development of a 24" diagonal PDP demonstrator with high resolution: 1280x1024 pixels, full colour, 3" thick, 160 degree viewing angle, and multimedia compatibility. feasibility study of a 40" diagonal high resolution PDP for professional applications. development of photomasks for large size PDPs. development of analog and digital interface cards for large area flat panel displays (PDP). demonstration of use of 24" PDPs for use in industrial process control. Results SIEMENS has specified user needs and is monitoring market trends. A first 24" PDP mock-up has been produced by TTE with encouraging results. Analog interface boards from ELDIM have been delivered; digital video adaptor feasibility study is in progress. First prototype sets of masks for the 24" PDP are available, further developments are ongoing at TERAPIXEL. Studies on 40" high resolution PDP feasibility for professional applications are ongoing at TTE. Publications on the development of the 24" plasma display appear in Electronique International, Euro Photonics, Electronic Display World, Laser Focus World, Opto Laser Europe. Participants THOMSON TUBE ELECTRONIQUES (F); SIEMENS (D); TERAPIXEL (SF); ELDIM (F) Contact point M. SPECTY 18, Avenue du Maréchal Juin 92366 MEUDON LA FORÊT (France) tel: +33 76574019 fax: + 33 76574085 Duration 24 months from 01.12.95 4-2 4. Peripherals TCS 98 EP 21657 BLUE BIRD High Capacity blue source based magneto-optical disc drive dedicated to network integration Summary The project objective is to address the need to handle files of ever-increasing size, to access them in the shortest time, to acquire and transfer information as quickly as possible, to ensure the safety of the stored information on a media and to reuse the same media. The project work will entail: Development of a powerful optical source (15mW, in pulse mode with a 50% duty cycle) operating at wavelengths of 430 to 480 nm obtained by frequency doubling. Development of a MO layer sensitive at these short wavelengths. The basic material is a type of ferrite with a very high Kerr rotation, high stability, allowing a large number of write/erase cycles with a high contrast. Mastering of technologies needed in an optical drive (optical heads, blocks, servomechanisms and algorithms to access to the information, electronics for signal treatment, writing/erasing strategy and logical formatting for the capacity and controller for the transfer rate. Integration of software layers into the drive in order to connect directly the machine to networks such as FDDI, Token Ring, Ethernet with DECNET, TCP/ip, NFS, Ethershare, LAN Manager and IPX network protocol. Objectives A rewritable high–performance optical storage peripheral directly connectable to a network, The rewritable optical storage peripheral will feature: a double-headed magneto-optical 12’’ drive, a double-sided magneto-optical disk, featuring a large capacity, in the range of 30 GBytes (twice the capacity foreseen for the products just to come), a high data rate in the range of 5 Mbytes/sec (average user data rate), a long user data life after recording and the ability to withstand a large number of write/erase cycles (>5.106) a direct connection to a network; the interface between the drive and the connection device will allow high performance: high data transfer rate and 16 bits (SCSI-2 fast and wide); the network connection will be an add-on element connected to the rear panel of the drive. Participants ATG (F); THOMSON-CSF (F); IAN (I). Contact Point Patrick LANGLADE – ATG Avenue Général Eisenhower 31047 TOULOUSE CEDEX (France) Tel: Fax: Duration 30 months from 02.05.96 +33 5.62.14.21.00 + 33 5.61.41.03.49 4-3 4. Peripherals TCS 98 EP 22575 ELDISP Next Generation Colour Electroluminescent Displays Summary The ELDISP project is aiming to develop the next generation of colour electroluminescent (EL) flat panel displays. It will also develop technologies for pilot manufacturing capacity for the production of these new displays. The target is cost effective, high performance EL displays based on the filtered concept with broad-band white light emitting phosphors. The new generation of colour EL displays will target the existing European and worldwide industrial and transportation market segments, as well as specific new consumer applications. Objectives The main objectives are to develop 8.4” to 10.4” VGA resolution colour displays for graphic display applications and 4.8” quarter VGA displays for graphic applications. In order to achieve these objectives the consortium will address: the development, scale-up and application of improved broad-band white light emitting phosphors as a crucial part of the work. the development of the new inverted and filtered EL display structure and pilot manufacturing processes the development of cost effective colour filters and high density interconnection techniques. the improvement and modification of the EL display driving circuitry, as well as the development of the equipment interfacing circuitry. Participants PLANAR (SF); CRL (UK); ERICSSON (S); HHI (HEINRICH-HERZ-INSTITUT (D); SAGEM (F); SGS-THOMSON (I); UPMC-AOMC (UNIVERSITY OF PARIS)(F). Contact Point Mr Arto PAKKALA PLANAR International Ltd PO Box 46, Olarinluoma 9 FIN-02201 ESPOO, (Finland) Duration 36 months from 01.11.96 tel: +358 9 42001 (direct: 4200316) fax: +358 9 4221432 E-mail: arto-pakkala@ planar.com 4-4 4. Peripherals TCS 98 EP 22615 PHOSPAP Development of Vacuum Ultraviolet (VUV) Phosphors for Large Plasma Display Panels Summary The project aims at the development of optimized phosphors with characteristics adapted to large size Plasma Display Panels (PDPs) used in future consumer TV and professional applications, as well as at the implementation in Europe of the manufacturing of such phosphors. The developed phosphors will have lower decay time (no smear on moving images), smaller grain size (higher pixel resolution), higher luminous efficiency (higher brightness of the screen or lower power consumption), more saturated colours (expansion of colour gamut). Objectives Reduction of the grain size of the red and blue phosphors currently used in PDP manufacturing, without degrading the other characteristics, particularly the luminous efficiency; Synthesis at a lab-scale level of green phosphors with high luminous efficiency = commercial P1, decay time t10% = 10 ms, grain size m = 3 µm, X = 0.30 and Y = 0.60. Selection of the best green phosphor; Scaling-up of the improved green, red and blue phosphors and evaluation on 9" monochrome PDPs; Manufacturing of a 24" trichrome PDP demonstrator using the conventional PDP manufacturing process. Partners: THOMSON-CSF/LCR (F), PHILIPS RESEARCH LABORATORIES (D), TECHNICAL UNIVERSITY DELFT (NL), PHOSPHOR TECHNOLOGY LTD (GB), THOMSON TUBES ELECTRONIQUES (F) Contact Point Antoinette MORELL Thomson-CSF/LCR Domaine de Corbeville 91404 ORSAY Cedex (France) Duration 24 months from 01.10.96 Tel : + 33 1 69 33 91 36 Fax : + 33 1 69 33 07 55 E-mail : morell@lcr.thomson.fr 4-5 4. Peripherals TCS 98 EP 22659 FED Development of a 5.2 " FED Colour Display Summary Building on the foundations of AIMFED, and taking into account the specific requirements of European instrumentation for transport and industrial markets in the area of displays, FED is a focused R&D program leading to an extension of the FED performance envelope towards higher brightness and power efficiency. The display will be, by the end of month 18, a 1/4 VGA, 5.2”, 150 cd/m2 full colour display. Objectives Extension of the performance envelope associated with PixTech’s FED, towards higher brightness and power efficiency. FED technology improvements include: An anode with a voltage stand-off up to 600 V. A transparent cathode for an inverted structure allowing a brightness improvement of a factor 2 relative to the standard structure. New phosphors with a mean luminescence efficiency of 3 lm/W in the white. Demonstration and full testing of 5.2’’, 1/4 VGA, full colour display with following basic characteristics: Luminance 150 cd/m2 in operation Contrast ratio 12:1 in a 500 lux ambient light 6 to 8 bits grey scale depending on market requirements More than 5000 hours lifetime in full white Further development of FED specific materials and equipment, including holographic exposure equipment : The hologram masks with 0.6 µm microhole diameter Zero defect holograms Equipment specification targeted to a production machine, with automated substrate handling system, a production friendly H-Mask changing system, an on-axis illumination system for the alignment and an environmental control system. Participants PIXTECH SA (F); HOLTRONICS SA (CH); INS STUTTGART (D); LETI-CEA (F); RHONE POULENC (F); SAES GETTER SPA (I) Contact Point Duration Christophe SALVAN PixTech SA Parc Industriel de la Pompignane Rue de la Vieille Poste 34055 Montpellier cedex (France) 18 months from 01 Feb. 97 tel: fax: +33 (0) 467 344 394 +33 (0) 467 650 821 4-6 4. Peripherals TCS 98 EP 25340 MOSAREL Monocrystalline Silicon Active Matrix Reflective Light Valve Summary An ultra-high resolution projection display system based on reflective light valves (LV) with 25602048 pixels will be developed. The applications are graphic workstation displays (enduser Barco) and head-up displays (HUD) (end-user Sextant). Combining a 0.7 µm CMOS technology for self-scanning active matrix addressing with a reflective nematic liquid crystal (LC) technology, the LV can be realised in existing ASIC (Alcatel-Mietec) and LC (Thomson-LCD) facilities, without major investments. All necessary design and backend processing (IMEC) and LC (Stuttgart) skills are present in the consortium. 15 µm pixels yield small 3831 mm LVs, a requirement in light, compact, cost-effective optical projection systems. Barco has proven that the development of an AMLCD technology for the targeted professional high-end display market can become an economic success and must develop higher resolution display systems to secure its position as a world leader in this market. Sextant is European leader in electronics units for aeroplanes. The availability of the targeted LV would reduce weight and volume and improve the potential of the increasingly important HUD-based landing systems. Objectives provide an alternative for existing transmissive active matrix displays to European flat panel display users and OEMs develop expertise on ASIC design for AM-LVs and set up new flat panel display producing possibilities by this “ASIC approach” for active matrix LCDs establish an ultra-high resolution reflective LC technology for AM displays, by using advanced Si processing and LC materials selected in the project provide design flexibility to European display manufacturers, as well for small quantities (high-end products) as for larger ones (cost determined) open new markets because of cost reduction for active matrix displays (reducing pixel sizes and integrating driving electronics on the active substrate) and by introducing new applications due to the higher resolution that is possible with the techniques developed develop a graphic workstation display around the developed LV develop a HUD demonstrator around the developed LV Participants BARCO (B), ALCATEL MIETEC (B), IMEC (B), UNIVERSITY OF STUTTGART (D), THOMSONLCD (F), SEXTANT AVIONIQUE(F) Contact Point Patrick VANDENBERGHE, Theodoor Sevenslaan 106 B-8500 Kortrijk, (Belgium) Duration 24 months from 1.09.97 Tel: +32 (0) 56 23 32 11 Fax: +32 (0) 56 23 33 32 E-mail: patrick.vandenberghe@barco.com 4-7 4. Peripherals TCS 98 EP 25187 Se-BN-LCD SURFACE EFFECT BISTABLE NEMATIC LIQUID CRYSTAL DISPLAYS Summary The main aim of this project is to develop new ‘surface effect bistable nematic’ liquid crystal screens. This new display technology, developed from basic, is characterised by its intrinsic memory (in other words, the information written by electrical signals persists after the electrical signals are removed), by its speed and by its potentially low mass production cost. The use of this technology will open the door to new product ranges, thus consolidating the industrial base which should, at a later stage, lead to the development of this new technology on flat screen markets today inaccessible to European industry. The work to develop these displays will be followed by an LCD manufacturer, in order to prepare for future industrialisation. Objectives Development of technologies required for production of a multiplexed demonstrator. Prototyping of displays for tests (static and multiplexed matrix). Development of electronic units (tests and demonstrator). Realisation and integration of a matrix demonstrator with its electronics (minimum multiplexing ratio of 32). First evaluation for industrialisation of manufacturing process for ‘bistable nematic’ screens. Participants SFIM REOSC (F); INFM (I); TECHNOPOLIS CSATA NOVUS ORTUS (I); TECDIS SPA (I); UNIVERSITÉ DE PARIS (F). Contact Point Mr. A. BOISSIER SFIM REOSC Avenue Paul Dautier 78140 VELIZY (France) Tel: Fax: Duration 12 months from 01.09.97. +33.1.69.89.76.27. +33.1.69.89.76.20 4-8 4. Peripherals TCS 98 EP 25224 VISUFLEX BISTABLE REFLECTIVE FLC DISPLAYS ON PLASTIC SUBSTRATES FOR SMART CARDS Summary This pilot project aims at demonstrating the feasability of a display component dedicated to the smart cards (with or without contacts) and the tag markets. To achieve such a display component the technology has to meet the overall specifications of the smart cards (mechanical, electrical, environmental, etc) and the requirements for low manufacturing cost (material, labour, depreciation). This pilot project, based on the fundamental research already conducted by the partners, aims at demonstrating a viable answer to these 2 challenges. Objectives Application requirements and evaluation: the use of displays in smart cards will demand specific requirements such as flexibility, geometry, temperature range and addressing voltages which have to be specified and carried out with the prototypes to perform and evaluation. Technical objectives: investigations on the ferroelectric materials, the plastic substrates, the barrier and alignment layers, glue and sealing materials and the compatibility between these various materials. Addressing schemes and circuitry will be developed adapted to the requirements of the displays and the smart card chips. These evaluations will be concluded with the manufacturing of several prototypes. Printing technologies: to reach the low cost target, work will be carried out for adapting printing technologies to the specific display requirements. The process will be investigated and developed to a degree that prototype displays can already be fabricated by printing and with the goal to be scaled in the future to continuous roll-to-roll processes. Participants GEMPLUS (F); UNIV. OF STUTTGART (D); HOECHST AG (D); INSA-LYON (F). Contact Point Mr. P. FOUGERE – GEMPLUS Rue Guynemer 34 92447 ISSY-LES-MOULINEAUX (France) Tel: Fax: Duration 12 months from 01.07.97. +33.1.46.48.20.32. + 33.1.30.50.90.92. 4-9 4. Peripherals TCS 98 EP 25498 LAMPADY Large Multimedia Plasma Display Summary This project focuses on research and development of colour plasma displays with screen sizes 42” and above. The main applications are consumer: digital television and multimedia. Considering the increasing user and market demand for large and flat displays and based on the Plasma Display Panel (PDP) technology of Thomson Tubes Electronics, the project aims at further developing the PDP and underpinning technologies (e.g., signal processing, electronics, etc.). Objectives General architecture and subassemblies for prototyping of 42’’ and above, 16/9 Multimedia plasma displays. Panel design and development. Plasma modules electronics. Demonstrators for multimedia and PC interfaces. Panel technologies for performance improvements. Definition and conception of pilot engineering process. Participants DEUTSCHE THOMSON BRANDT (D); CERDEC (F); GLAVERBEL (B); THOMSON TUBES ELECTRONIQUES (F); SGS-THOMSON MICROELECTRONICS (F); THOMSON MULTIMEDIA (F); SOPRA (F). Contact Person Mr G. RILLY Deutsche Thomson-Brandt GmbH Hermann-Schwer-Strasse 3 78048 Villingen-Schwenningen (Germany) Duration 24 months from 01.07.1997 Tel: +49.7721.85.21.85 Fax: 49.7721.85.22.35 4 - 10 4. Peripherals TCS 98 EP 21674 SCOTSMAN Strategic Components, Technologies & Systems in Magnetic Storage Summary The SCOTSMAN project builds on the successful results obtained in EP 9257 MAGDRIVE, where a 540 MB hard disk with removable cartridge has been developed and put into production, and EP 6189 MIHFAD where advanced magnetic heads where achieved. The goals of the project are to develop technologies for magnetic hard disk drives, to use them to realise two products for personal computers, and finally to integrate the new devices in system applications taking advantage of the new capabilities (listed below). Objectives a 1.5 GB 3½" single plater removable cartridge magnetic disk drive compatible with the common PD standard promoted by Nomaï and Syquest together with a range of application-optimised 3½" cartridges – plus a prototype double plater version using GMR heads an 800 MB 1.8" PC Card magnetic disk drive – plus a prototype 1.3 GB version using GMR heads an 800 Mbpsi planar inductive head – plus a prototype 1.2 Gbpsi version flexible circuits for the head/arm electronics for both disk drives a video editing demonstration system using the cartridge drive an electronic newspaper demonstration system using the PC Card drive Participants NOMAÏ (F); CALLUNA (UK); SILMAG (F); MYRICA (UK); XYRATEX (UK); FAST(D); ACORN (UK) Contact Dr. Nigel MACKINTOSH Mackintosh Consultants The Chase, Pinfold Lane, Northop Hall, Clwyd CH7 6HE, (United Kingdom) Duration 18 months from 01.02.96 tel: +44 244 819797 fax: +44 244 819796 E-mail: nigel@ndmack.demon.co.uk 4 - 11 4. Peripherals TCS 98 EP 21314 ELECline Electrical line for full compatible appliances, communications and utilities equipment Summary Products are to be developed with integrated EHS (European Home System) interfaces using the power line as a medium for the data transfer. These products will be configured and installed in two demo sites, one in Spain and one in Italy. The focus is to optimise the energy and load management as well as the comfort. For the first one an interface between utilities and the customer is developed to allow the utility to offer new services to the customer. In the second, a homogenous interactive television set-top box enables the client to configure his own system in a very user-friendly way. Additional communication products like PSTN gateways and CATV gateways will also permit a remote configuration and monitoring of the EHS functions by any external service provider. Objectives To define and implement the functional and architectural specifications for the products that will be developed within the project (intelligent sockets, intelligent thermostats, energy meter gateway, interactive TV terminal, CATV gateway). To define the interoperability profiles for load management and electro-appliances. To optimise the existing telephone gateway, energy controller and remote configurator to allow full energy control and the reception of data files. To develop new products: electric store heater, water heater, intelligent thermostat and intelligent socket. To test and verify user acceptance in a real environment of the following functionalities: energy management, remote configuration, control and monitoring of the electroappliances, user interface and external communications. Participants HIRCHMANN (A), FAGOR (E), VIMAR (I), VDE (I), ENEL (I), IBERDROLA (E), I. MULAZZANI (I). Contact Point Hirchmann Ges.m.b.H Josef FALLER Oberer Paspelweg 6-8 A-6830 Rankweil Brederis (Austria) Duration 24 months from 02.01.1996 tel: +43 5522 307314 fax: +43 5522 307394 E-mail: josef.faller@telecom.at 4 - 12 4. Peripherals TCS 98 EP 21499 OSIM-AHSII Open and scaleable intelligent metering system for advanced home services II Summary This project, OSIM-AHSII, follows a viability study achieved in EP 9264 OSIM-AHS. OSIM-AHS may be the key to the development of new services, and the aim is to design and realize the building blocks which are needed to establish a communicating architecture between utilities and customer, with a special emphasis on two-way communication with meters and two-way communication with appliances or systems in homes. The first range of products will be energy management oriented, but other applications will come in a second step when the infrastructure provided by OSIM-AHS Systems is available. In the proposed reference architecture, special attention has been paid to the possibility of upgrading the system services and communications means, without big overcharges or equipment modifications. The existence of a large number of customers having, through this architecture, access to information and services through the HS Power Line Connection, will help considerably in the promotion of the HS products, in countries where the participating utilities operate. Objectives The objectives are based on the concept of integrated and interactive home systems: Development, manufacture, and validation of an intelligent process unit (OSIM-AHS), situated at the end users' dwellings, capable of offering energy management services and the communication and interface basic functional blocks for supporting home services. Development, manufacture, and validation of the Concentrator & Communication Switching device (CCS), situated between the customer premises and the central low voltage unit, capable of communicating with several pieces of OSIM-AHS equipment. The use of this CCS device is enhanced by its alternative two-way data telecommunications system: PLC or telephone. Participants ASESA (E); EDP (P); LANDIS & GYR (CH); EDF (F); ALCATEL-MIETEC (B); GDF (F); ENEL (I); EA (UK). Contact Point Roberto TORDABLE Alcatel SESA Calle Einstein 7 (P.T.M), 28760 Tres Cantos, Madrid (España) Duration 26 months from 15.03.96 tel: +34 1 807 79 00 fax: +34 1 807 79 89 E-mail: tordable@alcatel.es 4 - 13 4. Peripherals TCS 98 EP 21667 GAP Gas-based EHS products for existing dwellings Summary GAP will be focused on the development of different technological elements and domestic appliances to be installed in existing dwellings with a double objective. to create a significant number of available EHS power line compatible products, and to consolidate an offer of EHS, gas-based domestic appliances. These objectives will allow for the promotion of new gas applications in the European market. These technological elements (called "EHS Gas Enabler") and domestic appliances are designed to be installed in any existing dwelling. Gas utilities wish to use it in the promotion of domestic gas applications. Objectives To develop a power line, EHS-compatible equipment set, heating programmer, telephonic gateway, thermostat, gas and water sensors, gas and water mains electrovalves, boiler actuator, heating zone valves, security detectors, distress call emitter and intelligent plugs. To use the existing EHS technology in the development of the "EHS Gas Enabler" elements. They will be based on the 80C51 microcontroller family. To produce a lighter version of the EHS specification (called HS Lite) so that it can be implemented in these small pieces of equipment at low cost. HS Lite will be an EHS library that implements a full compliant EHS protocol on Power Line. To develop power line compatible gas appliances: a combined condensation boiler producing heating and domestic hot water, a water heater, a bi-thermal washing machine, and a bi-thermal dishwasher (bi-thermal appliances receive hot water at the required temperature directly from the boiler). Participants INSTITUT CERDA (E), GAS NATURAL (E), GAZ DE FRANCE (F), BRITISH GAS (UK), FAGOR (E), DELTA DORE (I), TRIALOG (F) Contact Point Albert GIRBAL and Xavier PASSARET Institut Cerda Numància 185 4º2ª BARCELONA 08034 (España) Duration 25 months from 01.03.96 tel: +34 3 2802323 fax: +34 3 2801166 E-mail: 100114.3311@compuserve.com 4 - 14 4. Peripherals TCS 98 ESD Best Practice and Cooperative R&D EP 20482 HEARMASTER Advanced Hearing Aid Test Tools in Oticon Summary HEARMASTER is a Demonstration Project which demonstrates the introduction of advanced mixed-signal test techniques and tools in a leading manufacturing company of hearing aids. By introducing modern Digital Signal Processing (DSP) test techniques the envisaged improvement in throughput during testing can be increased threefold compared with the existing system for test. To cater for such improvements a certain amount of tailoring will be needed to comply with the demands of the user. Objectives To achieve a threefold improvement in test throughput with corresponding cost reductions. To achieve easy transfer of results from design verification to production test. To integrate a more user-friendly testing environment. To adapt the prototype tool to the user needs. To increase the vendor confidence in the market for the tool To disseminate the results throughout the community. Participants OTICON A/S (DK), MICROLEX SYSTEMS A/S (DK) Contact Point Niels Ole DALSGAARD Oticon A/S Strandvejen 58 DK-2900 HELLERUP (Denmark) Duration 15 months from 01.12.95 tel: +45 39 17 71 81 fax: +45 39 27 79 00 E-mail: nod@oticon.oticon.dk400.dk 5-1 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20491 SOGROUTE Physical Design Automation on Mixed Semi-Custom Arrays Summary Electronic systems for contactless identification use radio-frequency (RF) and infra-red (IR) transmission techniques to exchange information between a fixed, controlling device and a mobile, controlled device (typically an identification badge). These systems dramatically benefit from integration on a single chip, for economical, reliability and confidentiality reasons. In order to limit costs for medium-volume production, a mixture of full-custom and mixed-mode semi-custom solutions have been selected. Thanks to the availability of new, low-cost, physical design tools for gate arrays and standard cells provided by Snake Technologies (formerly EDA Solutions): GATESNAKE and CELLSNAKE, Prinsys is able to control the whole design flow of the ICs of its systems. Objectives Increase the know-how necessary to design mixed analogue-digital ICs at low cost and fast turnaround through the use of mixed-mode arrays and standard cell methodologies. Acquire a full control of the design process, from system to chip, and from high-level specification to low-level physical design. Take advantage of the advance availability of full-featured, low-cost, physical IC design automation tools from EDA Solutions and Snake Technologies: GATESNAKE and CELLSNAKE. Develop and evaluate a new analogue-digital IC design flow on PC, including tools well known on the market, and newer tools from EDA/Snake. Develop two mixed analogue-digital ICs to be integrated in the next generation of Prinsys products: one is a RF emitter in the range 125 kHz to 6 MHz, and the second is an AM demodulator coupled with a manchester-type decoder. Evaluate typical user expectations for IC physical design tools, and tune functionality and features accordingly. Set up a support and maintenance procedure. Participants PRINSYS (F), EDA SOLUTIONS (F) Contact Point Jean-Noel PREIN PRINSYS SA BP6 2, Impasse des Grès F-78117 Chateaufort (France) Duration 12 Months from 01.10.95 tel.: +33 1 39 56 28 07 fax: +33 1 39 56 20 99 5-2 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20755 EMCPCB Using new concepts to obtain EMC on PCBs Summary At the moment, in the electronic design flow at Siemens there is a connection between design entry and PCB layout as well as between design entry and analog simulation. There is no connection between layout and analog simulation. Higher frequencies and smaller packages combined with new technologies like multi-chip modules, surface mounted technology and others, make traces in the layout an important factor. The main objective is to make a connection between the simulation and the layout. This connection should work automatically and must be easy to use for an electric circuit designer. Within this project the software will be tested very thoroughly, all errors in the software will be reported by Siemens and fixed by Simlab. The simulation results will be used to improve the quality of the product and shorten the development time. Objectives Test and improve Simlab software: Siemens will use the Software “Extract” from Simlab in depth. This assures that the software will be free of errors and user friendly after the project is completed, ready to be sold on the market. Test the link between layout and simulation and optimise it for ease of use by the design engineer. Decrease product development times: Siemens is expecting from these tools, to locate errors in hardware design earlier. This should help cut down on development times and avoid unnecessary redesigns. It is hoped that earlier time-to-market and a competitive advantage will result. Participants SIEMENS AG (D); SIMLAB GMBH (D). Contact Point Siemens AG Dep. ZPL 1 MPP 4 81730 Munich (Germany) Duration 15 months from 01.10.95 tel: +49 89 636 47889 fax: +49 89 636 48100 E-mail: pkaiser@sun001.zfe.siemens.de 5-3 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20816 MISIDESY Closed front to back end mixed-signal ASIC Design System Summary MISIDESY aims to extend the power of analogue-digital design in Europe. The result of the project will be a continuous front-to-back and bottom-to-top design flow tested with real industrial examples that will work with analogue behavioural languages for analogue-digital systems. The latest commercial tools will be tested within the programme. From the advances in the digital field and the rising importance of complex mixed-signal ASICs it follows that what is needed, is to develop analogue design to the level of digital design. What is needed is the establishment of modern methodologies and tools. This will also bring mixed-signal design within the scope of SMEs. Thesys will train selected designers in the new methods, and use an analogue custom design as a demonstrator for design work using an A-HDL system description. Objectives The creation of analogue behavioural models which allow description and simulation of whole system (mechanical components, micromechanical systems, magnetic fields, electrical force, flows, pneumatic behaviour etc.). Standardisation of the analogue behavioural language. Linking different simulators for behavioural simulation and "classical" network analysis; digital simulators for behavioural and gate level simulation and connection with mathematically oriented programs (e.g. A-HDL, HF-Spectre, SPICE, Verilog, VHDL). Creation of models suitable for high level analogue behavioural description which describe precisely the analogue physical reality with all relevant dependencies. Combination of the analogue-digital simulator with effective analysis tools. Links with special simulators e.g. HF simulators, description within frequency domain or filter simulators Hierarchical analogue back annotation between behavioural simulation and layout with VAMPIRE. Participants THESYS GMBH (D); CADENCE GMBH (D). Contact Point Joergen STURM Thesys Gesellschaft fuer Mikroelektronik mbH Haarbergstr. 61 99097 Erfurt (Germany) Duration 18 months from 01.11.95 tel: +49 361 427 6666 fax: +49 361 427 6631 E-mail: joergen@thesys.de 5-4 5. ESD Best Practice and Cooperative R&D TCS 98 ESD 22103 DRIVE Design for Electronic Drive Control Summary Special adapted drives require rapid prototyping, short time-to-market, high design security, and high qualified technical support. The intelligent electronic drive control products of port are designed with DSP for control algorithmic and machine safety. In addition, FPGAs are used to connect power stages and measurement systems and for realising fast communication and logic control. To design new improved products, one task is to evaluate a commercially available development tool set and to use it to improve the design efficiency within a design experiment integrating new state of the art FPGAs with new functions into the motion products of port. Objectives The experiences in designing complex motion control products and high speed industrial communication have shown new requirements in the approach to electronic design. The complex planning of work and resources improves the quality assurance system of port . The new approach to electronic design is a first step to a linked hard- and software databank for control functions. The start of a new motion controller family will be enabled by using a new development tool set with support of mixed hardware/software design. Commercial impacts are expected in various directions; shorter development cycle times, higher quality outputs in electronic system design, predictable results, and re-usability of components for other projects. The goal of the project is very important also for other high technology oriented companies especially in the motion control market, e.g. for easy and fast solution of motion control problems with difficult dynamic properties, short time-to-market by rapid prototyping, and volume dependent cost optimisation of the final product. Participants PORT GMBH (D) Contact Point Duration Mr. Michael SUESS Project Engineer port GmbH Droyssiger Weg 56 D-06188 Hohenthurm (Germany) 18 months from 15.04.96 tel.: +49 34602 33279 fax : +49 34602 33280 E-mail: sue@port.de 5-5 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22105 PARIS Usability Optimisation and Productivity Enhancement of the Integrated Layout Tool PARIS Summary In order to reduce costs and increase the productivity in integrated circuit and system design, the new design tool PARIS was developed and combined with a technology independent layout module generator for the realisation of complex mixed-signal circuits. PARIS will be evaluated in the course of this project by using it in the design of a sensor ASIC. Major aspects of the evaluation will be the optimisation of the user interface, the enhancement of the module generators as well as the streamlining of technology file generation and administration. Compliance of the tool's interfaces with a number of industry standard data formats will be verified by cross-checking the layout and mask data with renowned manufacturers' database specifications. Objectives Speed up the development time and reduce the risk of the introduction of a new CAD tool by achieving a simple and intuitive, yet powerful and flexible, user interface and software structure. Decrease the development cost of ICs by utilising a development tool which is capable of running under a variety of operating systems and hardware platforms, including workstations as well as PCs. Feedback from the participating ASIC design companies to the software developers for user driven optimisation of PARIS with respect to the user's experience and requirements. Improvement of the adaptability of the software to the user's style as well as better understanding of the designer's philosophy and handling practice. Achieve a better market acceptance by cooperation with industrial users and providing a fully evaluated and demonstrated tool in a reference project for potential customers. Participants CISS (A); AISS (D); ASIC (D) Contact Point Klaus JÖSTL CISS - Consulting - Integrierte Schaltungen und Software GmbH & Co KEG Grottenhofstrasse 3-7 A-8053 Graz (Austria) Duration 18 months tel.: +43 316 265 222 fax: +43 316 265 361 E-mail: kj@ciss.co.at 5-6 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22133 SEED Software/Hardware Exploration: A European Demonstration Project Summary The development of an improved design methodology for mixed hardware/software embedded systems with real-time constraints is required for telecom applications. A design flow for this type of application will be developed and tested using a prototype environment developed at COGEFO/CEFRIEL, named TOSCA. This environment allows the user to specify and bind different parts of a design to hardware or software units. A critical control module for telecom applications will be designed exploiting the TOSCA environment, and analyses of hardware and software partitioning will be evaluated. From this design experience, improvements and user requirements will be implemented in the prototype environment. A marketing activity will be activated by the CAD vendor to introduce the design methodology thus identified to other potential customers for possible commercial exploitation. Objectives Design of an improved application in the telecom domain applying the prototype codesign environment TOSCA. A control module of the UT100 public switching exchange system has been selected. Improvement of the prototype tool TOSCA exploiting the industrial experience in system design gained with the application. Development of a design methodology and an integrated design flow for hardware/software mixed applications, considering in particular the phases of system specification and architectural exploration. Dissemination of the results of the project driven by a detailed technology transfer plan, including workshops presentations mainly aimed at SMEs. Exploitation of the engineering knowledge of the CAD vendor in order to gain enough confidence to bring the prototype environment eventually to the market. Participants ITALTEL SPA. (I); COGEFO (I); MENTOR ITALIA (I). Contact point Massimo BOMBANA Italtel spa DRSIT-RSC-SM CLTE Castelletto di Settimo Milanese 20019 Settimo Milanese (MI), (Italy) Duration 15 months from 01.07.96 tel: +39 2 4388 7431 fax: +39 2 4388 8593 E-mail: bombana@settimo.italtel.it 5-7 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22169 ENPROCO Enhanced Processor-Based System for Electronic Control Applications Summary The demonstration project ENPROCO aims to transfer research knowledge on HW/SW codesign, to small-size companies developing embedded systems based on small 8 to 16 bit microcontrollers. The research prototype HW/SW codesign platform CASTLE, developed at GMD, will be adapted and extended to support the specific requirements of such small and medium sized companies. New tools, such as emulators for the special microcontrollers in use there, will be added to the codesign system if required. Objectives Improve efficiency in electronic system design by the early introduction of novel design tools to an industrial partner. Transfer of know-how in design methods and tools to small-sized companies for better productivity and competitiveness. Demonstration of a practical gain in design productivity form advanced ESDA tools. Development of improved products with a shorter time-to-market. Acceleration and support of the adaptation of prototype CAD tools towards viable software products. Documentation of added value in system design through the use of novel tools, thereby preparation of their commercialisation. Demonstration of a possible leap in productivity to European industries with focus on small and medium sized companies. Participants KML ELEKTRONIK (D), GMD (D) Contact Point Edgar PETER KML Elektronik GmbH Hertzstrasse 14 D-53844 TROISDORF (Germany) Duration 24 months from 01.04.96 tel: +49 228 97185- 24 fax: +49 228 97185-33 E-mail: not available yet, may use Holger.Veit@gmd.de 5-8 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22203 VITALISE VXI Industrial Test Applications for Liaison with IEEE 1149.1 System Environments Summary The “Vitalise” project demonstrates the introduction of a new generation of mixed-signal test solutions and test concepts - combined with boundary scan compliant applications - in the development organisation of a leading mobile communication supplier. Objectives to allow for fast prototyping of new subsystem technologies for embedded applications such as the rapidly evolving PCMCIA applications, Multi-Chip-Modules (MCMs), Systems-on-Chip (mainly for telecom and multimedia applications). Participants THOMSON CSF COMMUNICATIONS (F); MICROLEX SYSTEMS A/S (DK) Contact Point Francis PICHON Thomson CSF Communications Rue du Fosse Blanc 66 BP156 F-92231 GENNEVILLIERS (France) Duration 16 months from 01.07.96 tel: +33-1-46-13-29-93 fax: +33-1-46-13-26-73 E-mail: francis.pichon@thomcom.thomson.fr 5-9 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22249 ADTV ASIC Design Transfer Using VHDL Summary With ASIC technology being improved every year, ‘old’ manufacturing processes are phased out and chip designs have to be retargetted to new processes. For applications with a low series production volume, the non-recurring costs of gate array redesign add a significant contribution to the product price. As today cheap FPGAs are available in complexities that were reserved for gate array design some years ago, devices, tools, and methods will be evaluated to transfer from gate array technology to FPGAs for such applications. The tools and methods will further allow a high flexibility in future selection of device types, manufacturers, and technology. Objectives A market survey will be performed to determine which FPGA product family will best suit the model application. A market survey will be performed to determine which design tools will allow a maximum of flexibility and independence of a specific manufacturer and/or ASIC/FPGA product family. Using one sample design, experience shall be gained how to transfer from a gate level description to a VHDL description for the purpose of portability. Evaluating two sets of design tools and two different FPGA product families experience shall be gained on design productivity and efficiency ( design cost, product cost ). Design methods and rules will be determined to ease future retargetting activities. The retargetted design will be simulated to a confidence level allowing a follow-on activity for production implementation. Participants NORD-MICRO AG (D) Contact Point Rainer SCHULZE, E2 Nord-Micro AG Victor-Slotosch-Str. 20 D-60388 Frankfurt / Main (Germany) Duration 15 months from 01.04.96 tel: +49 6109 303 309 fax: +49 6109 303 332 E-Mail: schulze@nm.utc.com 5 - 10 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22253 DEMOMAG Design and modelling improvement of magnetic components for aerospace applications Summary Performance and design process of Switched Mode Power Supplies (SMPS) are improved by means of the improvement of the design, modelling and manufacturing process of the power magnetic components. The influence of magnetic components in high frequency DC/DC converters is critical. Furthermore, the performance of HF magnetic components is very dependent on winging strategy and geometry effects, which are not properly calculated and predicted today. The Magnetic Element Modelling Tool (MEMT), based on Finite Element Analysis calculations, is used to generate accurate frequency dependent behavioural models, useful to guarantee adequate performance and save time in the design and development process of the whole SMPS. Objectives Accurate behavioural models, accounting for geometry and frequency dependent effects are obtained for the SMPS magnetic components. Layers position, sensitivity to track and isolation dimensions, etc., will be calculated with the new MEMT tool. Improvement of magnetic component performance, because the capability to obtain an accurate model before building the magnetic component and the physical insight by means of the Finite Element Analysis allows component optimisation. Improvement of SMPS, because performance of SMPS is highly dependent on magnetic components. Efficiency, stress, size, thermal management, etc, are more accurately calculated since accurate models are available. Improvement of design process: allows performance of electrical simulations and to check whether results are as expected before building magnetic component and SMPS. Development time reduction: design will not be iterative. Iterations will be done by computer, but not in the construction of the magnetic components. Cost reduction: due to the development time reduction and manufacturing cost of low profile PCB transformers, that is lower than hand made transformers when leakage inductance reduction is a must, as in this case. Participants ENOSA (E); UPM (E) Contact points Carmen GUERRA / Julio CEZÓN ENOSA Joaquin Rodrigo 11 28300 Aranjuez, Madrid (España) Duration Jose A. COBOS 12 months from 01.05.96 UPM Jose Gutierrez Abascal 2 28006. Madrid. (España) tel: +34 1 894 88 00 fax: +34 1 892 22 17 tel: +34 1 411 75 16 fax: +34 1 564 59 66 E-mail: cobos@upmdie.upm.es 5 - 11 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22409 EMCLO EMC Design Methodologies for PCB Layout Optimisation Summary The aim of this Demonstration Project is to show the viability of a prototype tool in performing predictive analysis and screening of EMC (Electromagnetic Compatibility) problems on PCB; the extraction, analysis and improvement of critical track configuration and the integration with the design methodology in our company. To prevent EMC compliance from posing a problem at product level, every level of the system from the design of the ground structure, to the selection of ICs and decoupling capacitors, to PCB layout must be considered. EMC problems which cannot be located before the prototype is tested, or, which are ascertained by the service technician at the customer site, create prolonged development cycles, excessive efforts during the testing period and decrease customer confidence due to lack of product quality. Objectives Perform predictive analysis and screening of EMC problems on PCB, the extraction, analysis and improvement of critical track configuration and the integration with the design methodology. Component value and layout optimisation. Product control at each development phase. With more stringent international EMC regulations on the horizon and shortened development cycle, MMDE cannot afford redesigns due to EMC problems discovered just prior to volume manufacturing. Viability of the prototype tool; HDT will cover the EMC market with a unique solution for conducted and radiated emission, a mature prototype proved on a real industrial problem and a tool customised in accordance with final user requirements. Reduction of design iterations; measurement reduction: ie measurement to be taken before manufacture. Promote the use of the defined methodology through publication of "application notes" with the case study. Participants MAGNETI MARELLI ELECTRONIC DIVISION, MMDE (I); HIGH DESIGN TECHNOLOGY, HDT (I) Contact Point Diego LASAGNA Magneti Marelli S.p.A. Research & Development Design Automation Corso G. Cesare 328 - 10154 Torino, (Italy) Duration 9 months from 01.05.96 tel: +39 11 2411315 fax: +39 11 2411330 E-mail: Dlasagna@torino.marelli.it 5 - 12 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22415 GERTRUDE Printed Circuit Board CAD/CAM data Transfer using EDIF Summary GERTRUDE is a Demonstration Project in which high-level electronic data transfer between design systems (CAD) and manufacturing systems (CAM), based on the emerging EDIF Version 4.0.0 data format for PCBs and Multichip Modules (MCMs) will be establsihed and demonstrated. A significant part of the EDIF format has been developed within Europe, supported by Esprit Project ESIP (8370). Objectives Significant reduction in cost for data transfer (20% saving) Significant reduction in time to market for PCBs (from 7 days to 5.5 days) Participants NOKIA MOBILE PHONES LTD (UK); ORBOTECH (B); REDAC SYSTEMS (UK); UNIVERSITY OF MANCHESTER (UK) Contact Point Dominic LOBO Nokia Mobile Phones (UK) Ltd Ashwood House, Pembroke Broadway Camberley, Surrey, GU15 3XD (United Kingdom) Duration 12 months from 17.06.96 tel: +39 11 887 91 25 fax: +39 11 887 90 32 E-mail:dominic.lobo@nmp.nokia.com 5 - 13 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22821 OPTISSIMO Evaluation and Demonstration of the Optical Proximity Correction and Simulation Tool OPTISSIMO Summary OPTISSIMO is a newly developed software tool from AISS for optical proximity correction and simulation in IC manufacturing. Optical Proximity Correction is a novel technique which extends the practical resolution limits of existing optical lithography equipment by at least one IC generation. OPC modifies the design data of an IC to correct for the diffraction phenomena encountered when printing close to the limits of the optical tool. OPTISSIMO is able to do this modification on the data volume of a whole chip in a reasonable time with sufficient accuracy for state-of-the-art ICs. Objectives In this project, Siemens Semiconductor validates and demonstrates OPTISSIMO on real IC designs. AISS receives feedback for the simulation accuracy, for optimisation and for better understanding of any restrictions in the practical application of OPC. So AISS can increase the usability and obtain the best functionality for industrial use of OPTISSIMO. The output of the project will be a commercially available software tool, that reflects the practical needs of IC manufacturing. Reports will describe the experiences with OPTISSIMO and deliver information about best practice for application. For Siemens Semiconductor, this project provides early access to a key technology developed according to the actual needs by an European software company. This opens the possibility for further shrinks of IC design geometries without the investment in next generation lithography tools. For AISS, the cooperation with Siemens provides application results in an industrial environment and a capable and competent partner to guarantee the commercial and technical success of the software package. The results of the project will be published at international lithography and design conferences, as well as in reports to the EC. Participants SIEMENS AG (D) Contact Point Wilhelm MAURER Siemens Semiconductor Group HL ST TE M3 Otto-Hahn-Riung 6 D-81479 MUNICH (Germany) Duration 15 months from 01.11.96 tel: +49 89 63643497 fax: +49 89 63648666 E-mail: wilhelm.maurer.hl.ostc.siemens.de 5 - 14 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22979 YETI Yield simulation and enhancement Tool YETI Summary For the integration of electronic systems in telecommunications, automobiles and consumer electronics the demands with respect to the performance and time-to-market are increasing rapidly. Thus the efficient control of the concurrent engineering processes design, layout and production line performance is of essential importance for the optimisation of the overall function of integrated circuits. Objectives A very important part of the design flow is the design verification to improve the yield. The design and the layout have to be examined not only in the view of minimisation of silicon area used or high speed of the circuit, but also with respect to manufacturability. If we want to generate such robust designs, the existence of parameter variations resulting from unintentional variations in the process parameters must be accounted for. A second issue of design verification is to find weaknesses in the layout. This is especially important for digital CMOS circuits as for a stable production line the yield is limited by functional yield losses (not parametric yield losses). Spot defects occurring unavoidably during the production process limit the achievable yield. AISS Gmbh has developed YETI, a new yield estimation and optimisation tool which assimilates all experience and know-how from research to date. The basis of YETI is the computation of critical areas on the layout level especially for shorts between conducting regions. It enables the choice of different defect models, simulation of process induced layout deformations as observed in manufacturing like over/under etching, rounding of corners, optical proximity effect simulation and both numerical and visual output or results. The evaluation and investigation of YETI by Siemens under industrial conditions for layout characterisation with respect to defect-related yield, compatible with the existing design flow, is the goal of this project. For selected circuits especially sensitive to failure modes caused by spot defects, the new tool will be applied to show how the yield can be calculated in advance and how the layout can be optimised for higher yield. Participants SIEMENS AG (D) Contact Point Susanne GRIEP Siemens Corporate Research and Development Otto-Hahn-Ring 6 D-81739 MUNICH (Germany) Duration 12 months from 01.11.96 tel: +49 89 63641871 fax: +49 89 63641442 E-mail: yield@parl.zfe.siemens.de 5 - 15 5. ESD Best Practice and Cooperative R&D TCS 98 EP 23037 FORSITE FORMAT Software in an Industrial Environment Summary This Demonstration Project will integrate a prototype tool using symbolic timing diagrams as a rigorous graphical specification language into an existing commercial tool (CheckOff). The improved tool will be evaluated through development of a PCI to Memory I/O ASIC. The new tool will allow designers to validate the correctness of an implementation against a design specification without the cost and time needed for traditional simulation. Objectives Reduction of 5 to 15% of engineering costs due to reduced logic simulation. Where use of formal methods prevents a redesign, additional cost savings of up to 30% are expected. Increased value of CheckOff-M software tool product by 20%. Participants SIEMENS AG (D); ABSTRACT HARDWARE LTD (UK); OFFIS (D) Contact Point Dieter WERTH Siemens AG (AUT GT 23) Gleiwitzer Str. 555 D-90327 Nürnberg (Germany) Duration 12 months from 01.11.96 tel: +49 911 895 3020 fax: +49 911 895 3762 E-mail:dieterw@m30x.nbg.scn.de 5 - 16 5. ESD Best Practice and Cooperative R&D TCS 98 EP 24097 PROSAFE Software-supported Prototyping and Real-time Implementation of Intelligent Multisensor-based Safety Control Systems Summary Since classical business areas show saturation effects, the proposed project is expected to strengthen Alcatel’s activities in the development of new strategic market opportunities, such as intelligent information processing products. Alcatel SEL’s interest in participating is related to the introduction of novel design methods for Artificial Neural Network and Fuzzy Logic-based information processing systems and has therefore a strategic dimension. Hence, a next generation prototype software tool will be used for rapid prototyping and fast realisation of a Neural Network-based product for the evolving market of security systems and services. Objectives In the proposed project, the design of an electronic surveillance system for the detection of human intruders into protected areas on the basis of multi-sensor input signals will be demonstrated. Using already simulated neural network-based algorithms, the focus of the proposed Demonstration Project will be on integrated system realisation in one single software environment for all design steps. These include graphical input of the neural network topology, source and DSP program development supported by the tool’s automatic code generation features, system evaluation on the same standardised PCbased platform, and final evaluation of the design process using the DSP-based target prototype system. Expected impacts will be on the minimisation of design costs and timeto-market as compared to traditional design methods. Furthermore, easy maintenance and further improvements of the target system is expected to be supported by future releases of the prototype Design tool. One example will be an improved functionality by tool-supported integration of Fuzzy Concepts into the next version of the surveillance system. Participants ALCATEL (D) Contact Point Michael TROMPF ALCATEL ZFZ/SC Holderäckerstrasse 35 D-70499 STUTTGART (Germany) Duration 13 months from 01.12.96 tel: +49 711 82132281 fax: +49 711 82132335 E-mail: mtrompf@rcs.sel.de 5 - 17 5. ESD Best Practice and Cooperative R&D TCS 98 EP 24268 TACTIC Test Applications concerted for Telecom Industry Challenges Summary TACTIC introduces a new generation of mixed-signal test verification solutions to the Nokia mobile communication division (NMP). This will allow fast verification of new mixedsignal applications by emulating critical analogue functionality of a given mixed-signal IC design and hence allow debugging of test and verification programs before the actual prototype chip is available. Objectives One main objective is to reduce the verification and debugging time associated with new mixed-signal prototype chips by 1-2 months to improve the time-to-market in the fast evolving mobile telephone business segment. Another important aim is to reduce the entire job of creating a test and verification solution for new complex mixed-signal components. This will make the program development effort significantly more efficient and allow the user company to handle even more complex solutions within a reasonable resource. It is planned to show clear improvement with respect to the user’s existing techniques in verification of mixed-signal applications. This will include reductions in test cost (e.g. improved throughput, lower total test costs, etc.). Part of the strategy is also to improve accuracy and measurement techniques such as multitone testing and other DSP based testing methods. Improved transfer of results from the user’s mixed-signal design environment, as well as ease-of-use is an area where significant achievements can be gained. The openness of the system approach taken, promise well for future upgrade, and may prove a major advantage for wider applications. It is planned to make known the results to other industries, not least those of the telecommunication sector. The user and the tool provider will make efforts to have the major results presented at key international events such as the European Design & Test Conference and the International Test Conference. The tool provider will also through sales efforts and dedicated seminars, be involved in dissemination. Seminars as part of the FUSE program could bring the results to a broad range of beneficiaries. Participants NOKIA MOBILE PHONES (SF) Contact Point Tapio KOIVUKANGAS Nokia Mobile Phones - IC-Technology Elektronilikkatie 10 FIN-90571 OULU (Finland) Duration 16 months from 01.01.97 tel: +358 10 5057448 fax: +358 10 5057303 E-mail: koivukangas@nmp.nokia.com 5 - 18 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20378 FASTTRACC Formal Analysis and Specification Tools to Realise Adaptive Cruise Control Summary FASTTRACC is an Application Experiment in which Lucas will undertake the design of a safety critical automotive component using the formal methodology and tools from AHL. Safety-critical systems are becoming more complex and more common-place. There are as yet few tools which address the issues of ensuring that a specification is both well-founded and implementable. One tool which has recently appeared on the market and which addresses the issues of safety-critical design is the LAMBDA tool from AHL. It is likely that as complexity continues to rise, standards authorities (e.g. Def Stan 00-55) will mandate the use of tools such as LAMBDA as best practice for the design of safety-critical systems. Objectives To assess the applicability of using mathematically formal techniques (LAMBDA) in the design of an adaptive cruise control system for an automobile. To improve the design efficiency in terms of shorter design cycle and higher design integrity. To allow re-usable designs through use of design history feature. To disseminate the results throughout the community. Participants LUCAS APPLIED TECHNOLOGY LTD (UK); ABSTRACT HARDWARE LTD (UK) Contact Point Karen HALE Lucas Advanced Engineering Centre Dog Kennel Lane, Shirley, SOLIHULL B90 4JJ, (United Kingdom) Duration 12 months from 01.01.96 tel: +44 121 627.35.90 fax: +44 121 627.35.84 E-mail: kgh@lishirl1.li.co.uk 5 - 19 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20385 MLS Design of an Interface ASIC for RISC systems using a VHDL based "Independent" Environment Summary This Application Experiment has as its main objectives the utilisation of VHDL, the use of an "Independent" Environment and the adoption of an advanced design methodology in order to improve the standard of design practice currently used by MLS Firmware S.A (OrCAD & ViewLogic EDA Tools). The Application Experiment will focus on the design of an advanced interface ASIC for the R4000 RISC family of IDT microprocessors that is used in high-performance embedded control systems i.e. fast telecommunications switching, high-speed networking (ATM switches) etc. The product will be tested with advanced prototype testing methods. The ASIC design will be carried out by MLS engineers with the support of INTRACOM engineers to ensure that the end-user learns sufficiently to repeat the process in the future without support. Objectives The adoption of an advanced design methodology with the use of VHDL and the design of an interface ASIC for the R4000 RISC family of IDT microprocessors. MLS plans to design this ASIC in collaboration with the Centre of Microelectronics of INTRACOM (CEM). CEM will provide the advanced design practice, the training of MLS engineers, the final Mentor Graphics platform environment and will do the final technology choice as well as supporting the implementation of the ASIC. To strengthen MLS' position in the embedded control systems market and in the prototype development work. To disseminate the results of this Application Experiment on a European-wide scale. Participants MLS FIRMWARE SA (GR) Contact Point Dr Nikos ZISSIS MLS Firmware S.A. Alex Papanastasiou St. 34 GR-54639 THESSALONIKI (Greece) Duration 15 months from 01.10.95 tel: +30 31 845845 fax: +30 31 868912 E-mail: zissis@compulink.gr 5 - 20 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20388 SYNC High level synthesis of a remote I/O for a Numerical Control system Summary The object of this Application Experiment is a full and practical test for assessing the actual advantages to be obtained by a small enterprise in using a modern (and very expensive) automated synthesis tool (SYNOPSYS) for the design of electronic systems based on fullprogrammable devices. The experiment is based on the complete design of a family of modular units for actuating a variety of I/O devices interconnected with a fibre optic link. Objectives Introduce a new and up-to-date design technology which, to a previous analysis, did not appear to be economical for a small enterprise. Compare the cost of design of electronic modules using traditional methods and a high level automated system. Improve the quality of electronic design with the use of automatic simulation and timing analysis. Increase the competitive position of the company by the reduction of time-to-market of new products and more modular structures in the products. Analyse the time required to prepare all necessary tools (hardware and software) to make the board testable on automatic testing machines in production. Increase the productivity of designers allowing them to concentrate on system functionality described as an algorithm rather than in terms of circuits and gates. Participants SELCA SPA (I); POLITECNICO DI TORINO (I). Contact Point Piero POMELLA Selca S.p.A Corso Vercelli 123 IVREA 10015 (Italia) Duration 15 months from 01.10.95 tel: +39 125 614423 fax: +39 125 251497 E-mail: p.pomella@selca.it 5 - 21 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20413 HARCODA Hardware realisation of communication coding algorithm Summary An innovative design and development environment is to be introduced using advanced EDA software tools. The new design process solution will be used for the development of an electronic system for use in data communication for the purpose of data security and integrity. The heart of the system will be an ASIC designed to realise a coding algorithm. Benefits of using advanced ESD tools will be disseminated to specific industrial sectors. Objectives Introduction of an evolutionary system development cycle based on concurrent engineering principles, replacing the existing traditional electronics design chain. Minimising development time through the use of the new design methodology will reduce product cost and improve quality. Demonstration of the improvement in the design practice through the design of a high complexity ASIC. Targeted dissemination of activities to the Greek Electronics Industry. Participants ECON INDUSTRIES SA (GR) Contact Point John SPANOUDAKIS ECON INDUSTRIES S.A. P.O. Box 60, 19003 Markopoulo, (Greece) Duration 18 months from 01.10.95 tel: +30 299 23831 fax: +30 299 23830 E-mail: jospan@econ.ath.forthnet.gr 5 - 22 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20455 QESDI Quantification of ESD Economic Impact for SMEs Summary This Application Experiment focuses on the use of advanced CAD tools. It is concerned with the design of an advanced model of an electronic cash register, a hot-line product of M&S HOURDAKIS SA, a Greek SME electronics manufacturer. The objectives of the project are to improve design efficiency through the application of the new tools to the design of an improved product. Objectives To achieve a higher degree of integration. To achieve a higher degree of manufacturability. To achieve a higher degree of reliability of designs To disseminate the results throughout the community. Participants M&S HOURDAKIS SA (GR) Contact Point Constantine MOUZAKIS M&S HOURDAKIS SA Industrial Area Koropi Nomos ATTIKIS GR-19400 KOROPI (Greece) Duration 11 months from 01.01.96 tel: +30 1 662.40.43 fax: +30 1 662 27 86 E-mail: mshou1@leon.nrcps.ariadne-t.gr 5 - 23 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20509 STAY ON ASIC Solution for Dedicated TV Camera Summary A dedicated, compact and cost-effective TV camera is to be designed for use in an Optical Character Recognition (OCR) subsystem as well as in a remote surveillance system. It must therefore be capable of performing pattern recognition and motion detection functions. ASIC technology has been selected to achieve the best price-to-performance ratio. Most of the image analysis functions are performed by the ASIC now in development and the complete system just requires few very low cost components other than the microprogrammable ASIC itself to do the required job. Objectives That the OCR under development can readily perform static image acquisition; it is simple and reliable and its production price can be very competitive in comparison with already available similar devices. That the ASIC itself can be profitably used in other planned products that require image analysis, such as a surveillance TV camera or a digital remote TV camera connected to the control monitor via a telephone line. The acquired microelectronic experience is to be transferred to other products, leading to enhanced performance and substantial savings in production cost. Participants METALPLEX SPA (I); EDELPRO SRL (I). Contact Point Cosimo LA RAGIONE Metalplex SpA tel: Duration 12 months from 01.011.95 +39 824 350204 5 - 24 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20548 SEM-A-HDL Smart Energy Meter design using novel CAD tools that support Analogue HDL modeling techniques Summary The aim of SEM-A-HDL is the comparison of the conventional way of implementing the Smart Electronic Energy Meter with the outcome of the Application Experiment: the same device design completed (at the behaviour level) using A-HDL based methodology. The most important goal is the exploitation of novel modelling techniques based on A-HDL (extension of VHDL for the analogue case) through modern CAD tools. The experiences accumulated during the development of the Smart Energy Meter will be valuable both for the user company for all their future mixed-signal products, as well as for all interested SMEs and Design Houses including the subcontractor. A parallel goal (supported by company resources) is the development of a Smart Electronic Energy Meter, an efficient solution that overcomes the constraints of the old Ferraris-type electricity energy-meter. Objectives To efficiently design a Smart Electronic Energy Meter device which will overcome the constraints of the old Ferraris-type one, and will provide advanced services like fraud detection, multi-tariff capabilities, two alternative ways of communication for the transmission of billing and status information etc. To introduce and exploit novel modelling techniques based on A-HDL in mixed designs . To demonstrate through efficient execution of the specific experiment the improvements that could be achieved in mixed hardware designs by employing the project’s emerging techniques and tools with respect to existing ones, in terms of better modelling, more reliable design procedures, reduced errors and redesign cycles and shorter time-to-market. To disseminate the experiences and lessons learned, through the execution of the specific experiment, in digital/analogue designs to SMEs and other interested bodies. Participants INTRACOM SA (GR) Contact Point Dimitris DERVENIS INTRACOM S.A. 19,5 km Markopoulou Ave 19002, Peania, Attika (Greece) Duration 18 months from 01.11.95 tel: +30 1 6860456 fax: +30 1 6860312 E-mail: dder@intranet.gr 5 - 25 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20605 PCASIC Personal Computer tools for the design of Application Specific Integrated Circuits Summary PCASIC is an Application Experiment which aims to provide FINT with experience with state-of-the-art design methods in digital microelectronics and establish a safer design route with minimum risk of reruns on developed ASIC designs. Objectives To establish a Best Practice design methodology within FINT in order to provide better products and to bring these products quicker to the market with a higher degree of success. To establish a design practice using VHDL. Evaluation of use of VHDL as a suitable tool for a small size company with minimal experience in high level description of design. The design time and efficiency of the design will be compared with schematic design tools. It is further aimed to establish a design practice using FPGA as a development and test tool before the final implementation is done in ASIC. The design will be functionally tested using FPGAs. The library-modules are different for the two technologies and the intention is to work in different design environments in the two cases. The main results expected are tools and experience in using such tools that allow FINT to develop products with a higher degree of functionality with a faster and safer design time. Experience will be acquired in design time and in design efficiency in terms of design errors and how this is affected by the design tools. These experiences will be shared with other companies through the Norwegian IT Industries Technological Fora and through presentation at relevant workshops such as the CAD Forum. Participants FIELDBUS INTERNATIONAL AS (N); SINTEF (N) Contact Point Jan Roar REMØY Fieldbus International AS P.Box 107 Blindern 0314 Oslo (Norway) Duration 16 months from 01.10.95 tel: + 47 22 06 73 19 fax: + 47 22 06 73 20 E-mail: Jan.roar.remoy@fint.no 5 - 26 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20702 EESD Enhancement of Electronic System Design by EMC Adviser System Summary The EESD project aims to improve the HWDC (hardware design cycle) by integrating a method of handling EMC (Electromagnetic Compatibility) problems as early as possible in the design and implementation phases. For the improvement of design efficiency, the proposed method deals with rule-based EMC evaluation. Bizerba expects to integrate the commercial EMC Adviser tool into the HWDC to avoid any costly, time-consuming and EMC-induced redesigns of the products. This is an essential prerequisite for expediently translating the developments into products ready for the market. These expected benefits result in a significant competitive advantage, especially in relation to Far East and South East Asian producers. Objectives Higher hardware quality Quantifiable EMC quality control: A design integrity meter is used to graphically show if the hardware system design conforms with EMC requirements. Reduced development cycles (= costs) and increased competitive advantages: Backed up by EESD procedure, the new finished products can be launched and placed on the market much faster, having a positive effect on customer response and product acceptance. Easy handling of EMC Adviser tool: The handling of the tool is easy to understand, the more so, as a rule-based Expert System is used in lieu of customary simulators. Enhanced motivation and increasing productivity/profitability: As the planning of project sequences improves and results are fairly predicted, the design engineer and associated staff become more highly motivated. Iterations after the testing phase are avoided. Participants BIZERBA GMBH & CO. KG (D) Contact Point Werner SAUTER Bizerba GmbH & Co. KG Department TE-BS-H, Post box 10 01 64 72301 Balingen (Germany) Duration 13 months from 01.09.95 tel: +49 7433 12 2204 fax: +49 7433 12 2841 E-mail: wsauter@bizerba.de 5 - 27 5. ESD Best Practice and Cooperative R&D TCS 98 EP 20883 PODSIM ISDN simulator pod supporting multiple S2M links Summary This Application Experiment concerns the redesign of an ISDN pod for advanced test equipment, to support multiple S2M links. V5.2 systems can use up to 16 S2M interfaces between the Access Network and Local Exchange, and a simulator must be able to handle this in order to test these systems in their maximum configuration. Signalling system number 7 exchanges share their message load over several links, and over a maximum of 4 channels within each link. This is beyond the current capabilities of any test system thus making a qualitative assessment impossible. Objectives The increased demands of a primary rate system in terms of both processing power and I/O bandwidth will require a far more sophisticated design tool than was used for the original system. The new design environment should offer the following advantages : integrated solution covering all aspects of the design process from circuit/schematic entry and analogue and digital simulation/analysis large component libraries and the ability to import standard descriptions (e.g. VHDL) integrated ASIC design capabilities support for future enhancements and technological changes The use of modern design tools and methods will have a direct impact on the cost and quality of the electronic products designed and developed by the company as well as in other factors (time-to-market) which determine company's place in the market. The direct benefits expected could be summarised in cost reduction, improved product quality and shorter timeto-market. Participants SKELTON GMBH (D), ITC SA (GR) Contact Point Duration Grigoris DOUMENIS SKELTON GmbH Mitltlerer Pfad 26 70499 Stuttgart (Germany) 18 months from 01.10.95 tel: +49 711 1389830 fax: +49 711 8661240 5 - 28 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22106 PLUTO Reduced Design Time using PLUTO Demonstrator Vehicle Summary PLUTO is an ESD Application Experiment in which Toucan Technology Ltd will introduce new design tools into their ASIC development process. The key commercial impact will be the development of a quicker and more cost effective development process that will enable the delivery of competitive products in a timely manner. Objectives The overall goal of the Application Experiment is to reduce the design time for ASIC based products by 20%. Measurable improvment is expected in the following design process metrics: Overall development time Overall documentation time RTL and Gate level simulation time Number of test cases Gate/RTL test coverage ratio Participants TOUCAN TECHNOLOGY LTD (IRL) Contact Point Aedan COFFEY Toucan Technology Ltd Galway Technology Centre Mervue Industrial Estate, Galway (Ireland) Duration 12 months from 15.03.96 tel: +353-91-757223 fax: +353-91-755635 E-mail: coffey@toucan.ie 5 - 29 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22342 VSDSE VHDL-based System Design and Simulation Environment Summary In this Application Experiment a hardware design environment for hardware is to be established for complex PLDs as well as ASICs and PCBs using the same advanced topdown methodology, the same tools and similar flows in the system design before the implementation phase. VHDL which is an international standard was selected to form the basis of the work to be done. The design environment planned will enable us to perform VHDL-based board and system simulations in an early stage of product development. Objectives A model of the system under design is to be created before the implementation phase by using only VHDL models and a special component library (SmartModels). Verification of the functionality of the new system design is to be done only by using a VHDL simulator and component libraries (VHDL and SmartModels). No traditional gate simulator will be used. Special methods are to be introduced into the system testbench for automating the simulation process and result analysis and therefore improving the efficiency of development work. Design risks will be minimised, as decisions on architecture can be verified in a rather early stage of the design process. An earlier failure detection and shorter iteration loops will lead to shorter design periods. Verification of functional operability of the system to be designed by simulation will reduce the time needed for putting it into operation. Participants SNAT (D). Contact Point Michael SZENGEL Siemens Nixdorf Advanced Technologies GmbH Scharfenberger Straße 66 D-001139 Dresden (Germany) Duration 15 months from 15.03.96 tel: +49 351 844-2316 fax: +40 351 844-2067 E-mail: szengel.drs@sni.de 5 - 30 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22408 ECU Design and Product Development of New Generation of ECU Summary Products designed for automotive applications must undergo an extensive and time consuming testing program. This, together with the relative short life of the vehicle models, imposes a number of constraints on the length of time allowed between the conception of the idea and the starting of the production activity. The objective of this Application Experiment is to reduce the concept-to-market time introducing a design methodology which allows the designer to test and verify his work as early as possible in the design process. The standards of quality, reliability, performance, and cost can be attained only if the products are designed, from the very beginning, with these objectives in mind. Objectives Reduction of time to market Reduction of product development costs Introduction of new technologies Participants MAGNETI MARELLI S.P.A. (I). Contact Point Maurizio CATENA MAGNETI MARELLI Electronics Division Viale Carlo Emanuele II, 118 10078 VENARIA REALE (TORINO) (Italy) Duration 16 months from 17.06.96 tel: +39 11 887 91 25 fax: +39 11 887 90 32 E-mail: catena@torino.marelli.it 5 - 31 5. ESD Best Practice and Cooperative R&D TCS 98 EP 22818 MCC Design of Motion Control Chip Summary The Application Experiment is TRINAMIC’s entry into the field of ASIC design. TRINAMIC’s know-how from the development of a range of microcontroller based stepper motor controllers will be used to design an advanced single chip stepper motor controller (MCC). The MCC will be implemented as an ASIC in co-operation with the University of Hamburg using state-of-the-art Cadence DFW-II chip development tool chain which has been in use at the university for several years. Objectives Acquisition of knowledge in VHDL standard language for hardware specification, synthesis and documentation. Reduction of design time from between 6 to 30 weeks down to 2 to 10 weeks. Improved testability reducing failure rate to 25% of current value Improved reliability and functionality together with 20% reduction in cost. Participants TRINAMIC ELECTRONIC SYSTEM DESIGN GMBH (D) Contact Point Dr Michael RANDT TRIANAMIC Electronic System Design GmbH Preystrasse 14 D-22303 HAMBURG (Germany) Duration 12 months from 01.10.96 tel: +49 40 270 921 73 fax: +49 270 921 77 E-mail:100327.254@compuserve.com 5 - 32 5. ESD Best Practice and Cooperative R&D TCS 98 EP 23051 VMUSB VHDL Model of Universal Serial Bus to ISA Bus Adapter Summary This Application Experiment will lead to improved design methodologies and personal skills equivalent to the current state-of-the-art techniques. These will be achieved during the course of developing a VHDL model of a universal serial bus to industry standard architecture bus interface. The main result will be new skills in VHDL and analogue design methodologies plus an improved product. This will enable the company to maintain its market edge as a producer of single chip solutions for computer peripheral interfaces. Objectives Acquisition of a library of components some 50% of which would be re-usable in future designs. A reduction of 50% in design time which is currently taking 4 to 5 months. A 25% reduction in the time-to-market currently running at 6 to 8 months. Participants SHUTTLE TECHNOLOGY LTD (UK) Contact Point David BRADLEY Shuttle Technology Ltd Alba House, Mulberry Business Park Wokingham RG41 2GY, (United Kingdom) Duration 12 months from 15.08.96 tel: +44 1189 770 441 fax: +44 1189 771 709 E-mail:davidb@shuttletech.com 5 - 33 5. ESD Best Practice and Cooperative R&D TCS 98 EP 23104 CATG Coverage Analysis and Test Generation Summary This Application Experiment will measurably improve the efficiency and quality of functional fault coverage of highly complex systems on Silicon. The VHDL Cover tool will be integrated into the existing design flow. The tool will be exercised and evaluated during application to the design of the Chameleon family of 64-bit microprocessors offering highly integrated software-based solutions thereby supporting flexibility in the end application. Functional verification is estimated to take between 30 and 50% of the design resource for typical microprocessor development. The expected impact from the experiment will be improvements in the efficiency and quality of functional coverage of these highly complex systems on Silicon. Objectives Reduction of manual overhead in coverage analysis to 25% of its current value. Reduction of machine time to perform VHDL statement coverage to 75% of current value. Add ability to generate branch, condition, path triggering and signal coverage to existing ability. Participants SGS-THOMSON MICROELECTRONICS LTD (UK) Contact Point Michael BARTLEY SGS-Thomson Microelectronics Ltd Aztec West 1000 BS12 4SQ BRISTOL, (United Kingdom) Duration 12 months from 28.11.96 tel: +44 1454 611 464 fax: +44 1454 617 910 E-mail:bartley@bristol.st.com 5 - 34 5. ESD Best Practice and Cooperative R&D TCS 98 EP 23181 OSSWLAN Optimized Spread Spectrum Wireless - LAN Summary The main objective of this project is the experimental use of state-of-the-art design tools in order to upgrade and enhance the electronics and ASIC design process, and more specifically to re-design a WLAN transceiver. Objectives STS expects the project to result in a reduction of design time, time-to-market and the cost of design as well as an improvement of quality in terms of increased effectiveness and decreased faults/defects. At the same time, the adoption of advanced design tools is expected to offer STS staff members the opportunity to gain useful experience with the help of such electronic development tools. The anticipated impact of the experimental project in question is that STS, as “idea and prototype factory”, will become capable of a more rapid and effective/efficient realisation of ideas, which will benefit STS considerably. In commercial terms, one could argue that the ability to demonstrate a simulation at an earlier stage of development will make it more likely to attract, convince, inspire confidence in potential clients, production and marketing partners and in doing so achieve their business commitment. Dissemination of the project’s results to a wider community will take place in various ways, i.e. contribution to national and international workshops, participation in presentations and preparation of articles for international / European magazines. Participants STS-SMART TELECOM SOLUTIONS (NL) Contact Point Hans VAN LEEUWEN STS-Smart Telecom Solutions Keizersgracht 298 NL - 1016 EW AMSTERDAM (The Netherlands) Duration 12 months from 01.10.96 tel: +31 20 4204200 fax: +31 20 4209532 E-mail: 100276.1177@compuserve.com 5 - 35 5. ESD Best Practice and Cooperative R&D TCS 98 EP 23237 CORE Core Processor Implementation for ADSL Telecom Applications Summary The main objective of the action is to investigate and do a feasibility on the improved utilisation of state-of-the-art tools (i.e. Virtuoso tools from Eonic Systems) to allow run-time support with core microprocessors for HW/SW codesign system-on-silicon implementations. Objectives Expected results: real-time operating system tools are nowadays usually applied for software implementations on fixed pre-defined board level architectures. The main result that can be expected of this project will be the proof that these functionalities can be used as well for HW/SW co-designs making use of embedded cores (e.g. ARM7), and that they can be encapsulated in a global system design and synthesis flow. Expected impact of results: the major impact of the project results will be that the utilisation of the Virtuoso run-time support tools with ultra-fast switching times can be extended from software implementations on fixed pre-defined board level architectures towards HW/SM co-designs with embedded cores (ARM7 in this project). This will allow other users to benefit from the establishments. For the user company itself, the feasibility study in this project can lead to an improved design efficiency and a higher design quality, for the ADSL application specifically but also for future applications. Participation and contribution to open international workshops and/or conferences in the target area will be planned, at mid-term and at completion of the project period, to transfer the expertise and benefits of this project to other companies. Actions will be prepared by the tool vendor to facilitate the usage of their tools in future design flows, and to disseminate the expertise gained from this application experiment through their commercial contracts with other European companies. Since the activities of this project are really innovative but in line with the major trends in electronic system design, the potential for replication of the outcome of this project to other companies will be sufficiently high, and new research activities can be started-up. Participants ALCATEL BELL (B) Contact Point Marc GENOE Alcatel Bell N.V. Microelectronics F. Wellesplein 1 B-2018 ANTWERPEN (Belgium) Duration 12 months from 01.10.96 tel: +32 3 240 71 96 fax: +32 3 240 99 47 E-mail: genoem@sh.bel.alcatel.be 5 - 36 5. ESD Best Practice and Cooperative R&D TCS 98 EP 25558 PASCALE Parasitic Substrate Coupling Analysis by Layout Extraction Summary The principle objective of the project is to contribute to better predictability of IC behaviour and hence reduce the number of re-design iterations due to substrate coupling by providing an industrial computer substrate coupling modelling and analysis software to semiconductor companies. This project will contribute to the development, intensive test and enhancement of LAYIN, a complete CAD package designated to parameterizing, modelling and analysing parasitic crosstalk related to the substrate of integrated circuits. Starting from a functional netlist, from the IC layout and from a description of the technology, the software extracts the parasitic substrate model of the IC, completes the simulation data files, and displays the substrate noise distribution. It will include a parameterization tool to create technology descriptions from actual fabrication process data. Objectives Development of a Technology Characterization Tool (TCT) to generate the technology description from fabrication process data via Graphic User Interface (GUI). GUI dedicated to the pre- and post-processing of the data required by the stand-alone tools. The GUI, initially developed as a stand-alone tool, will be integrated into the Layout Editor of Cadence Design Systems. Stand-alone UNIX tool to extract a surface model of the substrate necessary to visualise noise distributions, as well as a macromodel compatible with SPICE and ELDO simulators. Stand-alone UNIX tool to generate CIF representations of substrate noise distributions from surface models. Development and test of dedicated demonstrators and test cases by the Users. Participants SNAKETECH (F), ATMEL ES2 (F), C.I.S.S. (A), EPFL (CH), ERICSSON (S), GEC-PLESSEY (UK), SGS-THOMSON (F) Contact Point Michel OGER, Snake Technologies s.a.r.l Place de la Chaffardière, F-38620 , St Geoire en Valdaine, (France) Duration 18 months from 01.07.97 Tel: +33 476 07 65 05 Fax: +33 476 07 10 67 E-mail: michel.oger@snaketech.com 5 - 37 5. ESD Best Practice and Cooperative R&D TCS 98 EP 26698 SIFGEN Software Interface Function Generator Summary The project will deliver an improved method, with supporting tools, for the development of low level embedded software. By using advanced automatic code generation techniques to produce all low level, hardware related functions, the programmer can significantly reduce development time. The tools shall provide the user with intelligent support, providing the capability to quickly and accurately enter all of the programmable information associated with a given embedded microprocessor system. From this database of information the user shall then be able to automatically generate a library of low level Software Interface Functions (SIFs), designated Level 1 SIFs, which constitute a uniform layer of abstraction away from the embedded system hardware. This Level 1 SIF layer provides a clean interface on top of which system software can be built. In addition, the tools shall also provide the user with the capability to combine Level 1 SIFs, to form Level 2 SIFs, thus providing yet another layer of software abstraction from the hardware system. To improve the process of writing software, the libraries of Level 1 & 2 SIFs will be accessible to the user via a text editor, for direct placement into a source code program. Objectives Develop a method for rapidly developing low level embedded software. Provide a suite of intelligent tools to support the method. Demonstrate the tools in operation. Reduce user development time & effort for low level embedded software. Participants GEC-PLESSEY SEMICONDUCTORS (UK), ETNOTEAM (I), R&C (UK) Contact Point Colin TATTERSALL GEC Plessey Semiconductors Tamerton Road, Roborough, Plymouth,UK PL6 7BQ Tel: +44 1752 693344 Fax: +44 1752 693306 E-mail: Colin.Tattersall@gpsemi.com Duration 10 months from 01.01.1998 5 - 38 5. ESD Best Practice and Cooperative R&D TCS 98 Design Clusters EP 25213 TARDIS Design Clusters: Technical Coordination and Dissemination Summary The Design Clusters action aims to foster excellence in design skills, and to bring these skills to broad industrial use. Design Clusters are co-ordinated sets of design experiments comprising research and best practice work. Cluster themes currently addressed are Low Power Design and Mixed Signal Design, coordinated by DIMES and CNM respectively. The specific goals are: Low Power Design: design methods for reducing the power consumption of electronic circuits. Mixed Signal Design: design methods for solving problems related to integrating analogue and digital functions on a single device. 19 design experiments were launched at the end of 1997; additional experiments are planned. Capturing and dissemination of their gathered knowledge and experience to third parties is organised through the TARDIS project by the cluster co-ordinator with the support of design experiments. Objectives To organise the communication between design experiments and to exploit their potential synergy; To guide the capturing of methods and experiences gained in the design experiments; To organise and promote the wider dissemination and use of the gathered design knowhow and experience. Participants TECHNICAL UNIVERSITY OF DELFT/ DIMES (NL), CNM (E), PARTICIPANTS OF ALL DESIGN EXPERIMENTS Contact Point Dr. Rene VAN LEUKEN, DIMES Design and Test Centre H16 CAS Mekelweg 4, NL-2628 CD Delft, The Netherlands Duration 42 months from 16.07.97 Tel: +31 15 278 66 96 Fax: +31 15 278 75 64 E-mail: rene@dimes.tudelft.nl Cluster Homepage: http://www.ddtc.dimes.tudelft.nl/ESD-LPD 6-1 6. Design Clusters TCS 98 EP 25242 PREST Power REduction for System Technologies Summary In this programme the partners will study, develop and demonstrate techniques for Low Power / Low voltage IC operation with the aim of reducing typical system power demand by a factor of ten through the application of new circuit design techniques and supply voltage reduction on an advanced bulk CMOS process. The work will concentrate on the digital circuits identified as the main areas of current consumption in GSM personal communications integrated circuits (specifically the GPS GEM series chip-set) with the aim of raising the mobile phone performance to 1000 hours standby and 10 hours talk time between re-charging. Current systems are achieving around 100 hours standby and 2 to 4 hours talk time depending on the distance from the base station. Objectives Survey and Report on contemporary techniques for Low Power Design Survey and Report on commercial power analysis software tools Report on Architectural design techniques with a power consumption comparison Report on Algorithmic design techniques with a power consumption comparison Report on Asynchronous design techniques and Arithmetic styles Produce description of low-power design flow Fabricate and characterise demonstrator to assess the most promising power reduction techniques Participants GEC PLESSEY SEMICONDUCTORS (UK), UNIVERSITY OF MANCHESTER (UK), QUEENS UNIVERSITY, BELFAST (UK) & UNIVERSITY OF SHEFFIELD (UK). Contact Point Denzil BROADHURST, GEC Plessey Semiconductors MicroElectronics Centre Hollinwood, Oldham OL9 7LA (United Kingdom) Duration 24 months from 01.11.97 Tel: +44 161 684 4025 Fax: +44 161 688 7898 E-mail: denzil.broadhurst@gpsemi.com 6-2 6. Design Clusters TCS 98 EP 25248 LOVO Low Output VOltage DC/DC converters for low power applications Summary This Design Experiment addresses new design methodologies that will contribute to a significant decrease of power dissipation in electronic equipment by decreasing the power consumption and dissipation of the DC/DC converters feeding low power electronics. New low power systems mainly require low supply voltage. However, the lower the output voltage the lower the efficiency of the DC/DC converter. This is a very important drawback because size of the power converter is highly dependent on the efficiency, and furthermore, the ratio volume/watt in DC/DC converters is higher and higher as the output voltage is reduced. Therefore, it could be the case that future low power integrated circuits could be really small, and on the contrary the converter that feeds it would be a bulky and inefficient one. The experiment consists of checking the feasibility of new approaches to design and manufacture DC/DC converters generating very low output voltages (< 3.3 V), required for such applications. The main features are: very low output voltage: 1.5 V output power: 15 W very high efficiency (>85%) in an industrial application within the Telecommunication sector; low volume (size lower than 25x25x10 mm3); low cost (< 10 ECUs). Objectives Development of technical solutions for the power supplies of advanced low power systems, comprising the following topics, New methods for synchronous rectification for very low output voltage power converters; Analysis of techniques for high density of integration; Analysis and validation of new components; Functional demonstrator close to commercial specifications. Participants ALCATEL (E), UNIVERSIDAD POLITÉCNICA DE MADRID (E) Contact Point Enrique DE LA CRUZ Alcatel España S.A. Ramirez de Prado 5, 28045 Madrid, (Spain) Duration 15 months from 01.07.97 Tel: +34 1 330 4693 Fax: +34 1 330 5060 E-mail: delacruz@alcatel.es 6-3 6. Design Clusters TCS 98 EP 25249 AMIED Asynchronous Low-Power Methodology and Implementation of an Encryption/Decryption System Summary The aim of the project is the development of a low-power encryption/decryption circuit for data transmission systems. The portability of these systems requires a drastic decrease of their power consumption. The International Data Encryption Algorithm (IDEA) was selected, which is one of the most powerful algorithms today. A fully asynchronous ASIC implementation of the IDEA algorithm will be developed, which is expected to operate at frequencies up to at least 25 Mbits/sec. An advanced low-power design flow will be established on the basis of commercially available CAD tools, which can be used also for similar data processing applications. The main effort will be spent on the algorithmic and architectural design levels, with emphasis on asynchronous design methodology. The reduced power consumption of the asynchronous implementation will be demonstrated by comparison with a synchronous version. It will be tested in two products with different bit rate requirements. Hellenic Aerospace Industries will use the circuits in new versions of their mobile communication products. The asynchronous design methodology and techniques will be made available to other European companies. Objectives Implementation of the IDEA encryption/decryption method with drastically reduced power consumption; Advanced low power design flow with emphasis on algorithm and architecture optimisations; Industrial demonstration of the asynchronous design methodology based on commercial tools. Participants HELLENIC AEROSPACE INDUSTRY (GR), UNIVERSITY OF PATRAS (GR) Contact Point Dr. Vasileios TZERMPINOS Hellenic Aerospace Industries R&D Division P.O. Box 23 320 09 TANAGRA (Greece) Duration 24 months from 1.12.1997 Tel. +30-262-52 537 Fax +30-262-52 170 email hai51@haicorp.com 6-4 6. Design Clusters TCS 98 EP 25256 LPGD A Low-Power Design Methodology/Flow and its Application to the Implementation of a DCS1800GSM/DECT Modulator/Demodulator Summary A top-down design methodology/flow is proposed for power reduction, emphasising on optimisations at the algorithmic and architectural levels with respect to area, time and power. The design flow includes global and local power optimisation techniques and transformations at each design level. At the algorithm level, alternatives are explored in respect of locality, complexity, parallelism, and loop transformations. At the architecture level, the switching activity problem of modules and their interconnections is reduced by techniques like power-down, memory management, clock distribution, and data representation in relation to the statistical features of input signals. At the logic level, further power optimisation may be achieved by reducing the switching activity of the nodes of a logic circuit, by technology mapping, or by multilevel logic transformations. The design flow will be described in a universal way, so that its integration and application to other Design Environments is possible. It will be demonstrated at the example of a GFSK/GMSK MODEM, one of the most critical blocks in the entire baseband signal processing of a multi-mode DCS1800-GSM/DECT terminal. Objectives To complete the development of a top-down, low power design methodology/flow for DSP applications. To demonstrate the methods at the example of an integrated GFSK/GMSK ModulatorDemodulator (MODEM) for DCS1800-GSM/DECT applications. Participants INTRACOM (GR); UNIVERSITY OF PATRAS (GR) Contact Point INTRACOM S.A. Spyridon BLIONAS or Haralabos Karathanasis GR-190 02 PEANIA (Greece) P.O. BOX 68 Duration 24 months from 01.11.97 Tel: (+30-1) 686 0442 or 686 0407 Fax: (30-1) 686 0312 email: sbli@intranet.gr or bkar@intranet.gr Web Site: www.intranet.gr 6-5 6. Design Clusters TCS 98 EP 25279 COOL-LOGOS Power Reduction through the Use of Local don’t Care Conditions and Global Gate Resizing Techniques: An Experimental Evaluation. Summary The partners in this project have jointly developed a high-performance 24-bit DSP which is suitable for a multitude of applications, such as decoding the AC-3 Dolby standard for digital TV audio, voice compression, multi-channel echo-cancellation, digital beam forming, etc. This DSP has been fabricated and has been demonstrated in an AC-3 decoder application. The project partners have also been working on the development of low power design techniques aimed at achieving 25% power reduction over designs performed with our current cell-based IC design flow. These techniques are based on the exploitation of local don’t care conditions in multi-level logic circuits and gate resizing to achieve a net reduction in overall circuit power dissipation. A greedy algorithm for low power circuit node optimization using local don’t care conditions has been developed and tested in a simulation environment with encouraging results. Objectives To apply the developed low power design techniques to the existing 24-bit DSP which is already fabricated To assess the merit of the mew techniques using experimental silicon through - comparisons of the projected power reduction (in simulation) and actually measured reduction of new DSP; - assessment of the commercial impact. Participants DCT-HELLAS (GR), ATMEL/ES2 (F) Contact Point Stelios KOUTROUBINAS DCT Hellas P.O.Box 5115 26004 Patra, (Greece) Duration 16 months from 01.11.96 Tel: +30 61 453588 Fax: +30 61 453304 E-mail: steliosk@dctcorp.gr 6-6 6. Design Clusters TCS 98 ESD 25400 SUPREGE A low power SUPerREGEnerative transceiver for wireless data transmission at short distances Summary The objective is to investigate a new micropower wireless data transmission solution over short distance, in the UHF ISM frequency bands (430 and 920 MHz). The micropower transceiver will make use of an original architecture based on the super-regeneration principle. This circuit will be developed by the Electronics Laboratory of EPFL as a monolithic IC. The principle of super-regeneration, which is based on the variation of the start-up time of an oscillator as a function of the signal coupled from the antenna, allows a very simple transceiver architecture, and appears to be particularly suited to micropower applications, compared to classical solutions such as the superheterodyne, the low IF (Intermediate Frequency) or the direct conversion receiver. The present project seeks to take up the basic idea of superregeneration by introducing original analog integrated circuits techniques for low-power performance such as automatic power-down techniques, as well as improved selectivity, sensitivity and cancellation of parasitic radiation compared to a discrete-components solution. The core of the superregeneration system being an oscillator, the receiver and transmitter functions make full use of the same circuit blocks. The whole concept has been validated by simulation. A first version of the core of the receiver has been realised in AMS BICMOS 0.8 µm technology. The superregenerative transceiver will be used in 3 industrial applications which share the constraint of requiring micropower wireless data transmission over short distance: (1) a remote control for vehicle alarms (Transval), (2) wireless computer peripherals (Logitech), and (3) a wireless data transmission system for water counters (Mead Microelectronics). Objectives system-level design; design trade-offs and optimisation of the micropower receiver / transmitter as a function of various parameters (power consumption, area, bandwidth, sensitivity, etc); modulation / demodulation and interface with data transmission systems; realisation of the integrated micropower receiver / transmitter based on the superregeneration principle; realisation of 3 demonstrators dedicated to each industrial application. Participants EPFL- LEG (CH), TRANSVAL SA (F), LOGITECH SA (CH), MEAD SA (CH) Contact Point Dr. Catherine DEHOLLAIN EPFL, LEG, ELB Ecublens, CH-1015 Lausanne, (Switzerland) Tel: +41 21 693 69 71 Fax: +41 21 693 36 40 E-mail: catherine.dehollain@epfl.ch Duration 24 months from 01.12.97 6-7 6. Design Clusters TCS 98 ESD-LPD 25403 SOFLOPO Low Power Software Development for Embedded Applications Summary SOFLOPO will develop techniques and guidelines for mapping a specific algorithm code onto appropriate instruction subsets, so that it allows an optimal low-power code execution, for microprocessor architectures used in embedded applications. The power consumption of the code will be evaluated by means of physical measurements, instead of a detailed bottom-up simulation approach, which is unavailable due to the lack of detailed processor models. Upon these measurements, detailed models that relate software code and power dissipation will be established. These models will form the basis of developing code optimization techniques for the purpose of lowenergy software execution. Extensions of existing algorithms for Interpreter optimization, that will aim at energy minimization will be developed. This systematic modeling of the relationship between power dissipation and software code will take place for the ARM-RISC processor. An extension of the above methodologies to include DSP processors will follow. These processors constitute a big portion of embedded microprocessors. Except from specific conclusions for each architecture under inspection, general conclusions, applicable to other architectures, within some accuracy limit, will be extracted. The viability of the derived techniques will be demonstrated by their application upon the implementation by DCT- Hellas of the IEEE 802.11 protocol microcode, used in Wireless Local Area Networks. For their full dissemination, the results of the SOFLOPO project will be integrated into software for the power-conscious ARM-RISC and DSP code optimization. This software will be available to interested third parties. It will be also available for free to Universities under a non-disclosure agreement. Objectives Characterize the instruction set of the ARM (and a DSP) processor in terms of power consumption. establish models that relate software code and power dissipation. develop techniques and guidelines for mapping a specific algorithm code onto appropriate instruction subsets. integrate these techniques into software for the power-conscious ARM-RISC and DSP code optimization. Participants UNIVERSITY OF PATRAS (GR), DATA COMMUNICATIONS TECHNOLOGIES-HELLAS (GR) Contact Point Duration Dr. Thanos STOURAITIS, 24 months from 01.11.97 Department of Electrical and Computer Engineering University of Patras, Rio, 26500, (Greece) Tel: +30 61 997322 Fax: +30 61 994798 E-mail: thanos@ee.upatras.gr 6-8 6. Design Clusters TCS 98 EP 25475 COLOPODS Design of a Cochlear Hearing Aid Low-Power DSP System Summary The proposed project reduces the power consumption of the external processor of the LAURA Cochlear Implant system. The Laura Cochlear Implant is an implantable device for the deaf and profoundly hearing impaired that electrically stimulates the auditory nerve fibres. The operation of the internal part of the LAURA cochlear implant system is controlled by an external speech processing system the size of a normal hearing aid. In this speech processor the sound signal is processed into stimulation commands that are transmitted to the internal part. A low power implementation will make operation from standard hearing aid battery cells possible. This will mean a fundamental upgrading of the LAURA cochlear implant system and will allow a stronger position for Antwerp Bionic Systems on the world market. It is expected that the redesign of the cochlear hearing aid Digital Signal Processor in a low power technology will reduce the processor's power consumption by a factor of 10. Through gained know-how and experience in low power optimisation, low power DSP design techniques the speech processing can be further optimised using dedicated processing architectures. ABS has two alternatives for the low power I.C. technology for the actual implementation: a low power, high speed IMEC pilot process and a mainstream PHILIPS process that would be operated at a low voltage yielding a low power, low speed technology. Since both technologies have their own drawbacks and advantages, a pre-study is incorporated in the project to select the most appropriate technology. Objectives Selection of a future oriented low-power technology enabling future power reduction through integration of analog modules. Design of a speech processor IC yielding a power reduction of 90% compared to the 3.3 Volt implementation. Gain low-power design know-how for further power reduction of the system. Participants ABS (B) Contact Point Ir Jan JANSSEN, Antwerp Bionic Systems N.V. Drie Eikenstraat 661, 2650 Edegem (Belgium ) Tel: +32 3 825 26 16, Fax: +32 2 825 06 30 E-mail: jan.janssen@phi.com Duration 16 months from 01.12.97 6-9 6. Design Clusters TCS 98 EP 25476 PAPRICA POWER AND PART COUNT REDUCTION INNOVATIVE COMMUNICATION ARCHITECTURE Summary The PAPRICA project will demonstrate the capability of CMOS technology in the low power RF domain, to achieve a considerable power reduction in wireless terminals. The main goal is to design a new architecture for RF digital mobile communication systems. The novel receiver architecture, called DOUBLE Quasi-IF with early A/D conversion (DQIF), offers a high degree of flexibility, allowing its implementation for a different number of standards, like DECT, PMR (TETRAPOL), and GSM. Since a relevant part of signal processing is performed at baseband instead of high frequency, the architecture offers a reduction in power consumption when compared with other traditional techniques, like the super-heterodyne one. Particular features are i) triple RF to baseband down-conversion, with ii) first down conversion at 150 MHz through a LO at fixed frequency, iii) second conversion of a sub-band of 3 MHz containing the desired channel, iv) third completely digital conversion after delta-sigma band-pass A/D conversion, v) final channel selection performed in the digital domain. Due to the particular conversion technique, the electrical specifications of the most critical blocks will be less demanding, and consequently expected power consumption will be very competitive. Project Objectives Feasibility assessment of DQIF, through physical design and characterisation of the core blocks; DQIF “ad-hoc” block specifications from system specifications (i.e. DECT); Low-power RF design techniques in standard CMOS digital process; Process qualification for RF (RF design Manual); RF design tools and framework; PAPRICA Design Kit. Participants ATMEL ES2 (F), IST (P), MATRA COMMUNICATION (F) Contact Point Ben ALTIERI Atmel ES2 (France) Duration 30 months from 1 August 1997 Tel: +33.442536194 Fax: +33.442536001 E-mail:baltieri@es2.fr 6 - 10 6. Design Clusters TCS 98 EP 25485 ALPINS Analogue Low Power Design for Communications Systems Summary The ongoing trend towards reduced supply voltages of mobile and cordless systems is mainly driven by the need to implement their digital part in modern sub-micron technologies, but it introduces serious problems for the design and verification of analogue circuits. It is the strategy of this project to reduce the minimum required supply voltage of a typical analogue signal processing circuit by focusing on the design methodology of its most critical blocks. In this way, the well-established gm-C filter technique will be optimised for low-voltage operation, new A/D- and D/A- converter concepts will be investigated and the recently developed log-domain filter technique will be brought to commercial use. This filter principle is especially well suited for low-voltage low-power applications, since it represents internal signals by instantaneously compressed voltages, while maintaining an over-all linear transfer function. Innovative and aggressively optimised circuits require also a more profound way of design verification. Therefore, a recently developed Formal Verification Tool will be implemented in the design environment and used for checking the new designs. For ensuring a timely return of investment, a DECT and a GSM handset were chosen as demonstrators for this project. Objectives New instantaneous companding filter principle; Efficient use of the dissipated power, in particular at very low supply voltages (<1.5V); Low-voltage voice band smoothing filters and analogue-to-digital and digital-to-analogue converters for an analogue front-end circuit of a DECT system; High linear transconductor-capacitor (gm-C) filter for GSM Analogue Interface Circuit operating at supply voltages as low as 2.5V; Formal verification tools, which will be implemented in the industrial partners design environment. These tools support the complete design process from system level down to transistor level. Participants SIEMENS AG (D), SIEMENS EZM (A), UNIV. HANNOVER (D), EPFL (CH) Contact Point Dr. Rudolph KOCH Siemens Semiconductor Group HL SP E MS D-81541 Munich,(Germany) Tel: +49 89 636 24048 Fax: +49 89 636 23649 E-mail: rjkoch@scn.de Duration 24 months from 16.11.97 6 - 11 6. Design Clusters TCS 98 EP 25518 DABLP Low Power Exploration for Mapping DAB Applications to Multi-Processors Summary A channel demodulator and decoder IC for Digital Audio Broadcast (DAB), called DABchic, has been designed by Philips. This IC has a great relevance for near future markets in the digital automotive and handheld DAB terminal segment. IMEC has developed a unique low power system exploration methodology (ATOMIUM), that concentrates on algorithm and architecture transformations at a high abstraction level, and which will be applied to this application. The result will be an alternative architecture, which will be analysed by comparing the power consumption of the new design with the existing one. The power dissipation should be reduced by at least a factor of three. The direct result will be a lowpower architecture to be used later in the next generation DAB channel decoder IC, marketed by Philips Semiconductors. The analysis of the result will lead to a further improvement of the ATOMIUM methodology and the supporting system exploration tools. That methodology will be used in the future for IC-architecture designs. In this consortium IMEC delivers the methodology so it becomes available for the Philips design centres. IMEC on the other hand improves the methodology by using the industrial experience. Objectives An existing state of the art system-level low-power IC design methodology, ATOMIUM, has been developed by IMEC. This methodology will be used on a channel demodulator and decoder IC for Digital Audio Broadcast (DAB). The main results of this project will be: A DAB channel decoder architecture with reduced power consumption; Proof of the impact of the ATOMIUM methodology; Refined and extended ATOMIUM methodology and supporting tools Participants PHILIPS (NL), IMEC (B) Contact Point Duration Ir. Paul Lippens, 36 months from 01.11.97 Philips research laboratories Prof. Holstlaan 4 (WAY 41), 5656 AA Eindhoven, (The Netherlands) Tel: +31 40 27 44346 Fax: +31 40 27 44657 E-mail: lippens@natlab.research.philips.com 6 - 12 6. Design Clusters TCS 98 EP 25519 DESCALE Design Experiment on a Smart Card Application for Low Energy Summary The market of smart cards is booming and the European semiconductor industry has a firm lead in the development and production of so-called smart card controllers. From a technology point of view, there are two important trends. Primarily, more and more functionality is added on-chip, requiring more computational power. Both the associated extra energy consumption and the extra heat removal (plastic is a poor heat conductor) are major challenges. Secondly, a large growth is expected in the market for contact-less cards, respectively dual-interface cards. Those cards collect energy from the electro-magnetic field applied to it from some distance. Here it is also critical to lower the peak current consumption. DESCALE, a Design Experiment on a Smart Card Application for Low Energy, proposes the application of the highly innovative handshake technology to address both issues, aiming at some 5 times less power and some 10 times smaller peak currents compared to synchronously operated solutions. The required technologies are all represented in the consortium, so are the means to exploit the results. DESCALE can contribute to strengthen the European leadership in smart cards. Participants PHILIPS SEMICONDUCTORS (D), PHILIPS RESEARCH (NL), MIKRON (A), MIKROELEKTRONIK ANWENDUNGSZENTRUM HAMBURG (D) Contact Point Dr. Volker TIMM Philips Semiconductors Hamburg (Germany) Duration 24 months from 1 November 1997 Tel: +49-40-5613-2961 Fax: +49-40-5613-3313 E-mail: Volker.Timm@hamburg.sc.philips.com 6 - 13 6. Design Clusters TCS 98 EP 25599 SB-USB Software Based Universal Serial Bus Summary The so-called Universal Serial Bus (USB) is a fast, bi-directional isochronous, low-cost, dynamically attachable serial interface for connecting a wide range of peripherals like telephone/fax/modem, answering machines, scanners, keyboards and mice to PCs. This new standard developed by Compaq, DEC, IBM, Intel, Microsoft, NEC and Northern Telecom is rapidly gaining acceptance across the entire PC industry. All existing USB interface devices are implemented in 3 layers: the electrical interface handled by dedicated analogue hardware, the low-level protocol layers implemented in dedicated digital circuits, and the high-level protocol layers implemented in software. An implementation of all protocol layers in software would be valuable in terms of cost, flexibility, and versatility. In existing USB devices, however, the low-level protocol layers are implemented in hardware, since most available 8-bit microprocessor cores consume more power than available or provide only a fraction of the required processing speed. In the meantime it was shown that CSEM’s CoolRISC microprocessor cores provide already 2/3 of the required processing speed (25 MIPS in 0.5u CMOS technology, while 36MIPS are needed) within the defined power constraints. To reach the USB specifications, critical groups of USB instructions will be implemented in dedicated circuits and integrated as peripherals to the CoolRISC microprocessor core, such that they can be executed in a single microprocessor instruction. Objectives A software-based low-speed USB device will be developed based on low-power 8-bit microprocessor cores such as CSEM’s CoolRISC. This device will be integrated in Logitech’s USB mice. Participants XEMICS (CH), LOGITECH (CH) Contact Point Vincent RIKKINK, XEMICS SA Rue de la Maladière 71, CH-2007 Neuchâtel (Switzerland) Duration 18 months from 01.01.98 Tel: +41 32 720 54 27 Fax: +41 32 720 54 27 E-mail: vincent.rikkink@xemics.ch 6 - 14 6. Design Clusters TCS 98 EP 25615 SALOMON System-level analog-digital trade-off analysis for low power Summary The goal of SALOMON is the development of a design flow that allows a system-level exploration of mixed analog-digital telecommunication ASICs. Such exploration will allow high-level architectural trade-offs between an analog and a digital implementation of a given functional block in order to obtain the lowest overall power consumption. The design flow will allow system designers to simulate architectures by making use of high-level models of the circuits. Together with the high-level simulations, the overall power consumption will be monitored. To this purpose, high-level power estimators will be developed in this project for the different analog and digital blocks that are used in the examples. Today analog-digital partitioning is typically performed in a heuristic manner by an experienced system designer and it is often strongly based on previous designs precluding the investigation of novel architectures that may consume less power. In order to make such system-level architectural explorations feasible without designing every sub-block down to the transistor level, the system designer must be able to simulate the entire system architecture at a behavioural level in order to verify the functionality and the performance. Existing simulation tools are not satisfactory to this end. In this project a new high-level design flow for mixed-signal telecom ASICs will be developed based upon the combination of system-level behavioural performance simulation and power estimators. This general design flow could be implemented by means of a number of different software tools for simulation. In this project, one particular prototype implementation will be realised in order to illustrate the feasibility of the general design flow. Objectives a general top-down design flow for mixed-signal telecom ASICs. high-level models of analog and digital blocks and power estimators for these blocks. a prototype implementation of the design flow with particular software tools to demonstrate the general design flow. application of the design flow to digital telecom examples. Participants IMEC (B), K.U.LEUVEN (B), ALCATEL-MIETEC (B) Contact Point Dr. Piet WAMBACQ, IMEC Kapeldreef 75, B-3001 Heverlee (Belgium) Duration 36 months from 01.10.97 Tel: +32 2 16 281 223 Fax: +32 2 16 281 515 E-mail: wambacq@imec.be 6 - 15 6. Design Clusters TCS 98 EP 25702 I-MODE Low Power RF to Baseband Interface for Multi-Mode Portable Phones Summary The main objective of I-MODE is to raise the level of integration in a DECT/DCS1800 transceiver, by implementing the necessary analog baseband low-pass filters and data converters in CMOS technology using low power techniques. The proposed work is closely related to and complements the OCMP Esprit Project (24123) and the ASPIS Esprit Project (20287). OCMP undertakes the development of a direct conversion transceiver for DECT/DCS1800 modes in a bipolar technology, whereas ASPIS undertakes the development of the baseband processing (DSP) function in a CMOS process for DECT/GSM/DCS1800 modes, operating from a 3V supply voltage. In the I-MODE project, the required filters and data converters (not covered in the OCMP or ASPIS Projects) will be implemented, using low-power-effective techniques, such as current-mode, in a CMOS technology. The overall gain in reduced complexity, area and power consumption will be direct for the end product. As a matter of fact, the proposed action is an essential step towards a true one-chip system. Moreover, the use of low-power design methods can contribute to further lowering the power consumption profile for the end product. Objectives The project will facilitate the complete eventual integration of the analog/digital interface with the RF frontend (from OCMP) on a single BiCMOS chip or with the DSP (from ASPIS) to ultimately put all the baseband processing on a single digital CMOS chip. Participants INTRACOM (GR); INSTITUTE OF COMMUNICATIONS AND COMPUTER SYSTEMS-NATIONAL TECHNICAL UNIVERSITY OF ATHENS (GR) Contact Point Mr. Dimitris DERVENIS INTRACOM S.A. 19,5 km Markopoulou Ave 19002 Peania, (Greece) Duration 18 months from 01.12.97 Tel: +30 1 6860456 Fax: +30 1 6860312 E-mail: dder@intranet.gr Web: http://www.intracom.gr 6 - 16 6. Design Clusters TCS 98 EP 25710 CRAFT CMOS Radio Frequency Circuit Design for Wireless Application Summary The main objectives of the project are to develop low power and low voltage key RF blocks for highly integrated personal communication terminals and to derive a design methodology for such RF blocks based on the used CMOS technology. This Design Experiment is aimed on advanced architecture and circuit design to allow single chip integration of the base-band and RF section in CMOS technology for 2nd and 3rd Generation Mobile and Wireless Systems using the 900MHz and 2GHz band. The main areas of application for the developed circuits are for example the UMTS (W-CDMA, TD-CDMA), GSM, DECT and FLEX paging standards. By designing, building and testing functional silicon prototypes, enhanced technologies for manufacture and assembly are to be developed in the field of advanced low power CMOS circuits. The prototypes are developed in three steps, component level, block level and system level, and are designed to serve as electronic building blocks in real products in wireless and mobile communications applications. Furthermore, the technology is considered to be suitable for the design of subsystems in the market segments of consumer products, automotive and other industrial applications. Objectives Advanced CMOS RF circuit design including blocks such as LNA, downconverter mixers & phase shifters, oscillator and frequency synthesiser, integrated filters, delta sigma conversion, power amplifier, etc. Development of novel models for active and passive devices as well as fine tuning and validation based on first silicon fabricates; Analysis and specification of sophisticated architectures to meet in particular low power single chip implementation ; Individual block design, simulation, and evaluation against silicon prototypes; Exhaustive system validation based on a complete prototype for a dedicated system; Functional prototypes based on applications for wireless and mobile communications. Participants CSEM (CH), SGS-THOMSON (F), CNET (F), UNIVERITY PAVIA (IT), EPFL (CH) Contact Point Duration Dr. Heiko ERBEN, 24 months from 01.01.98 Centre Suisse d’Electronique et de Microtechnique SA Advanced Systems Engineering Tel: +41 -32 / 7205 695 Fax: +41 -32 / 7205 720 E-mail: heiko.erben@csemne.ch http://www.csemne.ch 6 - 17 6. Design Clusters TCS 98 EP 25716 PCBIT Low Power ISDN Interface for Portable PC's Summary OCTAL has developed and is presently commercialising a PCBIT board which plugs into the PC's ISA bus and allows an ISDN interface. The current PCBIT board uses off-the-shelf components based on the Siemens chipset. The objective of this project is to redesign this board in a PC-Card format with a PCMCIA interface so that the portable PC market can be targeted. Essential for the success of a product in the portable market is its low power consumption. We propose to design an ASIC to integrate much of the functionality of the off-the-shelf components. We expect to achieve significant power savings by this process alone. Moreover, we plan to explore some power management techniques to further reduce power consumption. Objectives Design of a PC-Card board that implements the PCBIT interface; Integrate levels 1 and 2 of the communication protocol in a single ASIC; Incorporate power management techniques in the ASIC design: - system level: shut-down of idle modules in the circuit, - gate level: precomputation, gated-clock FSMs; Evaluate the impact of the different power reduction methods used; Promote the design methodology and design experiment results. Participants INESC (P), OCTAL (P) Contact Point Prof. José C. Monteiro, IST / INESC Rua Alves Redol, 9 - Sala 134 (Portugal) Duration 18 months from 01.11.97 Tel: +351 1 310 0283 Fax: +351 1 314 5843 E-mail: jcm@inesc.pt 6 - 18 6. Design Clusters TCS 98 EP 26530 ABACUS Active Bus Adaptor and Controller for remote UnitS Summary In the area of electronic systems for satellites and spacecrafts, where LABEN mainly operates, the demand for an increasing number of channels, while maintaining the same power consumption and system volume, together with the availability of new rad-hard technologies imposes fully integrated solutions. Objective of this design experiment is the development of a mixed-signal ASIC, using 0.8 µm TEMIC SOI technology, that implements an analog-digital interface between the spacecraft On-Board Data Handling (OBDH) bus and the Remote Terminal Units (RTUs). The main characteristics are: implemention of an analog/digital interface between the spacecraft On Board Data Handling (OBDH) subsystem bus and the satellite Remote Terminal Units (RTUs); Provision of the RTUs with a non-corrupted data flow (as happens in case of multiple loads on the bus or in case of cross-talk phenomena); Provision of synchronisation detection and clock period recovery; Interface the ESA-OBDH data bus in full compliance with the TTCB-01 OBDH protocol. The device has to withstand a wide range of radiation environments, so it has to be radiation hardened. Objectives To extend design know-how by acquiring the capability to design and manufacture mixed analog-digital components with advanced technologies and state-of-the-art design tools. To derive design requirements and final design specifications of the device. To perform the detailed design phase including design and simulation of the functional blocks, performing transistor/gate-level implementation of the functions and simulation allowing also the validation of the high level models. Two iterations are foreseen for this phase. To produce prototypes of the device. Two iterations are foreseen for this phase. To perform testing of the mixed-mode prototypes. Partcipants LABEN (I), UNIVERSITY OF PAVIA (I), MICONOVA SISTEMI (I) Contact Point Dr. Corrado MAUCERI LABEN S.p.A. S.S. Padana Superiore, 290 20090 Vimodrone (MI) –(Italy) Duration 24 months from 01.01.98 Tel. +39.2.25075.1 Fax +39.2.2505515 Email mauceri.c@laben.it 6 - 19 6. Design Clusters TCS 98 Equipment Assessment EP 20305 EMW Evaluation of a Highly Productive Computercontrolled Microwave Barrel Ash System for IC Fabrication Summary The performance of the Technics Plasma microwave barrel asher "Plasma-Processor 300Autoload" is to be assessed in the IC manufacturing line of SIEMENS Bauelemente, Villach. The assessment is to show that the Technics Plasma barrel asher offers the advantages of both barrel (high wafer throughput, low cost of ownership) and single wafer ashing systems (low degree of radiation damage). Objectives To evaluate and demonstrate high availability and throughput, and low cost of ownership of the barrel asher. To evaluate substrate surface and gate oxide damage and compare with single wafer ashing systems for different IC process technologies. To carry out a final equipment test under full production conditions in the SIEMENS Villach production line. Participants SIEMENS BAUELEMENTE (A); TECHNICS PLASMA (D); ZMD (D). Contact Point Michael SCHWARK SIEMENS Bauelemente Siemensstr. 2 A-9500 Villach (Austria) Duration 12 months from 08.12.95 tel: +43 4242 305 524 fax: +43 4242 305 401 7-1 7. Equipment Assessment TCS 98 EP 20331 SIDOSI Single Wafer Highly Doped n+ and p+ Amorphous and Polysilicon Summary The performance of the ASM International Paragon single wafer polysilicon deposition system and process are to be assessed, improved and compared with batch systems. The assessment will be on 200 mm silicon wafers. Specifications for 300 mm processing will also be established. Objectives To evaluate the Paragon single wafer deposition system and a deposition process for heavily p+ and n+ doped amorphous and polysilicon thin films on technical, technological and productivity merits. To give special emphasis to throughput and cost of ownership of the deposition system and to reactor memory phenomena in connection with reactor cleaning and wafer surface preparation. To focus on process parameters such as uniformity and reproducibility of film thickness, resistivity and grain size. To compare costs of single wafer and batch furnace processing. To provide specifications for 300 mm processing in addition to the assessed 200 mm capabilities of the ASM I deposition system. Participants GRESSI (F); ASMI, (NL); MOTOROLA (UK); SGS THOMSON (F); PHILIPS (NL). Contact Point Daniel BENSAHEL GRESSI (CNET) BP 98 F-38043 Meylan (France) Duration 12 months from 01.12.95 tel: +33 76 764140 fax: +33 76 903443 E-mail: bensahel@cns.cnet.fr 7-2 7. Equipment Assessment TCS 98 EP 20390 FORCEFILL Assessment for 0.5 micron contact/via plug technology (Al/0.5%Cu) in a high volume production environment Summary The performance of the Electrotech SIGMA 204 FORCEFILL cluster tool is to be assessed for 0.5 micron contact/via plug technology (Al/0.5%Cu) in the high volume production environment of Texas Instruments, Freising Germany. The advantages of this aluminium FORCEFILL technology over the presently employed tungsten plug and aluminium process has to be demonstrated under manufacturing conditions. The complete metalisation process sequence is: Sputter etch - Ti/TiN - Al/0.5%Cu - FORCEFILL. Objectives To evaluate performance and cost benefits of the new metalisation technology over the tungsten plug/ aluminium process. To evaluate the sputter etch - Ti/TiN processes which precede the aluminium deposition and the FORCEFILL process. To assess and improve the overall equipment performance in a high volume 0.5 micron BICMOS production line Participants TEXAS INSTRUMENTS (D); ELECTROTECH (UK); ERICSSON (S). Contact Point Leo STROTH Texas Instruments Deutschland Freising Wafer Fab Haggertystr. 1 D-85350 Freising (Germany) Duration 13 months from 01.12.95 tel: +49 8161 804070 fax: +49 8161 804835 7-3 7. Equipment Assessment TCS 98 EP 20445 CAME Cleaning Assessment in a Mini-Fab Environment Summary The "Chamber-Flow" acid wafer cleaning equipment of SAPI provides an ideal capability for an ASIC mini-fab, such as ELMOS or ZMD, to break away from the conventional robotic wet bench acid cleaning systems, with their high operating costs and over-capacity (1000 wafers/hour), and to use the appropriate capacity of a smaller modular system. Several other advantages, like small footprint, complete air-free "dry-to-dry" process and "piston-effect" rinsing bring advantages over robotic wet benches. Objectives Assess SAPI "Chamber-Flow" acid pre-furnace in ELMOS new 150 mm fab-line. Establish and meet target specification for the quality of the cleaning process in terms of particles (<0.05/cm2 at 0.3 micron ), metal contamination (<1.0 x 1010 atoms/cm2 for common metals), and surface roughness (<0.5 nm over 100 x 100 micron. Establish cost effective, "Caro"-HF-last, cleaning process to above specification as first step. Establish "High-Rel", highest quality, cleaning process to improved specification as second step. Correlate cleaning efficiency with actual yield on reliability data from running production. Characterise the "Chamber-Flow" in terms of CoO, uptime (>95%), MTBF (>500 Hrs), MTTR (<5 Hrs), reproducibility and safety. Participants: ELMOS GMBH (D); SAPI (F); ZMD (D); FHG-IMS (D). Contact Point: Volker GRUBER ELMOS GmbH Joseph-von-Fraunhofer Str. 9 D-44227 Dortmund (Germany) Duration: 15 months from 01.12.95 tel: +49 (0)231-7549-232 fax: +49 (0)231-7549-149 E-mail: vgruber@elmos.de 7-4 7. Equipment Assessment TCS 98 EP 20628 CICDIP Hot Cluster for Integrated Vapour Phase Cleaning and Processing of Dielectrics and In-situ Doped Polysilicon Summary The performance of a four port hot cluster delivered by ASMI (platform and CVD modules) and by AST (RTP modules) will be assessed at SIEMENS in Munich. The final goal is to demonstrate technological superiority of clustered single wafer processing of very thin films over batch processes. This should lead to competitive cost of ownership figures even with lower throughput for single wafer processing. Objectives To establish sequential processes including rapid thermal clean (RTC), DRAM or EEPROM stack (Rapid Thermal Oxidation/Nitration: RTO/N) and rapid CVD of doped poly or nitride (RTCVD). To examine technical processes, equipment economics (CoO) and reliability for the hot processing cluster-tool. To compare technological performance and economics of the cluster tool with standard batch processing. Participants SIEMENS (D); ASMI (NL); AST (D); AMS (A). Contact Point Alexander GSCHWANDTNER SIEMENS (D) Otto-Hahn-Ring 6 D-81739 Munich (Germany) Duration 18 months from 01.06.96 tel: +49 89 636 45067 fax: +49 89 636 48666 7-5 7. Equipment Assessment TCS 98 EP 25470 PLASMON Assessment of advanced plasma diagnostic tools for in-situ process control and monitoring Summary To evaluate different advanced in situ plasma control tools. The assessment will be carried out on production tools used for 0.25 m technology on 200 mm wafers. In situ monitoring of every product wafer is the key to reducing production time and costs. The use of plasma diagnostic tools helps to avoid misprocessing and wafer scraps. Furthermore, cleaning procedures and chamber conditioning can be optimised in order to increase wafer throughput. Objectives Siemens AG evaluates the Hercules sensor from the Adolf-Slaby Institut, Berlin. This sensor measures the electron density and electron collision rate of the plasma. The studies will focus on endpoint detection of small area features, determination of wet-clean cycles of the etching chamber, process faults, and process drifts. SGS Thomson uses an ion flux probe developed at the Université Joseph Fourier, Grenoble. This sensor measures the ion flux impinging on the sensor during plasma processing. Since the ion flux depends on the thickness of polymers deposited on the probe during etching, this method allows the cleanness of the chamber to be measured. Other possible applications are determination of process faults and drifts, and monitoring of chamber cleaning and seasoning procedures. SMST evaluates the Mulitchannel Process Monitor MPM16 from PAS, Itzehoe/Berlin. This method allows etch rate and uniformity measurements of deposition and etching processes. The potential of endpoint detection as well as process drifts and faults are under investigation. Reflectance difference spectroscopy (RDS) from Jobin-Yvon, France, will be used by GRESSI to monitor in real-time polysilicon gate etch processes. The two potential applications of RDS are 1) detection of the end of the polysilicon etch when arriving on the thin gate oxide 2) the signatures recorded in real-time may be used to control the reproducibility of the etch from wafer to wafer and from batch to batch. Participants SIEMENS AG (D); SGS THOMSON (F); SMST (D); GRESSI (F) Contact Point Ferdinand H. BELL Siemens AG HL CPS 3 D-81730 Munich (Germany) Duration 15 months from 15.09.97 tel: +49 89 636 50435 fax: +49 89 636 44236 E-mail: ferdinand.bell@hlistc.siemens.de 7-6 7. Equipment Assessment TCS 98 EP 20747 EDUSA European Deep-UV Stepper Assessment Summary The overall goal of this SEA project is to perform an in-depth assessment of the ASM-L PAS 500/300 deep-UV Wafer stepper for the volume production of 0,25 micron CMOS devices and to explore its potential for 0,18 micron geometries. The assessment site is at IMEC, while industrial users from Europe, the USA, Korea and Taiwan will be involved in the assessment. The project should result in the definition of industrial specifications for future deep-UV steppers, thereby strengthening the world-wide market position of the European equipment maker involved. Objectives assessment of the capabilities of a newly developed deep-UV stepper from ASM-L (PAS 500/300) for the volume production of 0,25 micron CMOS integrated circuits; evaluation of the stability of key lithographic parameters, such as, resolution, depth of focus, exposure latitude and proximity effects; study of lens heating effects; comparative study of the image sensor focus monitoring technique with alternative techniques; in-depth study of reliability issues such as mean time between failure (MTBF), mean time to repair (MTTR), mean time between incident (MTBI); analysis of cost of ownership in comparison with i-line steppers, taking into account capital investment, environmental issues, operational cost, material consumption and total installed wafer capacity; definition of updated specifications for future deep-UV steppers; initial evaluation of the PAS 500/300 performance for 0,18 micron CMOS technologies. Participants IMEC (B); ASML (NL); SIEMENS (D); PHILIPS (NL); GPS (UK); AT&T (E); NATIONAL SEMICONDUCTOR (USA); TI (USA); AMD (USA); TSMC (TAIWAN); GOLDSTAR (KOREA). Contact Point Luc VAN DEN HOVE IMEC Kapeldreef 75 3001 Leuven (Belgium) Duration 18 months from 01.06.96 tel: +32 16 281324 fax: +32 16 281214 E-mail: vdhove@imec.be 7-7 7. Equipment Assessment TCS 98 EP 23928 OPTIMA Optical Proximity Techniques in Microelectronics Applications Summary Optical lithography is a key technique used in semiconductor manufacturing. Strong efforts are being made worldwide to drive it to its technical limits in order to postpone the inevitable introduction of non-optical techniques. Optical Proximity Correction (OPC) is a technique which will make it possible to extend the practical resolution limits of existing exposure tools by at least one technology generation. The necessary OPC tools will be developed and evaluated under OPTIMA. Objectives The overall goal of OPTIMA is to demonstrate the effectiveness of proximity corrections in a production environment for both memory and logic applications. To develop a commercially available fast software tool which generates fully automatically a proximity corrected IC design with maximum CD variation due to proximity effects not more than 5% of the target dimension. To produce test masks for proximity parametrisation, demonstration masks for logic and memory applications (total dimension control better than 70 nm), and masks to investigate the resolution limits when applying OPC in combination with other enhancement techniques (total dimension control better than 50 nm). To assess the economical impact of the introduction of OPC taking into account that prices of proximity corrected reticles will be close to those of embedded PSM. Major results of the first project year. Software and Simulation The first available versions of the OPC correction software are based on a rule-based correction strategy. Using a rule-based approach the CPU time needed for correction is kept to a minimum. The table with rules used for correction can be filled with both experimental as well as simulated data. The OPC software is integrated into the existing SIGMA-C 'CAPROX' postprocessor environment. The users within the consortium are testing the software and provide feedback on performance Mask Making and Implementation. Using the available production facilities, a number of test masks have been generated for the parametrisation of the proximity effects. These test masks include electrical measurement structures that allow fast and efficient data collection over the stepper image field. The dimension control on these masks is in the order of 30nm (3) for the uniformity and 50nm variation in the target dimension. Further improvement is expected from the process enhancements studied in the project. For testing new maskwriters and processes, a test pattern has been designed which is a combination of the structures used for parametrisation and OPC corrected structures. The pattern enables the testing of the resolution, throughput and processing aspects of the 7-8 7. Equipment Assessment TCS 98 maskmaking process. Using the pattern, a number of new high-resolution maskwriters have been evaluated. From the test results an overview of the present and next generation maskwriter capabilities will become available. In Figure 1 SEM photographs of corrected structures are depicted. The structures have been generated using the Leica VB6 and a dry chrome etch process (left) and the EBMF tool using dry etched MoSi (right) and indicate the ultimate resolution capability available within the project. Figure 1 Mask with OPC corrected structures. In parallel with maskwriter evaluation and optimisation, chrome etching, resist technology and inspection are studied to achieve the performance required for OPC masks generation. Application and demonstration To use OPC effectively the printing and etching process are characterised in terms of their contributions to the proximity effect. Experimental data (resist and electrical measurements) and simulation are used. In order to benchmark the available OPC software programs, a comparison of the commercially available packages was made in two steps: First, all available OPC tools were reviewed according to their published specifications and roadmaps. Second, a subset (three tools) was selected for more throrough investigation. General features and handling of large data volumes ("load test") were investigated, and the correction efficiency was tested by the exposure of test wafers with corrected and un-corrected designs. Participants PHILIPS (NL); SIEMENS (D); IMEC (B); COMPUGRAPHICS (UK); SIGMA-C (D); SGS THOMSON (I); RAL (UK); GRESSI (F); CENTRE COMMUN (F). Contact Point Casper JUFFERMANS Philips Research Prof. Holstlaan 4 5656 AA Eindhoven (The Netherlands) Duration 24 months from 01.01.97 tel: +31 40 27 42540 fax: +31 40 27 43390 E-mail: juffermn@natlab.research.philips.com 7-9 7. Equipment Assessment TCS 98 EP 23929 LAPS Large Area Synthetic Fused Silica Photomask Substrates for 0.18 µm CMOS Technology Summary At the project start, high end photomask substrates were produced by Japanese suppliers only, who also dominate the high end photomask blank market. LAPS aims to establish a European source of substrates and blanks, which meet the requirements of 193 nm excimer laser exposure, 0.18 µm process technology, and 300 mm wafer size. Objectives To develop and evaluate 6”x6” substrates for 0.35 µm processing. To develop and evaluate 7”x7” substrates for 0.35 and 0.25 µm processing taking into account material resistance to 248 nm excimer laser radiation damage. To develop equipment and technology for large area substrates (9”x9”), which includes the process steps melting and squaring, and with respect to only technology development (using commercial equipment) includes process steps like slicing, lapping, polishing and cleaning. To develop large area photomasks material for production which is resistant to radiation damage at 193 nm exposure wavelength (for 0.18 µm technologies and beyond). Intermediate Stage Results (31.12.1997) Evaluation by Siemens of 6” blanks produced by Robotron with substrates provided by Sico indicated the following technological level: state-of-the-art results for all samples checked could be achieved for all parameters with the exception of defect density specification, which was fulfilled only by 3 out of 5 samples. Robotron, as reaction to the above results, has completed upgrading of the cleaning procedures. Improvements concern both handling and hardware used and have been confirmed by tests. Complete blanks will be produced as a next step. First improvements to the quartz melting technology resulted in bigger diameters and lengths of the raw glass ingots than achieved previously. Other relevant parameters remained the same or also improved. Participants At project Start: SICO (D); TBS (A); ROBOTRON (D); SIEMENS (D); IPTH (D) Changes: (actual situation at 28.1.98) TBS renamed to TBP; ROBOTRON taken over by Schott Glaswerke Mainz under firm SCHOTT ML GmbH (retrospectively from 1.1.1998, but not yet in effect); SICO’s business sections involved in this project also taken over by Schott Glaswerke Mainz under firm SCHOTT ML GmbH (retrospectively from 1.1.1998, but not yet in effect) Contact Point Dr.Fredi SCHUBERT Schott ML GmbH Jerusalemer Straße 13 D-98606 Meiningen, (Germany) Duration 33 months from 01.04.97 Tel: +49 3693 522574 Fax: +49 3693 710914 E-mail: Schott-ML.Masks@t-online.de 7 - 10 7. Equipment Assessment TCS 98 EP 23166 ELDS L-STRIPPER - Assessment of an excimer laser based tool to achieve perfect dry single step resist and polymer stripping for sub-micron technology Summary Removal of tough compounds which are formed during semiconductor wafer fabrication, is one of the tough challenges in photoresist stripping of sub half micron semiconductor wafers. The L-Stripper, a novel DUV-excimer laser based system, was developed by Oramir Ltd. to solve those demands. The fully automatic equipment comprises an industrial excimer laser, specially designed UV optics and a process chamber where the stripping process is achieved. The L-Stripper will be evaluated for its capability to achieve perfect dry single step (no post dry strip wet processing) resist and polymer stripping on deep sub-micron 150 mm and 200 mm semiconductor wafers. Expected results include single step dry photoresist stripping with reduction of cost of ownership (CoO), improved process yield and uptime. Objectives To evaluate the L-Stripper system to obtain: Photoresist stripping results for the advanced processes of sub-micron technologies. Cost of ownership figures for reference to other equipment. Assessment of installation and equipment functionality for future improvements. Assessment of yield improvement. Participants FRAUNHOFER INSTITUTE FOR SOLID STATE TECHNOLOGY (D); ORAMIR LTD (NL), ALCATEL-MIETEC (B); PHILIPS (NL); SIEMENS (D). Contact Point Peter RAMM Armin Klumpp FhG-IFT Hansastr. 27D 80686 MÜNCHEN (Germany) Duration 18 months from 01.04.97 tel: +49 89 54759299 fax: +49 89 54759100 E-mail: klumpp@ift.fhg.de 7 - 11 7. Equipment Assessment TCS 98 EP 24030 APC Advanced Photomask Cleaning Summary The goal of this project is the assessment of Steag HamaTech`s newly developed automated photomask cleaner (cassette to cassette) ASC 500. The assessment is to be carried out at the Siemens Mask Shop with masks for different applications. The result of the assessment of the ASC 500 will be a benchmark showing best of breed features: process performance, yield, reliability, uptime, cycle-time and cost-of-ownership. Objectives To integrate and evaluate the ASC 500 cleaner as one of the most important tools in the mask making process for production masks meeting the requirements of 0.25µm wafer technology. To prove the process quality of the ASC 500 (zero defects larger than 0.20µm), mean time to failure (MTTF) and mean time to repair (MTTR). For the evaluation of the ASC 500, a variety of masks (production masks and special test masks) with differing applications (CMOS/ASICs/Logic), mask types (Binary/ Phase shift masks) and production methods (E-beam/ Laser writing) will be used. Participants SIEMENS AG (D); STEAG HAMATECH GMBH(D); COMPUGRAPHICS INTERNATIONAL LTD. (UK), DUPONT PHOTOMASKS (USA, D); MZD (D) Contact Point Bernd HAY SIEMENS AG HL MAT PPT Balanstrasse 73 81617 Munich (Germany) Duration 14 months from 01.02.97 tel: +49 89 4144-8038 fax: +49 89 4144-3029 E-mail: bernd.hay@hl.siemens.de 7 - 12 7. Equipment Assessment TCS 98 EP 20757 AUTOWET AUTOmatic WET Bench for Critical Pre-Oxidation Treatments for Sub-Half Micron Applications Summary As Flash Memory products are getting more and more complex, the processes needed to produce these devices are getting more detailed and critical, while manufacturing costs and environmental friendliness are a must at the same time. To satisfy the above-mentioned requirements, the implementation in production of a new simplified cleaning concept (Twin Clean) with diluted chemistries and all the necessary hardware features to satisfy stringent process requirements (such as a HF concentration monitoring system) is the goal of the project. Objectives Reduction of CoO through a reduced chemical and DI water consumption per processed wafer and an increased throughput. Increase of the product yield through the improvement of the quality of critical active dielectrics. Reduction of the environmental impact through the simplification of the cleaning cycle and the elimination of dangerous chemicals. Set-up and characterisation with critical applications of a HF point-of-use monitoring system with software active automatic intervention on process parameters. Feedback and experience on the implementation in a production environment of a new cleaning concept. Strong cooperation among industrial users. Participants SGS-THOMSON MICROELECTRONICS (I), PHILIPS SEMICONDUCTORS (NL), STEAG MICROTECH GMBH (D) Contact Point Mauro ALESSANDRO SGS-THOMSON Microelectronics Via Olivetti 2 20041 Agrate Brianza (MI) (Italy) Duration 18 months from 01.12.95 tel: +39 39 6035852 fax: +39 39 6035233 E-mail: mauro.alessandro@st.com 7 - 13 7. Equipment Assessment TCS 98 EP 21981 APPLE Advanced Polishing and Planarisation Equipment Summary The performance of a Chemical Mechanical Polishing (CMP) cluster with the potential for 300 mm wafer processing, delivered by P. Wolters, is to be assessed and improved under IC manufacturing conditions at TEMIC in Heilbronn, Germany. A complex technological assessment programme is foreseen as well as intensive work on reliability and uptime improvement and reduction of chemicals consumption to achieve competitive cost of ownership figures. Objectives To improve throughput restrictions of CMP planarisation by clustering 2 to 3 polishing heads with a single double sided cleaning unit for 150 and 200 mm wafer processing. Better performance, lower cost of operation and flexibility for different CMP applications are targeted. Incorporate robotic handling, SMIF I/O, barcode reader, SECs/ GEM interface and endpoint detection. Later use of the tool for CMP planarisation of metal or high performance bulk silicon wafer polishing. Participants TEMIC (D); P. WOLTERS (D); SMST (D); SIEMENS (D); WACKER (D); AMS (A); FHG-ISIT (D); FHG-IIS (D). Contact Point Heinz-Achim HEFNER TEMIC Theresienstr. 2 (PO Box 3535) D-74072 (Germany) Duration 18 months from 01.04.96 tel: +49 7131 67 2379 fax: +49 7131 67 2933 E-mail: hhefner@temic-hn.de 7 - 14 7. Equipment Assessment TCS 98 EP 20580 ESCAPE-NET Total Environmental Fab Waste Gas Management via Networked and Monitored ESCAPE Disposal Systems Summary The performance of a monitored network of DAS ESCAPE waste gas abatement systems will be assessed in the production line of the IC manufacturer ZMD. Four critical disposal processes have been selected to demonstrate the technical performance of the networked ESCAPE system under production conditions, together with the cost advantage of monitored networks of abatement systems over the same number of independently used ones. Objectives To evaluate the emission of waste-gas of Al, TiN/Al, and SiO dry etching processes using CF4, CHF3, C2F6, BCl3, Cl2, SiCl4. To evaluate waste-gas emission of SiO, PSG and SiN CVD using SiH4, PH3 ,TEOS, DCS, NH3. To assess and minimise the cost of ownership of above mentioned disposal processes based on network data collection by ESCAPE-NET. Participants ZMD (D); DAS (D); ALCATEL MIETEC (B). Contact Point Guenter von RUTHENDORF ZMD GmbH (PO Box: 800134) Grenzstr. 28 D-01101 Dresden (Germany) Duration 12 months from 08.12.95 tel: +49 351 8822-287 fax: +49 351 8822-276 E-mail: teucher@zmd-gmbh.de 7 - 15 7. Equipment Assessment TCS 98 EP 23042 TRIO Optimally integrated vacuum/abatement/monitoring equipment for demanding semiconductor manufacturing processes (TRIO-VAMP) Summary In order to meet the customer needs for more efficient, cost-effective vacuum/ abatement/monitoring methods, Leybold Vakuum GmbH developed a new component system in a joint venture with DAS GmbH, a leading European waste gas abatement specialists. This system, TRIO, comprises a dry vacuum pump, hazardous waste gas abatement, and monitoring of status, including control. This new concept was introduced to the market at Semicon-Europa (April 1996), where the prototype attracted a lot of attention. Leybold assumes product responsibility and asks a major IC fab and the worldwide leading equipment manufacturer to support TRIO by participating in an SEA project. Expected results include reduction of CoO for vacuum/abatement/monitoring through high mean-time-between-failure, low mean-time-to-repair, and high abatement efficiency. Objectives The objectives of the TRIO-VAMP SEA are to evaluate the TRIO at a semiconductor manufacturing facility, together with an equipment manufacturer, in order to obtain: qualification for a new generation of dry vacuum pump, including treatment of waste gases, for critical manufacturing processes, e.g. metal etching, with leading U.S. fabrication equipment cost-of-ownership figures in running production for reference and competitive sales assessment of functionality in crucial running regimes for further improvements established references from semiconductor manufacturing end-users and guarantee of compatibility from major equipment manufacturers for optional purchase by future customers The proposed evaluation will give Leybold the unique opportunity to have its equipment evaluated by an industrial user as well as a wafer fabrication equipment maker. A broad base of fab managers, facilities managers, and processes are included in the evaluation. Participants TEXAS INSTRUMENTS DEUTSCHLAND GMBH (D); APPLIED MATERIALS (D); FHG-ISIT (D); LEYBOLD (D) Contact Point Dr. Helmut ENDL Texas Instruments Deutschland GmbH Wafer Fab Haggertystr. 1 D-85356 FREISING (Germany) Duration 12 months from 01.12.96 tel: +49 8161 80 4428 fax: +49 8161 80 3350 E-mail: dfeh@msg.ti.com 7 - 16 7. Equipment Assessment TCS 98 EP 22207 RETIMATIC Dual carousel semi-automatic reticle stocker Summary The performance of the dual carousel semi-automatic reticle stocker developed by Dynamic Microsystems is to be assessed and improved. Multiple reticle changes and high number of reticles in use typify the ASIC business, which seeks to improve the problem in manageable proportions with this reticle cassette stocker. Objectives To demonstrate under real manufacturing conditions the productivity and cost of ownership benefits of this fast reticle retrieval (10 secs) and dense (1000 reticles in 1.5 m² footprint) ASIC reticle storage machine. To show satisfactory operation of the stocker supervising computer when linked to the fab CIM system. Participants ALCATEL MIETEC (B), DYNAMIC MICROSYSTEMS (D), MATRA MHS (F) Contact Point Edgar LAES Alcatel-Mietec Westerring 15 9700 Oudenaarde (Belgium) Duration 11 months from 01.03.96 tel: +32 55 332245 fax: +32 55 332647 E-mail: ed_laes@mietec.be 7 - 17 7. Equipment Assessment TCS 98 EP 20379 IMPROVE In-line monitor for process optimization and verification Summary This project will assess, in a process environment, the SOPRA Multi-Layer Monitor (MLM) which is an automatic, clean-room compatible, high throughput, optical monitoring instrument based on multi-channel spectroscopic ellipsometry. The machine is capable of measuring, non-destructively, up to five layers simultaneously on patterned product wafers, providing information on thickness, crystallinity, composition, refractive index and roughness, together with uniformity mapping. The outcome of the project will be a machine with an operator-level methodology for important CMOS/Bipolar process steps with quantified capabilities/benefits. Objectives Improve current version of machine by: (a) reducing minimum wavelength to operate in UV for ultra thin oxide/nitride/oxide multilayers, (b) reducing spot size to 100x200 micron to allow measurements in test pads as well as scribe lines, and (c) incorporating alloy composition determination procedure in software. Assess accuracy and precision (repeatability) on a wide range of structures by comparison with off-line measurements. Assess ability to discriminate changing layer characteristics both within batches and from batch-to-batch, together with throughput and reliability, by extensive trials on selected representative structures from mainstream CMOS technology demonstrators and advanced Bipolar systems. Optimize ease-of-use by customization of analysis methodology for representative structures. Participants DRA (UK); SOPRA (F); GPS (UK); TEMIC RAL (UK). TELEFUNKEN MICROELECTRONIC Contact Point Dr Christopher PICKERING Defence Research Agency St Andrews Road MALVERN WORCS WR14 3PS (United Kingdom) (D); AMS (A); Duration 15 months from 01.01.96 tel: +44 (0)1684 894898 fax: +44 (0)1684 894311 E-mail: cpickering@dra.hmg.gb 7 - 18 7. Equipment Assessment TCS 98 EP 20649 HRAS High Resolution Analytical SEM Summary This project will assess an analytical Scanning Electron Microscope (SEM) from LEO (exZEISS), which offers a unique combination of state-of-the-art resolution in a low-voltage regime with the high-beam current of a Schottky heated field emission electron source. The advantage of this machine over the main competitors, Hitachi and Jeol, is a better signal-tonoise ratio and a significantly higher sensitivity in materials' analyses. The outcome of the project will be a machine upgraded to meet the online needs of defect/particle and failure analysis laboratories, today handled offline by the semiconductor manufacturers. Objectives Improve current version of machine by: improving the handling and equipping the tool with the proper load-lock, anticontaminator, and stage. simplifying operations with completely menu-driven parameter sets. adding missing link from inline review-stations to offline analysis. reducing maintenance frequency with a better performing contamination protection in the column. Participants SIEMENS (D); LEO (D); ZMD (D). Contact Point Jérôme TOUZEL SIEMENS AG Otto-Hahn -Ring 6 81739 München (Germany) Duration 18 months from 01.12.95 tel: +49 89 636 53281 fax: +49 89 636 44236 7 - 19 7. Equipment Assessment TCS 98 EP 22072 ILETIC In-line ellipsometer for thickness control Summary The assessment of the Plasmos SD 400 ellipsometer is to be carried out in the production environment of SMST. The result will be a benchmark showing best of breed features: precision, measurement capabilities (e.g. interferometer emulation for thin and thick layers, poly-Si, multilayers, multipurpose), throughput, cost-of-ownership. Objectives To integrate and evaluate the SD 4000 in a vertical furnace process cell of a high volume 4 Mb, 0.8 micron process line. To prove its versatility, accuracy and cost effectiveness for measuring a range of thin, single and multiple films. The layers to be evaluated include single layers in the range 4 nm - 1000 nm, multiple layers of ONO, OPO and monitoring of CMP processes. Participants SMST (D); PLASMOS (D); SIEMENS (D) Contact Point Martin HAFNER SMST HL 6435 Prozeßtechnik Schickardstraße 25 1460 BÖBLINGEN (Germany) Duration 12 months from 01.04.96 tel: +49 7031 184625 fax: +49 7031 185175 E-mail: mhafner@vnet.ibm.com 7 - 20 7. Equipment Assessment TCS 98 EP 22158 METEOR Metrology Equipment Test for Overlay Reading for Sub-micron Technology Summary The performance of the JMG overlay measurement tool ALARM 2 (evolution of ALARM 1, formerly supplied by Nanomaster) is to be assessed and improved at GRESSI, Grenoble, France. The overall equipment precision necessary to measure overlay figures as required by 0.18/0.25 micron IC technologies and 300 mm wafer handling capability are the main targets of the project Objectives To measure photolithography overlay with a high precision of 6-8 nm for the 60-80 nm overlay budgets used in 0.25/0.18 micron resolution lithography on 150 to 300 mm wafers. High throughput (90 wafers/hour, 5 points), good measurement performance of difficult grainy layers and flat CMP surfaces, and low added contamination (<0.01 particles./cm²/pass) are targeted. Evaluate fast measurement mode in two directions which calculates average overlay to suppress tool induced shift (TIS) bringing both improved accuracy and good long term repeatability. Participants GRESSI (F); JMG (F); MATRA MHS (F); IBM (F); CENTRE COMMUN CNET ST (F); AT&T (E). Contact Point Gilles FANGET GRESSI rue des Martyrs 17 F 38054 (France) Duration 12 months from 01.02.97 tel: +33 76 88 4918 fax: +33 76 88 3034 E-mail: Gilles.FANGET@macmel.ceng.cea.fr 7 - 21 7. Equipment Assessment TCS 98 EP 22205 ESAMA European scanning acoustic microscope assessment Summary The scanning acoustic microscope (SAM) developed by Ultrasonic Sciences Ltd. will be assessed. The equipment, which uses high frequency imaging and characterisation techniques will be evaluated for its improved capability for non-destructive inspection and investigation of plastic encapsulated semiconductor components. Generation of multiple images from a single scan will enable several fault features at different levels (die attach chip delamination, plastic voids) in the package to be examined simultaneously. Measurement features will be easily changeable during the assessment by using fast reprogrammable FPGAs in the DSP200 boards. Objectives To assess the mechanical scanning unit for high inspection rate, from single component to JEDEC tray size. To assess the ultrasonic instrumentation and software (new DSP board for gate peak detection). To evaluate the software for control and image generation/assessment. Participants ALCATEL MIETEC (B); ULTRASONIC SCIENCES (UK); ANALOG DEVICES (IRL); ANAM (KOREA) Contact Point Gust SCHOLS Alcatel Mietec Westerring 15 9700 Oudenaarde (Belgium) Duration 12 months from 01.04.96 tel: +32 55 332342 fax: +32 55 332647 E-mail: gu_schols@mietec.be 7 - 22 7. Equipment Assessment TCS 98 EP 22206 EMMEA Electromigration monitoring equipment assessment Summary The assessment of the DESTIN electromigration test system will be carried out by three semiconductor manufacturers. Normally high currents have been used to speed up electromigration test results but correlation with real-time results is poor. Here the approach is very accurate measurement of degradation resistance changed at low stress currents to give better correlation with real-time. Objectives To reduce test time in electromigration tests targeting low current 0.1 mA/cm², more appropriate to real life, and to perform very accurate measurement of resistance degradation at a very accurately held temperature ( = 0.0085 °C) to obtain credible results in about 10 days, and low costs per DuT (Device under Test). To establish a new standard for electromigration testing with reduced test time using insitu degradation monitoring, opening up a whole new family of reliability systems using the same principles. Participants ALCATEL MIETEC (B), DESTIN (B), PHILIPS (NL), SIEMENS (D) Contact Point Gust SCHOLS Alcatel Mietec Westerring 15 9700 Oudenaarde (Belgium) Duration 15 months from 01.04.96 tel: +32 55 332342 fax: +32 55 332647 E-mail: gu_schols@mietec.be 7 - 23 7. Equipment Assessment TCS 98 EP 22350 COTRED Cost of Test Reduction Summary The performance of the new generation ITS9000CV of Schlumberger will be assessed at the IC manufacturing facilities of SGS-Thomson in Rousset, France. To lower IC production costs it is the aim of the project to demonstrate cost of IC test reduction by a factor of two. Production batches of different ICs will be run and test costs will be compared between the ITS9000CV and the previous generation testing equipment of the same supplier. The evaluations will be done using two high volume products; one, a mixed function microcontroller, the other, a pure digital device. Objectives To prove the new generation ITS 900CV tester, which is specifically targeted at the microcontroller market, in the high volume production line of SGS-Thomson in Rousset. To demonstrate the effectiveness of the hardware and software developments achieved during previous projects. To reduce the ‘Cost of Test’ by a factor of two over the equipment’s predecessor. To compare ‘Cost of Test’ using ‘parallel by four’ of a ‘parallel by two’ format. Participants SGS-THOMSON (F); SCHLUMBERGER (F); MATRA MHS (F). Contact Point Herve DESHAYES SGS-Thomson ZI de Rousset (BP 2) F-13106 Rousset Cédex (France) Duration 10 months from 01.03.96 tel: +33 42 25 89 05 fax: +33 42 25 89 93 E-mail: hervé.deshayes@st.com 7 - 24 7. Equipment Assessment TCS 98 EP 24364 BAGINEA Ball grid array inspection equipment assessment Summary Ball grid arrays (BGAs) are a relatively new type of components, which offer numerous advantages over leaded components and are expected to grow strongly in the coming years. Annual growth rates of 50% are forecast. At present there are very few systems on the market for three-dimensional inspection of BGAs. They are all laser based and are adaptations of existing systems for inspection of leaded components. ICOS from Heverlee in Belgium, has developed an inspection technique which is dedicated to BGA packages and offers several major advantages over laser systems. The assessment of the LI-8250 3D BGA inspection system is to be carried out in the production environment of Mietec. The equipment will be benchmarked primarily against competing American equipment. Parameters to be assessed include accuracy, repeatability, throughput, mean-time-between-failure, uptake and change-over speed. A cost of ownership model will be defined. Objectives To evaluate the capability of the LI-8250 system to perform a 100% cost effective 3d inspection of BGA components. To prove the capability, accuracy and cost effectiveness of the system to perform as well 3D inspection of leaded components. To evaluate the change-over speed from one package type to another. To benchmark the equipment against competing inspection systems. Participants MIETEC (B); ICOS (B); SGS-THOMSON (F); ANAM INDUSTRIAL CO. (KR) Contact Point Gust SCHOLS Alcatel Mietec Westerring 15 Oudenaarde 9700 (Belgium) Duration 12 months from 01.02.97 tel: +32.55.332342 fax: +32.55.332647 E-mail: gu_schols@mietec.be 7 - 25 7. Equipment Assessment TCS 98 EP 26233 FANETA Failure analysis plasma etch equipment assessment Summary Failure analysis, on both packaged and unpackaged dies, is of crucial importance for a semiconductor manufacturer. Through results obtained from failure analysis, waferfab manufacturing processes are adapted and tuned in order to improve the yields. The etch process capabilities of the NE860 high density RIE/Microwave plasma etch system of Nextral are to be assessed . This system has been developed for sample preparation for ebeam measurements on new generation, deep-submicron products. It makes use of a microwave generated plasma with RF bias for dielectric depassivation down to 3 (or more) metal layers, while maintaining the full functionality of the product. Objectives To evaluate the capability of the NE860 system for the clean, anisotropic depassivation of packaged dies, while maintaining the full functionality of the product. To evaluate the capability of the system for reverse engineering of wafers up to a diameter of 200 mm for deep-submicron technologies with geometries down to 0.25 and below and with up to 6 metal layers. To evaluate the capability of the system for localised backside thinning of packaged dies for IR inspection or light emission microscopy. To evaluate the capability of the system for selective deprocessing of packaged dies, for failure analysis. To benchmark the equipment against competition systems. Participants MIETEC (B); NEXTRAL (F); SGS-THOMSON MICROELECTRONICS (F); SIEMENS (D). Contact Point Duration Dr. Gust SCHOLS Alcatel Mietec Westerring 15 B-9700 OUDENAARDE (Belgium) 12 months from 01.01.1998 Tel: +32 - 55 33 23 42 Fax: +32 - 55 33 26 47 E-mail: gu_schols@mietec.be 7 - 26 7. Equipment Assessment TCS 98 EP 23657 SEA 300 SEA 300 Summary International and national initiatives as I300I in Austin (US) and SELETE in Yokohama (Japan) have been launched to ensure 300 mm semiconductor manufacturing equipment is available at the right time at lowest possible costs and risk. The equipment to be demonstrated as well as the still very expensive 300 mm silicon wafers are expected to be provided for free. Under these conditions only a few European equipment suppliers are able to participate in such demonstration tests in different places in the world. Many of them need tests and the corresponding services also in Europe. As part of the SEA initiative SEA 300 offers the European equipment companies a phased and effective path to 300 mm activities. Objectives The overall objective of the SEA 300 initiative is to support demonstration of European semiconductor manufacturing equipment in the global conversion process to 300 mm wafer processing. This will be done by Attraction of IC manufacturers from all over the world to Demonstration Test sites, Provision of 300 mm wafer (blank and processed), metrology and analytical services, Dissemination of equipment test results to potential customers. To reach the above mentioned objectives a Dissemination Centre will be established at RAL (UK) and a Service Centre at GRESSI (F). Participants RUTHERFORD APPLETON LABORATORY /RAL/ (UK); GRENOBLE SUB-MICRON SILICON (GRESSI) (F). Contact Point SEA / SEA 300 Office Central Microstructure Facility Rutherford Appleton Laboratory Chilton, Didcot, Oxfordshire, OX11 OQX, (United Kingdom) Duration 18 months from 01.01.97 tel: +44 1235 445946 fax: +44 1235 446174 E-mail: sea@rl.ac.uk World Wide Web: http://www.ebl.rl.ac.uk/sea.html 7 - 27 7. Equipment Assessment TCS 98 EP 25991 FLASH PT 300 Future leadership through assessment of high quality production tool for 300 mm Wafers Summary The project is to assess the Plasmos SD 3000 fully automatic ellipsometer tool for the future 300 mm market and to improve its present performances. The assessment has been organized such that two units are being evaluated at the same time: one to be installed at SELETE, in Yokohama, Japan and a second one, fully automatic, to be installed first at I300I, in Austin, USA, and thereafter at GRESSI to complete the evaluation and implement the improvements. The final outcome of the project will be a reliable 300 mm ellipsometer ready to be used at industrial semiconductor manufacturers facilities for in line control of IC fabrication process on 300 mm silicon wafers. Objectives To measure and evaluate the capabilities for: thin/thick single and complex multilayer structures. monolayers, multilayers, absorbing films, thin metal films, rough films, small spot size patterned wafers. wafer handling ability with SMIF, open 13 wafer cassette, open 25 wafer cassette, double sided polished wafers, and with the new standard FOPOD. the operation of the system in its fully automatic configuration the interface with CAM systems at the fabrication facilities. Integration in production logistics the productivity: throughput, cost of ownership Participants: GRESSI (F); PLASMOS (D); SGS THOMSON MICROELECTRONICS (F), I300I (USA), SELETE (J) Contact Point Guillermo Bomchil France Telecom Cnet BP 98. 38243 Meylan Cedex France tel: +33 4 76 76 42 22 fax: +33 4 76 90 34 43 E-mail: guillermo.bomchil@cnet.francetelecom.cnet Duration 18 months from 01.07.97 7 - 28 7. Equipment Assessment TCS 98 Basic Services and First Users Action EP 21101 EUROPRACTICE BASIC SERVICES Promoting Access to Microelectronics Technologies Summary By incorporating modern microelectronics technologies in their products, companies can enhance production efficiency, reduce cost, improve product performance, reduce size weight and power consumption or gain product differentiation through new functionality. EUROPRACTICE offers a cost-effective and flexible means of accessing ASICs, MCMs and microsystems technologies (MST) with software support and complemented by training and best practice courses; through the provision of consultancy, training, software tools, design support, prototyping, low-volume production runs, packaging and test, and access to “normally” internal volume production facilities. The costs of developing ASICs and MCMs for dedicated applications with low-volume production are often prohibitively high, especially for SMEs. Multi Project Wafer (MPW) runs and dedicated low-volume MCM and MST services offer a cost-effective route to ASIC, MCM and MST design and fabrication. The cost, complexity and expertise required to develop microsystems components or Microsystem based products often present a barrier to the introduction of this technology. Services providing solutions and knowledge in a globally integrated manner including a path from feasibility studies and prototyping through to high volume production are offered. Design, microsystems process technology, as well as packaging and integration of the microsystems component in the final product or system are all covered. EUROPRACTICE Basic Services will reduce the cost and risk for companies who wish to begin using these technologies and for academic institutes who wish to include these technologies in their educational offer. General enquiries may be addressed to the contact point below, from which reference to the best contact for further detailed information may be obtained. Objective The overall objective is to stimulate wider exploitation of state-of-the-art microelectronics and microengineering technologies by European industry. Contact Point Dr Brian JONES Europractice Coordination Office Rutherford Appleton Laboratory Didcat OXII OQX (United Kingdom) Duration 36 months from 01.10.95 tel: +44 1235 445451 fax: +44 1235 446283 Email: brian.jones@ral.ac.uk http://www.europractice.com 8-1 8. Basic Services and First Users Action TCS 98 EP 21963 FUSE First Users Action Summary The main instrument for achieving the goals of FUSE is a funded Application Experiment (AE). In these experiments, an enterprise will carry out the design, manufacture and test of a component which is relevant to the improvement of their manufactured products. A vital principle of FUSE is that the participating enterprise acquires the necessary know-how (via collaboration with subcontractors) and experience to access and use microelectronics technologies themselves. The secondary instruments are the Technology Transfer Nodes (TTNs). These nodes are established in regions throughout Europe to provide a local interface to participating enterprises. They proactively seek enterprises in all industry sectors and at all levels of the ‘technology ladder’ and offer technical and economic expertise to assist them in their selection and application of technologies. In addition to the benefits gained by the funded enterprise, FUSE aims to capture and disseminate the essentials of AEs to encourage other enterprises to adopt microelectronics technologies as a means of improving competitiveness. It is the task of the TTNs to extract the essentials of the AEs which they monitor, and use these in order to create awareness of the benefits of microelectronics technologies. Objectives FUSE has the global objective of broadening the use of microelectronics technologies by all sectors of European industry; it means of achieving this is to produce and disseminate “demonstrators” (i.e., case studies drawn from Application Experiments) of the benefits of these technologies. Participants A EUROPEAN-WIDE NETWORK COMPRISING THE TTNS AND MORE THAN 400 ENTERPRISES, MOST OF WHICH ARE SMES WHICH PARTICIPATE IN APPLICATION EXPERIMENTS . Contact Point Mohamed Wahab University of Glamorgan Mid Glamorgan UK-Pontypridd (United Kingdom) Duration 36 months from 01.01.96 tel: +44 1443 482542 fax: +44 1443 482541 Email: mawahab@glamorgan.ac.uk 8-2 8. Basic Services and First Users Action TCS 98 Networks and Working Groups EP 21949 ACiD-WG Working Group on Asynchronous Circuit Design Summary ACiD-WG coordinates research, training and dissemination activities in Europe concerned with the design of asynchronous digital VLSI circuits. Demonstrator chips, such as those designed on OMI/EXACT (EP6413) and OMI/DE-ARM (EP6909), indicate that asynchronous circuit techniques can help reduce power consumption and electromagnetic radiation. Current sister-projects include OMI/DE2 (EP20452), PREST (EP25242), AMIED (EP25249) and DESCALE (EP25519). The ACiD-WG Technical Management Committee (TMC) consists of ten distinguished European Scientists who have applied their expertise in the fields of computer architecture, DSP, silicon compilation, logic synthesis and formal methods, to the asynchronous domain. European companies are encouraged to becomes ACiD-WG Industrial Affilates. Objectives Facilitate research and technology transfer activities undertaken by the TMC Organise European workshops for regular exchange of information and discussion between research teams and industry. Organise a European summer school aimed at university students, young researchers and practising engineers. Sponsorship of Async97 and Async99, International Symposia on Advanced Research in Asynchronous Circuits and Systems. Event ACiD-WG workshop Async97 ACiD-WG summer school ACiD-WG workshop ACiD-WG workshop Async99 Date 9-10 September 1996 7-10 April 1997 18-22 August 1997 26-27 January 1998 late 1998 April 1999 Venue Groningen Eindhoven Lyngby Turin Newcastle upon Tyne Barcelona Participants SOUTH BANK UNIVERSITY (UK); PHILIPS RESEARCH LABORATORIES (NL); TELECOM BRETAGNE (F); POLY. OF CATALONIA (E); UNIV. OF GRONINGEN (NL); UNIV. OF MANCHESTER (UK); POLY. OF TURIN (I); EINDHOVEN UNIV. OF TEC. (NL); TECH. UNIV. OF DENMARK (DK); UNIV. OF NEWCASTLE UPON TYNE (UK). Contact Point Dr. Mark B. Josephs Centre for Concurrent Systems and VLSI School of CISM, South Bank University 103 Borough Road, London SE1 0AA, UK Voice +44 171 815 7413 Fax +44 171 815 7499 Email Mark.Josephs@sbu.ac.uk URL http://www.scism.sbu.ac.uk/ccsv/ACiD-WG Duration 36 months from 01.05.96 9- 1 9. Networks and Working Groups TCS 98 EP 20796 GOOD-DIE NETWORK Get Organised Our Dissemination of Die Information in Europe Summary The current acceleration of MCM development is led by the need in electronics packaging for increased integration, reduced size and weight, increased reliability, reduced cost and increased performance. One of the major factors in MCM design is the use of new technology and very high I/O ICs such as microprocessors and ASICs with many thousands of gates. For memories and other devices, the technology is shrinking to 0.5, 0.35 and even 0.25 micron. The use of these new technologies affects the device yield; the higher the number of die per MCM, the greater the risk of low first time yield and the need to rework. In order that the manufacture of these high density MCM electronic modules be costcompetitive with current electronic manufacturing technology, Known Good Die, KGD sourcing must be possible. If the KGD concept is accepted internationally, it will also reduce the costs of single die packaging due to the higher yield of the die. To assist in achieving these requirements, this project is set up to create an information exchange network open to all semiconductor manufacturers, systems designers, MCM manufacturers and users, CAD vendors, standards organisations, etc. for the exchange of information on KGD. This will be based at a technical organisation who will assist in the organisation of seminars, workshops, task forces, a newsletter etc. as the knowledge base for KGD. (See also EP 20797 GOOD-DIE.) Objectives Create a network with an open membership list. Set up a programme of meetings, seminars, etc. for information exchange. Give presentations at other conferences, seminars, etc. on KGD information. Make contacts with other MCM and electronic EUROPRACTICE-MCM, NETPACK, JESSI, MCC etc. Issue a newsletter on KGD and associated topics. Create contacts made with standards groups to maintain continuity. Exploit the need for KGD and the use of the databases. packaging groups, e.g. Participants CODUS (UK), IMEC (B), PHILIPS (CH), ELTEK (UK), ROOD TECHNOLOGY (NL) Contact Point Mike G. ROUGHTON CODUS 142 Colebrook Road Sharley Solihull B90 1BX (United Kingdom) Duration 30 months from 01.12.95 tel: +44 121 693 3116 fax: +44 121 693 3116 E-mail: mroughton@fdgroup.co.uk 9- 2 9. Networks and Working Groups TCS 98 EP 21468 NETPACK Network of Excellence in Microelectronics System Integration Technologies - Packaging Summary Packaging and interconnection technology is essential for the realisation and manufacturing of all electronic equipment. It also determines to a large degree the overall system engineering approach which is adopted, including design, assembly and test. During the last few years packaging and interconnection has received growing attention from the industry as a way to achieve system integration: The spectrum of existing technological approaches is becoming broader with the incorporation of emerging types of construction and innovative combinations of materials and processes. To make the best use of the capabilities of assembly technologies, system manufacturers need to have access to - and master - a variety of technological routes. In all cases a thorough understanding of the available techniques, their strengths and weaknesses, their impact on performance and reliability, and very particularly the associated cost aspects are essential from the component, subsystem and system producers to succeed in world markets. Objectives Identify packaging activities in Central and Eastern European countries and potential areas for cooperation. Presentation and publication of "European Packaging" journal. Contribute to the conception of European R&D programmes. Develop technology roadmaps for different packaging applications. Establish a packaging communication electronic network. Present status and future evolution of CSP (Chip Scale Packages). Establish links with Known-Good-Die action and Europractice-MCM. Organise NETPACK sessions in conjunction with major events on Packaging and Interconnection. Participants FHG-IZM (D), BULL (F), BPA (UK) COMBITECH ELECTRONICS DANFOSS A/S (S), DOW EUROPE SA (CH), ES2 (F), GEC MARCONI (UK), IMEC (B), IBM (D), IMC (S), LETI (F), LUCAS (UK), M+S HOURDAKIS (GR), MAGNETI MARELLI (I), NCSR DEMOKRITOS (GR), NOKIA (SF), PICOPAC (I), SGS-THOMSON (UK), VDI (D), VTT ELECTRONICS (SF) Contact Point Professor Herbert REICHL FHG-IZM Gustav-Meyer-Allee 25 1000 Berlin 65 (Germany) Duration 24 months from 01.05.96 tel: +49 30 314 72882 fax: +49 30 314 72835 9- 3 9. Networks and Working Groups TCS 98 EP 20307 SYSLINK Documentation and Dissemination Service for Electronic System Design Summary The main objective of this Dissemination Activity is to disseminate the results of ESDprojects, both of Application Experiments and of Demonstration Projects to the electronic system design community in Europe. For this purpose, there is first a process for collecting information on applied methods and tools, approaches used and experiences gained. This may include novel design methods and tools from CAD vendors and stable prototypes from European research activities. This information is then made available by various means to the participants of ESD projects and later also to a wider electronic community with emphasis on SMEs in Europe. Objectives To promote and encourage the widespread use of advanced ESD technology in Europe with emphasis on users from SMEs. To build up a broad level of know-how on ESD methods and tools including their merits and shortcomings with respect to a wide area of practical applications. Help to improve the quality and efficiency of system design products on a larger scale. Contribute to shorten the learning curve for new system designers resulting in shorter time-to-market products at a higher level of product quality. Bring together potential partners for technological cooperations across Europe to achieve improved competitiveness of European industries on international markets. Participants GERMAN NATIONAL RESEARCH CENTRE FOR INFORMATION TECHNOLOGY, GMD/SET, (D); POLITECNICO DI TORINO, (I); UNIV. JOSEPH FOURIER, (F) Contact Point Karl H. GLAESSER GMD/SET P.O. Box 1240 D 53757 Sankt Augustin (Germany) Duration 24 months from 01.12.95 tel: +49 2241 142048 fax: +49 2241 142342 Email: glaesser@gmd.de Internet: http://set.gmd.de/SYSLINK 9- 4 9. Networks and Working Groups TCS 98 EP 21972 EARNEST ECSI Awareness Reflection Network for Electronic System Design Standards Summary The awareness of existing Best Practice and modern design and development methods is crucial for European industry products competitiveness in terms of time-to-market, quality and reliability. EARNEST is a European-wide dissemination activity aimed at the promotion of awareness of existing Best Practice, tools, methods and standards in the domain of electronic system design (ESD). It will provide information, advice and promotion of the collected and processed material in order to ensure that European companies, varying from large multi-nationals to SMEs, have appropriate access to Best Practice experience and standards related information. Objectives Collection of the material to be disseminated in paper and electronic form from ECSI Industrial Members, from other Dissemination Actions, standardisation organisations, user groups and other relevant sources. Classification of the information to match the target audience needs. Dissemination of the material to the targeted audience in a packaged and directed form. Preparation of workshops for European Best Practice projects participants. Preparation of Executive Digests of the material. Provision of a coordinated mechanism to access the documentation. Support of other EC projects, including Application Experiments, Demonstration Projects and other projects supported under the Framework IV Programme, through dissemination activities and consultancy. Participants ECSI (F), TUW (A), UM (GB), UPM (E), KTH (S), EPFL (CH). Contact Point European CAD Standardisation Initiative Parc Equation 2, avenue de Vignate F-38610 Gières (France) Duration 12 months tel: +33 76 63 49 34 fax: +33 76 42 87 87 Email: ecsi@grenet.fr, office@ecsi.alpes-net.fr 9- 5 9. Networks and Working Groups TCS 98 EP 20713 NEXUS Network of Excellence in Multifunctional Microsystems Summary The network of excellence NEXUS provides an industrial and academic forum to accelerate the dissemination of information using microsystem technology (MST) in industry in order to secure the European position during the industrialisation phase of MST. The organisation consists of an industrially led board, an academic working group and four user clubs headed by industrial chairpersons. FHG ISiT provides a general coordination and runs the NEXUS office. Objectives Provision of an industrial forum and appropriate infrastructure to facilitate the interdisciplinary cooperation that is needed to design and manufacture products using microsystem technology. Systematic identification of specific application opportunities by organisation of industrially driven user clubs in all important fields of applications. Elaboration of long-term perspectives for R&D and providing inputs to the growing number of private and public initiatives. Establishment of a common European MST representation at European and international forums, and in international events including the initial world-wide discussions on standardisation. Establishment of a world wide web based MST information network and monitoring of progress in MST on a world-wide scale. Organisation of publicity and awareness activities in the field of MST. Organisation of task forces to address specific MST related issues such as, production equipment for MST. Executive Board members and coordinator only: FHG ISIT (D), SEXTANT AVIONIQUE (F), GEC-MARCONI (UK), SENSONOR (N), SCHLUMBERGER-GEM (F), CRL (UK), DAIMLER-BENZ (D), MICROPARTS (D). Contact Point Dr. Hans-Christian PETZOLD FHG ISiT Dillenburger Strasse 53 D 14199 Berlin (Germany) Duration 15 months from 01.10.95 tel: + 49 30 82 998 110 fax: +49 30 82 998 199 9- 6 9. Networks and Working Groups TCS 98 9- 7 9. Networks and Working Groups TC S 98
