Licensing Opportunity
from the University of Rhode Island
Cache memory system for vector processing
Description of Invention: A cache memory system for use during vector processing in a processor.
The processor contains a central processing unit (CPU) and a main memory. The system includes a vector
cache memory, a first address register, a main memory address calculation unit, and a cache address
calculation unit. The first register stores a first address associated with an instruction executed by the CPU.
The main memory address calculation unit is coupled to the first address register for calculating a second
address utilizing the first address and vector stride data associated with said executed instruction. The
second address is utilized to access the main memory. The cache address calculation unit is coupled to both
the first address register and the main memory address calculation unit for calculating the third address
utilizing portions of the first address and portions of the second address. The third address is utilized to
access the vector cache memory.
Potential Areas of Application:
1) The invention relates to information processors involving cache memory systems, and specifically to
cache memory systems for use in vector processing. The research for this invention was supported,
in part, by National Science Foundation Grant No. CCR-8909672.
Main Advantages of Invention:
1) The invention relates to a new cache system, referred to as prime-mapped cache, which is designed,
in part, to minimize cache miss ratio in vector processing (with scalar or vector processors). A primary
feature of the design is that memory data are mapped into cache lines according to a Mersenne
prime. The cache access logic of the mapping scheme operates in virtually the same time period as
direct-mapped cache, resulting in no additional delay for cache accesses.
2) The address generation for the cache takes no longer than the normal address calculation time for
main memory due to the special properties of the Mersenne number as utilized in the present
invention. The generation of addresses for cache access is done in parallel with normal address
calculations resulting in no performance penalty. Thus, it has the advantages of both direct-mapped
cache and fully associative cache if replacement is not considered.
Lead Inventor:
Qing Yang, Electric, Computer & Bio Engineer
Status:
U.S. application 07/882,857 filed May 14, 1992 issued U.S. patent 5,379,393 on January 3, 1995
Cache Memory System USPTO Website Link
Category: Computers and Displays
Licensing Status:
Available for licensing
Reference #:2375
Please contact David R. Sadowski or Raymond Walsh - Division of Research & Economic Development, University of Rhode Island,
75 Lower College Rd. Suite 001, Kingston, RI 02881; 401-874-4807 or Fax 401-874-7832
http://www.uri.edu/research/tro/executive/sadowski.html
Rev. 01-14-10