Statement of Purpose I am applying for the Ph.D. student position in the Department of Electrical Engineering and Computer Science of MIT. I love the area of nano-electronic devices and enjoyed very much in my research projects. In the past three years, I have worked in Nano-Devices and Integrated Circuits Research Group of Peking University and working on projects including simulation, characterization, modeling and fabrication of nano-systems. Till now, I have authored or co-authored 17 scientific papers in international journals and conference, including two papers published in IEDM 2008 and VLSI Symposium 2009 as the first author. Physics background: In my point of view, physics background is one of the most essential factors for a researcher of semiconductor devices, since a clear understanding of device physics provides a conceptual framework for interpreting experiments and guiding device design. I was selected as the member of national training team (19/300,000) for the 34th International Physics Olympiad (IPHO), and soon became an undergraduate student in School of Physics in Peking University. I took the initiative to read the classical physics textbook “Modern Quantum Mechanics” (by J.J.Sakari) in order to build a quantum way of thinking, read "Introduction to Solid State Physics" (by Kittle) to master crystal structures, the energy band theory and get to know the surface effect for nano structures. Then I extended my reading to courses on Nanohub.com to be acquainted with ballistic transport, NEGF method and first principle calculation. Through advanced books and literatures, I get familiar with electron-phonon interaction and hall effect in nanosized sturcture, k*p method to calculate energy band, the fully tunneling effect in the transport of grapheme, and etc. Based on these experiences, I can think both in a combined way of both engineering and physics when facing real problems in my future research. Research experiences: Since 2006, I joined Prof. Ru Huang’s Nano-electronic Devices and Integrated Circuits research group and received systematic training in research of devices. The continuous scaling of silicon devices are facing several major issues, they are: 1) poor gate electrostatic control; 2) high gate leakage; 3) reduced channel mobility; 4) increased source/drain resistance. These issues cause higher off-state leakage and limit the drive current leading to compromised performance, defeating the main purpose of scaling. Gate-all-around silicon nanowire devices (SNWT) provide (1) the excellent electrostatics, (2) capability of being realized from both top-down and bottom-up approaches, (3) possibility of 3D integration, (4) possibility of new applications and markets, for example, memory, bio, medical, energy, green electronics, and etc. They have been considered as one of the most probable candidate for the next generation devices, so that I decided to choose nanowire devices as my research area. By then, most of the investigations that are performed on SNWTs have focused on their dc characteristics and fabrication, while their potentials in RF applications have not been reported, so that I choose simulation on the RF performance of nanowire devices as my first project. In this project, Analog/RF behavior and impact on device parameter variation are simulated by Synopsys TCAD Sentaurus Device simulation tools, with a carefully calibrated 3-D density-gradient drift diffusion model for corrections of sub-band induced band broadening and quantum transport through the channel. Results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. However, performance of SNWTs suffered a lot from the large parasitic resistance of their ultra-narrow S/D extension. As a result, Schottky Barrier Nanowires (SB-NWTs), which replace the doped S/D and extension to silicides/metal, was proposed with the original purpose to reduce the S/D series resistance. However, so far, both experiments and simulation show weak performance of SB-NWTs compared with silicon nanowires. I then chose my second topic as the simulation of SB-SNWT to evaluate the performance limit of this kind of devices. This work was also performed with Santaurus and a Non-local tunneling model with corrected tunneling mass was selected, without consideration of the mirror barrier lowering effect, since result with this model is closer to the results got by Air Function method. Based on the results, I proposed a new embedded dopant segregation approach to effectively improve the on-current of SB-FETs. I have chosen Ni/Si and Ni/Ge Metal-Semiconductor junction to comparatively perform the proposed approach and the experiments are under progress. Since the reliability issues are among the most important problems for ultra-small devices, I decided to work on the Experimental study on Negative Bias Temperature Instability (NBTI) effect of SNWTs as my next topic. In summary, by analyzing the degradation of gate current, I have demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanowire structure due to multiple surface crystal orientations of the cylinder nanowires. Quite different from conventional planar devices, both stress and recovery of NBTI in SNWTs are evidently impacted by electron trapping/detrapping behavior, due to the enhanced electrical field with cylinder surrounded gate, increased electron traps in the gate dielectrics and electron injection from metal gates. Considering electron/hole trapping and detrapping behaviors, a empirical NBTI model is proposed for SNWTs with metal gates for further understanding of NBTI in nano-scaled devices. The generation of new-born trap-precursors in the gate dielectrics of SNWTs was also observed and the generation kinetics is discussed. These new-born precursors can be converted into traps after experiencing a grounded recovery phase and a pulse state, leading to additional unexpected reliability degradation of SNWTs. However, the detailed NBTI mechanism in SNWTs with quasi-1D channel is still far from fully understood, as well as the NBTI induced device performance fluctuation and the resulting degradation of circuit FOM(figures of merit).I continued this work and performed extended research on this issue. I comprehensively investigated the NBTI behavior of the device both experimentally and theoretically, taking into account of the 2-D axial H/H2 diffusion, multiple crystal orientation, non-uniform heating profile and quantum effects in the unique quasi-1D structure of GAA SNWTs. With my newly-proposed and verified NBTI model and parasitic capacitance model for SNWT, NBTI-induced threshold voltage (Vt)-mismatching and typical circuit degradation is estimated, combined with the measured performance fluctuation of fresh devices. The impact of crystal orientation, oxide traps and gate trimming process on typical logic and analoge circuits was also evaluated quantitatively, which can provide the design guidelines for nanowire-based circuit reliability improvement. Our results shed new light into NBTI effects on the properties of Silicon, and further investigations are underway to build a more detail NBTI model for SNWTs. As I discussed above, the performance of ultra-scaled devices is highly affected by localized effects such as random trapping behavior. Random telegraph signal (RTS) noise caused by single carrier trapping/detrapping within the gate stack has provided the unique opportunity to study the trapping and detrapping behavior of traps in deep-nanometer SNWTs. I found the observed RTS in SNWT is found to have Coulomb-blockade characteristics rather than those described by conventional Shockley–Read–Hall theory. The capture and emission time constants of oxide traps strongly depend on the gate bias due to strong quantum confinement and enhanced electrical field in nanowire structures. Amplitude of single RTS in SNWTs is found within 10%, while large amplitude of multilevel RTS up to 34% at room temperature is observed due to the ultranarrow channel and the behavior of independent multitraps in SNWTs. Then I invented a newly-developed combined Ig-Id RTS technique, which overcome the drawbacks of traditional Id RTS technique that can only investigate majority carrier traps in MOSFETs. I used this method to separately investigate the electron and hole traps in the gate stacks of SNWTs. Based on corrected RTS model for gate-all-around (GAA) SNWT structure, the locations, time constant, activation energy and capture cross sections of traps in SNWTs are extracted. In addition, two kinds of oxide hole traps that can cause Id RTS are observed. The results can help further understanding of the physical properties of the oxide traps in SNWTs. Meanwhile, I broadened my research interest to high-k gate stack devices, which enables EOT continue reducing without a gate leakage current penalty when CMOS devices scale down to the 45nm node and beyond. In this project, further results and in-depth study on Ig RTS noise in SiON/HfO2/TaN gate stack PMOSFETs are reported. Single carrier trapping/detrapping in the high-k/metal gate stack under NBTI stress is observed for the first time. The location of traps, the impacts of gate bias, temperature and substrate bias are discussed for understanding the RTS mechanism in high-k devices. Moreover, during long time stress, an abrupt change of amplitude of Ig fluctuation and the mean capture and emission time is also observed for the first time, which can be probably attributed to the slow trap or the generation of the new trap in HfO2 layer. Moreover, besides RTS, I have invented a new method to use flicker noise method to analyse the impact of oxide traps in High-k/Metal gate stack devices. This project is currently under way. Besides these projects I mentioned above, I also take my initiate to take part in other works, such as: (1) Experimental investigations on channel backscattering characteristics of gate-all-around silicon nanowire transistors from top-down approach; (2) Carrier transport in silicon nanowire transistors; (3) Impact of one dimensional to three transition and the optimization of S/D contact in SNWT; (4) fabrication of Gate-all-around nanowire devices on bulk and SOI substrate with top-down process; (5) Characterization and modeling of NBTI in nanowire devices with on-the-fly measurement method; (6) Simulation on the impact of LER of nanowire devices;(7) Modeling of gate current of SNWT devices.