DESIGN Near-Term Difficult Challenges > 65nm, < 2007
Difficult Challenges
Near-Term
1. Design Process
Design sharing/reuse for
geographically distributed and
multi-company design projects
Increased design complexity and
frequency with shrinking feature
size
Time-to-market for cost-driven
SOC
2. System-Level
Growing size and complexity
SOC with diverse design styles
Summary of Issues
 Integration of mixed multi-vendor and internal design technology (MPU, SOC)
 Standard information model for IC design data w/standard interface adopted across tools,
databases
 Tool integration minimizing data translation time and redundancy
 Incremental analysis and optimization capability for constraint-dominated design
 Concurrent execution of design and analysis tools to reduce design cycle times
 Technology models controlled by process owner w/common interpretation by design,
analysis tools
 Common information models to support reuse and design space exploration (SOC)
 Design rules to assure reusability, design and validation tools to assure these rules (SOC)
 Design flow integration for hardware/software, digital/analog, MEMS, memory, design tools
(AMS)
 Analog design synthesis comparable to digital RTL-based synthesis (AMS)
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Embedded software as a key design problem (SOC)
Core and IP-reuse based design methodology and integration standards (SOC)
Managing large, collaborative, multi-skilled, geographically distributed teams (SOC, MPU)
Interacting design levels with multiple complex design constraints (SOC)
Specification and estimation at all levels (MPU, SOC, AMS)
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Formal methods for system-level verification (MPU, SOC)
SOC specification (SOC)
Early high-level timing verification (SOC, MPU)
Verification of heterogeneous systems including AMS, MEMS (SOC)
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Variability (mfg, thermal, etc.) impact on parametric yield and performance verification
Development of new logic families to meet performance challenges (MPU)
Scalability of performance verification methodologies (MPU)
Atomic-scale effects (MPU)
Full leverage of new process innovations (Cu, Low-K, SOI, …) (MPU, SOC)
Convergence and predictability of system implementation process (SOC)
Interacting design levels with multiple complex design constraints (SOC)
Electrical/manufacturing aware technology remapping and migration to maintain
productivity (SOC)
Synthesis of high-quality analog, optical interface, embedded passive building blocks
(AMS,SOC)
Improved test tools for advanced (open, delay, etc.) fault models (MPU, ASIC/SOC)
Continuation (avoidance) of at-speed func test w/ increased clock frequencies (MPU,
(ASIC/SOC))
Signal integrity (noise, capacitive/inductive coupling, etc.) testability (MPU, ASIC/SOC)
DFT to enable low-cost ATE (MPU, ASIC/SOC)
Non-intrusive logic BIST (including advanced fault models) (MPU, ASIC/SOC)
Fault diagnosis and design for diagnosability (MPU, ASIC/SOC)
Power and thermal management during test (MPU, ASIC/SOC)
Test of core-based designs from diverse sources including AMS, RF (SOC)
At-speed structure test with increased clock frequencies (MPU, ASIC/SOC)
Yield improvement and failure analysis tools and methods (ASIC/SOC)
Fault models for analog (parametric) failures (AMS)
AMS DFT/BIST, especially at beyond-baseband frequencies (AMS)
DFT, BIST and test methods compatible with SOC core-based environment and constraints
(AMS)
Test and on-chip measurement techniques for multi-gigahertz serial ports (AMS)
Chip-package co-analysis/opt
3. Functional Verification
Equivalence checking between
design levels (esp. system to RTL)
Comprehensive approaches to
core-based SOC design
verification incl. AMS
4. Logical, Physical, Circuit
Large numbers of interacting
devices and interconnects
Cost-driven design for signal
integrity, noise, reliability and
manufacturability
Dynamic and static power
management, clock distribution
5. Test
At-speed test with increasing
frequencies
Capacity gap b/w DfT/Test
generation/fault grading tools and
design complexity
Quality and yield impact due to
test equipment limits
Signal integrity testability and
new fault models
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DESIGN Long-Term Difficult Challenges < 65nm, > 2007
Difficult Challenges
Long-Term
1. Design Process
2. System-Level
3. Functional Verification
4. Logical, Physical, Circuit
5. Test
Summary of Issues
 Higher-level verification of function, performance, manufacturability (SOC, MPU)
 Synthesis of mixed-tech designs (including analog) comparable to digital RTL-based
synthesis (AMS)
 Total system integration including MEMS, EO, chemical, biological (SOC)
 Design techniques for fault-tolerance (MPU)
 Embedded software and on-chip operating system issues (SOC)
 Physical verification of novel high-frequency interconnect (optical, RF, 3D) (SOC)
 Verification for novel devices (nanotube, molecular, chemical) (SOC)
 Unified chip-package analysis and optimization
 Design under uncertainty of fundamental chip parameters (e.g., signal skew) (MPU)
 Design with novel devices (multi-Vt, 3D-layout, SOI) and technologies (MEMS, bio)
(MPU, SOC)
 Physical and communication architectures for SOC implementation fabrics
 Logic implementation to deal with single-event upset (MPU, SOC)
 True one-pass optimization flow with incremental and partial design specification (MPU,
SOC)
 Seamless integration of design and manufacturability for reliability and yield (MPU, SOC)
 Adaptive and self-correcting circuits (MPU, SOC)
 Extremely low-power sensing, sensor interface circuits (AMS, SOC)
 Self-repairing circuit technologies
 Test of multi-gigahertz RF front ends on chip (AMS)
 Utilizing on-chip programmable resources for SOC self-test (SOC)
 Diagnosis and failure analysis for AMS parts (AMS)
 Design for efficient and effective burn-in to screen out latent defects (MPU)
 Dependence on self-test solutions for SOC with RF, AMS components (SOC)
 New timing-related fault models for defects/noise in UDSM technologies (MPU,
ASIC/SOC)
 Quality and yield impact due to test equipment limits (MPU, ASIC/SOC)
 DFT and fault tolerant design for logic soft errors (MPU, ASIC/SOC)
 (Analog) signal integrity test issues caused by noise from digital to analog circuitry (AMS)
 Test methods for heterogeneous SOC including MEMS and EO components (SOC)
 Logic self-repair utilizing on-chip reconfigurability (SOC)
 System-level on-line testing (SOC)
DESIGN PROCESS
NEAR-TERM
Integration of mixed multi-vendor and internal design technology (MPU, SOC)
Design sharing/reuse for geographically distributed and multi-company design projects (SOC, MPU)
Standard information model for IC design data w/standard interface adopted across tools, databases
Address increased design complexity and frequency with shrinking feature size
Tool integration minimizing data translation time and redundancy
Incremental analysis and optimization capability for constraint-dominated design
Concurrent execution of design and analysis tools to reduce design cycle times
Technology models controlled by process owner w/common interpretation by design, analysis tools
Address time-to-market for cost-driven SOC
Common information models to support reuse and design space exploration (SOC)
Design rules to assure reusability, design and validation tools to assure these rules (SOC)
Design flow integration for hardware/software, digital/analog, MEMS, memory, design tools (AMS)
Analog design synthesis comparable to digital RTL-based synthesis (AMS)
LONG-TERM
Higher-level verification of function, performance, manufacturability (SOC, MPU)
Synthesis of mixed-tech designs (including analog) comparable to digital RTL-based synthesis (AMS)
SYSTEM-LEVEL
NEAR-TERM
Growing size and complexity (MPU, SOC)
Embedded software as a key design problem (SOC)
SOC design with a diversity of design styles (MPU, SOC, AMS, RF, MEMS, EO)
Analysis and optimization across chip-package boundary (AMS, MPU, SOC)
Core and IP-reuse based design methodology and integration standards (SOC)
Managing large, collaborative, multi-skilled, geographically distributed teams (SOC, MPU)
Interacting design levels with multiple complex design constraints (SOC)
Specification and estimation at all levels (MPU, SOC, AMS)
LONG-TERM
Total system integration including MEMS, EO, chemical, biological (SOC)
Design techniques for fault-tolerance (MPU)
Embedded software and on-chip operating system issues (SOC)
FUNCTIONAL VERIFICATION
NEAR-TERM
Equivalence checking b/w design levels, esp. system (SystemC, SpecC, etc.) to RTL (MPU, SOC)
Formal methods for system-level verification (MPU, SOC)
SOC specification (SOC)
Early high-level timing verification (SOC, MPU)
Comprehensive, systematic approaches to core-based SOC design verification including AMS (SOC)
Verification of heterogeneous systems including AMS, MEMS (SOC)
LONG-TERM
Physical verification of novel high-frequency interconnect (optical, RF, 3D) (SOC)
Verification for novel devices (nanotube, molecular, chemical) (SOC)
LOGICAL, PHYSICAL, CIRCUIT
NEAR-TERM
Large numbers of interacting devices and interconnects (MPU, SOC)
Cost-drive design for signal integrity, noise, reliability, manufacturability (MPU, AMS, SOC)
Dynamic and static power and current management, clock distribution (MPU, SOC)
Variability (mfg, thermal, etc.) impact on parametric yield and performance verification
Development of new logic families to meet performance challenges (MPU)
Scalability of performance verification methodologies (MPU)
Atomic-scale effects (MPU)
Full leverage of new process innovations (Cu, Low-K, SOI, …) (MPU, SOC)
Convergence and predictability of system implementation process (SOC)
Interacting design levels with multiple complex design constraints (SOC)
Electrical/manufacturing aware technology remapping and migration to maintain productivity (SOC)
Synthesis of high-quality analog, optical interface, embedded passive building blocks (AMS,SOC)
LONG-TERM
Unified chip-package analysis and optimization
Design under uncertainty of fundamental chip parameters (e.g., signal skew) (MPU)
Design with novel devices (multi-Vt, 3D-layout, SOI) and technologies (MEMS, bio) (MPU, SOC)
Physical and communication architectures for SOC implementation fabrics
Logic implementation to deal with single-event upset (MPU, SOC)
True one-pass optimization flow with incremental and partial design specification (MPU, SOC)
Seamless integration of design and manufacturability for reliability and yield (MPU, SOC)
Adaptive and self-correcting circuits (MPU, SOC)
Extremely low-power sensing, sensor interface circuits (AMS, SOC)
Self-repairing circuit technologies
TEST
- ATE reaching limitations in testing high-performance devices
- Integration of complex, heterogeneous components in SOC
- UDSM invalidates IDDQ approaches and causes new failure modes
- Paradigm shift: high-level, earlier testability analysis, test
insertion, test handoff
- Paradigm shift: simpler ATE systems and more IC self-testing
- Paradigm shift: DFT/BIST for parametric noise faults
- Component-level self-test methodologies
- System-level test, test access interface and diagnosis
- Fault modeling, test generation, diagnosis for UDSM defects
(power supply noise, crosstalk effects)
- Test technologies for analog/RF circuits
NEAR-TERM
Capacity gap b/w DfT/Test generation/fault grading tools and design complexity (MPU, ASIC/SOC)
Improved test tools for advanced (open, delay, etc.) fault models (MPU, ASIC/SOC)
Continuation (avoidance) of at-speed func test w/ increased clock frequencies (MPU, (ASIC/SOC))
Signal integrity (noise, capacitive/inductive coupling, etc.) testability (MPU, ASIC/SOC)
DFT to enable low-cost ATE (MPU, ASIC/SOC)
Non-intrusive logic BIST (including advanced fault models) (MPU, ASIC/SOC)
Fault diagnosis and design for diagnosability (MPU, ASIC/SOC)
Power and thermal management during test (MPU, ASIC/SOC)
Quality and yield impact due to test equipment limits (MPU, SOC)
Test of core-based designs from diverse source including AMS, RF (SOC)
At-speed structure test with increased clock frequencies (MPU, ASIC/SOC)
Signal integrity testability (MPU, SOC)
Yield improvement and failure analysis tools and methods (ASIC/SOC)
Fault models for analog (parametric) failures (AMS)
AMS DFT/BIST, especially at beyond-baseband frequencies (AMS)
DFT, BIST and test methods compatible with SOC core-based environment and constraints (AMS)
Test and on-chip measurement techniques for multi-gigahertz serial ports (AMS)
LONG-TERM
Design for efficient and effective burn-in to screen out latent defects (MPU)
New timing-related fault models for defects/noise in UCSM technologies (MPU, ASIC/SOC)
Quality and yield impact due to test equipment limits (MPU, ASIC/SOC)
DFT/BIST/BISR for soft errors (MPU)
Dependence on self-test solutions for SOC with RF, AMS components (SOC)
System test (including MEMS and EO components) (SOC)
Test of multi-gigahertz RF front ends on chip (AMS)
(Analog) signal integrity test issues caused by noise from digital to analog circuitry (AMS)
Diagnosis and failure analysis for AMS parts (AMS)
Dependence on self-test solutions (including RF, analog) (SOC)
Utilizing on-chip programmable resources for SOC self-test (SOC)
Test methods for heterogeneous SOC including MEMS and EO components (SOC)
Logic self-repair utilizing on-chip reconfigurability (SOC)
System-level on-line testing (SOC)