SERIAL – PARALLEL ADDITION MULTIPLIER
AJIT PRASAD
ID: 4634888
Digital Design & Synthesis
COEN 6501
Department of
Electrical & Computer Engineering
Concordia University
December 2005
Ajit Prasad (4634888)
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Serial-Parallel Addition Multiplier
TABLE OF CONTENTS
INTRODUCTION
5
.1 VHDL Design Process
5
.2 Report Breakdown
5
MULTIPLIER DESIGN
6
.1 Multiplier Operation
6
.2 Full Adder
7
.3 D Flip-Flop
9
.4 Parallel Load Shift Register
10
.5 Parallel Load Parallel Output Register
11
.6 Serial-Input Parallel Output Register
11
.7 Multiplier Controller
12
.8 Integrated Multiplier
14
DESIGN ENHANCEMENTS
16
.1 32 X 32-Bit Expansion
16
.2 Pipelined Design
16
.3 Synthesized Design
16
CONCLUSION
17
5.0 REFERENCES
18
APPENDIX A: VHDL SOURCE
19
APPENDIX B: SYNTHESIS
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LIST OF FIGURES
Figure 1.1
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 2.9
Figure 2.10
Figure 2.11
Figure 2.12
Figure 2.13
Figure 2.14
Figure 2.15
Figure 2.16
Figure 2.17
Figure 3.1
VHDL Design Process…………………………………………………………………………. 5
Serial-Parallel Multiplier……………………………………………………………………….. 6
Multiplier Block Diagram………………………………………………………………………. 7
Full Adder K-Map………………………………………………………………………………. 8
Full Adder Schematic………………………………………………………………………….. 8
Full Adder Simulation………………………………………………………………………….. 8
Positive Edge Triggered D Flip-Flop With Asynchronous Reset…………………………. 9
D Flip-Flop Simulation…………………………………………………………………………. 10
Parallel Load Shift Register…………………………………………………………………… 10
Parallel Load Shift Register Simulation……………………………………………………… 10
Parallel Load Parallel Output Register………………………………………………………. 11
Parallel Load Parallel Output Register Simulation………………………………………….. 11
Serial-Input Parallel Output Register………………………………………………………….11
Serial-Input Parallel Output Register Simulation……………………………………………. 12
Multiplier Controller State Machine…………………………………………………………... 12
Multiplier Controller Schematic……………………………………………………………….. 13
Multiplier Controller Simulation……………………………………………………………….. 14
8 by 8-Bit Serial-Parallel Multiplier Simulation………………………………………………. 14
32 By 32-Bit Multiplier Simulation…………………………………………………………….. 16
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LIST OF TABLES
Table 2.1
Table 2.2
Table 2.3
Full Adder Truth Table…………………………………………………………………………. 7
D Flip-Flop Characteristic Table……………………………………………………………… 9
Multiplier Controller State Table……………………………………………………………….13
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INTRODUCTION
The objective is to design an 8 by 8-bit serial-parallel multiplier using structural VHDL. The multiplier
receives two operands A and B, and calculates the result C. The multiplier will be further expanded to
32 by 32-bit multiplication, pipelined, and synthesized.
1.1 VHDL Design Process
The design procedure that will be followed is shown in figure 1.1 below. The target device is the Xilinx
xc3s200 FPGA from the Spartan family of devices. This document will illustrate the design process
from design entry to design implementation of the multiplier.
Figure 1.1 VHDL Design Process [1].
1.2 Document Breakdown
This document breaks the multiplier down into major blocks and designs each block independently
before finally assembling the complete multiplier. Each block is coded in purely structural VHDL
therefore it is necessary to conceive the schematic of each block in advance. To ensure that each block
works as intended it will be simulated and important timing parameters will be extracted.
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2.0 MULTIPLIER DESIGN
The multiplier uses the serial-parallel method of addition to calculate the result of multiplying two 8-bit
numbers as shown in figure 2.1 below. The multiplier receives the two operands A and B and outputs
the result C. Operands A and B are loaded in parallel into 8-bit registers and the result C is shifted into
a 16-bit register. Multiplication begins on the assertion of a START signal and once the calculation is
complete a STOP signal is asserted.
Figure 2.1 Serial-Parallel Multiplier.
2.1 Multiplier Operation
The serial-parallel multiplier is based on the addition of bits in the corresponding column of the
multiplication process as shown below. Each column is added in one clock cycle generating the
corresponding bit. The resulting bit is then shifted into output register. Therefore the entire multiplication
process for the 8 by 8-bit multiplier requires 16 clock cycles to complete the calculation.
a1a0
x b1b0
-----------------------------------a1b0
a0b0
a1b1
a0b1
-----------------------------------a1b1 (a1b0 + a0b1) a0b0
The block diagram for the multiplier is shown in figure 2.2 below. The first operand, A, is loaded in
parallel and the most significant bit is shifted out during each clock cycle. Operand B is also loaded in
parallel and its value is stored in the register for the entire multiplication process. The result C is
generated by shifting the added bits of each column one by one into the resultant register. Therefore
register RA is a parallel load shift register, RB is a parallel load parallel output register, and RC is a
serial input parallel output register.
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Serial-Parallel Addition Multiplier
Figure 2.2 Multiplier Block Diagram.
In addition to the three mentioned registers, the multiplier also requires 7 one-bit registers to store
intermediate values such as the carries generated from each addition, and the bits shifted out from
register RA.
Each component to the multiplier is designed and simulated in the following sections.
* It is important to note that all clocked circuits below use an asynchronous active low reset denoted as
Resetn, and a clock period of 20 ns.
* For the complete VHDL code for the multiplier and its components refer to Appendix A.
2.2 Full Adder
Part of the partial product sum ripple adder block, the full adder is a combinational circuit that calculates
the sum of three bits. The resulting sum is output along with the carry. The truth table and K-maps for
the full adder is shown below in table 2.1 and figure 2.3.
Table 2.1 Full Adder Truth Table.
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
C
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
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Figure 2.3 Full Adder K-Map [2].
Therefore the simplified expressions for the full adder are
S = x’y’z + x’yz’ + xy’z’ + xyz
C = xy + xz + yz
Grouping the above expressions appropriately, the full adder can be constructed using two half adders
and an OR gate
S = z  (x  y)
C = z(xy’ + x’y) + xy
The implementation of the full adder is therefore
Figure 2.4 Full Adder Schematic [2].
The result of simulating the circuit is shown in figure 2.5 below.
Figure 2.5 Full Adder Simulation.
Although it is not obvious from the schematic, the simulation reveals that the maximum delay of the
circuit is the time it takes for the sum output to be generated (which indicates that the XOR gate has the
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largest delay compared to the AND or OR gates). In this case the delay of the full adder circuit is
approximately 8.196 ns.
2.3 Edge Triggered D Flip-Flop
The positive edge triggered D flip-flop with asynchronous reset is used throughout as the main register
type to store various bit values for the multiplier. The characteristic table for the D flip-flop is shown in
table 2.2 below. For this type of register the next output is simply the present input.
Table 2.2 D Flip-Flop Characteristic Table.
D
0
1
Q(t+1)
0
1
Reset
Set
An efficient implementation of a D flip-flop uses three SR latches as shown in figure 2.6. Two latches
respond to the CLK and Data inputs. The third SR latch generates the outputs Q and its complement Q’
[2].
Figure 2.6 Positive Edge Triggered D Flip-Flop With Asynchronous Reset [2].
The result of simulating the circuit is shown in figure 2.7.
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Figure 2.7 D Flip-Flop Simulation.
The delay from the clock input to the output is approximately 11.678 ns.
2.4 Parallel Load Shift Register
The 8-bit parallel load shift register is composed of multiplexers and D flip-flops, refer to figure 2.8. The
multiplexers select whether to load the data or to simply pass the previous register value. If neither the
load or shift enable inputs are high the registers keep their current values. If both inputs are high then
the load input takes precedence. Otherwise the circuit either loads or shifts at each clock cycle with
respect to the input that is high. If the circuit is shifting then a 0 is introduced at the leftmost bit.
Figure 2.8 Parallel Load Shift Register.
The result of simulating the circuit is shown in figure 2.9 below.
Figure 2.9 Parallel Load Shift Register Simulation.
Since in either the loading or shifting case data must travel from the input of the LSB multiplexer to the
output shift bit the delay is equal at approximately 14.891 ns. Knowing from the previous simulation that
the D flip-flop has a delay of 11.678 ns we can induce that the multiplexer has a delay of approximately
3.213 ns.
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2.5 Parallel Load Parallel Output Register
Similar to the previous register, the parallel load parallel output register is composed of multiplexers
and D flip-flops. In this case, however, the circuit either loads new data or does not change its output.
Refer to figure 2.10 below for the schematic.
Figure 2.10 Parallel Load Parallel Output Register.
The result of simulating the circuit is shown in figure 2.11 below.
Figure 2.11 Parallel Load Parallel Output Register Simulation.
In this circuit a delay is introduced only if new data is loaded. As the simulation shows the delay is
equivalent to that of the previous register RA (14.891 ns) since at each clock cycle data is fed from the
input of the multiplexer to the output of the D flip-flop, which is the same critical path as the previous
circuit.
2.6 Serial-Input Parallel Output Register
The final register circuit in the multiplier is the serial-input parallel output register. This register stores
the result of each succeeding column addition and outputs the result in parallel. The circuit is very
similar to the other two registers however it is configured to shift a data bit into the MSB and to output
the register state when it is not shifting data as shown in its 8-bit implementation below.
Figure 2.12 Serial-Input Parallel Output Register.
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The result of simulating the circuit is shown in figure 2.13 below.
Figure 2.13 Serial-Input Parallel Output Register Simulation.
Equivalent to the other two registers RA and RB, the delay for this circuit is 14.891 ns.
2.7 Multiplier Controller
The circuit which allows for the multiplication process to actually take place is the multiplier controller.
Upon assertion of the START signal the controller resets the registers, loads the operands, calculates
the result and asserts the STOP signal. The START signal is only valid in the idle state or the done
state since it is assumed that no calculation would be interrupted for new data. The STOP signal is
asserted after 16 clock cycles determined by an internal counter. A finite state machine is used to
design the circuit as shown below.
Figure 2.14 Multiplier Controller State Machine.
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Serial-Parallel Addition Multiplier
The corresponding simplified state table for the FSM above is shown in table 2.3 below.
State values: Idle = 00, Load = 01, Calculate = 10, and Done = 11.
Table 2.3 Multiplier Controller State Table.
Present State
X
Y
x
x
0
0
0
1
1
0
1
0
1
1
1
1
Start
x
1
x
x
x
1
0
Input
Counter
x
x
x
< 1111
1111
x
x
Resetn*
0
1
1
1
1
1
1
Next State
X
Y
0
0
0
1
1
0
1
0
1
1
0
1
1
1
Load
0
0
1
0
0
0
0
Shift
0
0
0
1
1
0
0
*Active low
The resulting simplified equations are (using sum of products)
X+ = Resetn X’ Y + Resetn X Y’ + Resetn Start’ X Y
Y+ = Resetn Start X’ Y’ + Resetn Counter1111 X Y’ + Resetn X Y
Load = Resetn X’ Y
Shift = Resetn X Y’
Stop = Resetn X Y
Reset_Counter = Resetn X Y’ + Resetn X Y
Which translates to the following schematic
Figure 2.15 Multiplier Controller Schematic.
Output
Reset_Counter*
0
0
0
1
1
1
1
Stop
0
0
0
0
0
1
1
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The result of simulating the circuit is shown in figure 2.16 below.
Figure 2.16 Multiplier Controller Simulation.
With a clock period of 20 ns, the delay from the first clock signal after assertion of START till the
assertion of STOP is approximately 354.580 ns.
2.8 Integrated Multiplier
The complete multiplier can now be implemented by integrating the modules above into a single
functional circuit. The result of simulating the circuit is shown in figure 2.18 below.
Figure 2.17 8 by 8-Bit Serial-Parallel Multiplier Simulation.
As can be seen, the delay from the START signal to the assertion of STOP is the same as the multiplier
controller. The overall multiplier circuit delay is approximately 354 ns. This delay is the result of the fact
that the calculation requires 16 clock cycles (320 ns) plus the delay of loading the data (14 ns) and
finally the delay to assert the STOP signal (which is one clock cycle after the last shift = 20 ns).
It can be noted that although the critical path of the circuit is
Ajit Prasad (4634888)
Serial-Parallel Addition Multiplier
the Xilinx software automatically optimizes the circuit upon running a timing analysis simulation.
Therefore, in the optimized circuit, the serial addition of 7 full adders and one flip-flop occurs in less
time than the clock period. If the circuit were not optimized a rough approximation for the minimum
clock period would be
Tmin = DFFCLKQ + 7 * FA = 14 ns + 7 * 8 ns = 70 ns  14.29 MHz
assuming the AND gate and the setup time for the D flip-flop is negligible.
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3.0 DESIGN ENHANCEMENTS
The following section describes enhancements to the multiplier circuit which include 32 by 32-bit
expansion, pipelining, and synthesizing the design.
3.1 32 by 32-Bit Expansion
To expand the circuit to 32 by 32-bits, the registers RA and RB must each be expanded to
accommodate 32 bits and register RC must be increased to 64 bits. The multiplier controller must also
be changed to assert STOP after 64 clock cycles. The result of simulating the 32-bit circuit is shown
below.
Figure 3.1 32 By 32-Bit Multiplier Simulation.
The delay from the assertion of START to STOP is approximately 1310.117 ns. As can be seen, the
delay for this circuit is consistent with the 8-bit circuit such that it is approximately equal to 64 clock
cycles (1280 ns) plus the delay of loading the data (14 ns) and finally the delay to assert the STOP
signal (which is one clock cycle after the last shift = 20 ns).
3.2 Pipelined Design
Due to the fact that the circuit operates in an almost entirely serial fashion and that each calculation
requires exactly 16 shifts and 15 additions from the input to the output for an 8 by 8-bit multiplier,
pipelining is not possible as a way to increase throughput. After the initial multiplication, where the
latency equals 354 ns for a 20 ns clock period, it is not possible to generate a new multiplication result
at each successive clock cycle. The throughput of the current 8-bit design is
Throughput = 17 clock cycles + Tco = latency = 354 ns.
3.3 Synthesized Design
Since both the 32 by 32-bit and the 8 by 8-bit circuits have the same general repetitive structure only
one of them, the 32 by 32-bit circuit, was synthesized. The synthesized design optimizes the circuit by
reducing the delay of any critical paths, reducing the number of gate levels used in the circuit, and
minimizing the number of states in the state machines used. The complete synthesized schematic is
shown in Appendix B.
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4.0 CONCLUSION
An 8 by 8-bit serial-parallel multiplier was successfully designed using structural VHDL. The circuit was
broken down into basic blocks in order to eventually combine them and generate the final multiplier
schematic design. Each block and the final design was coded structurally in VHDL and simulated to
verify its functionality. Using a clock period of 20 ns the delay for performing a complete multiplication
operation is approximately 354 ns from START to STOP.
The design was further enhanced to support 32 by 32-bit multiplication and it was determined that this
method of multiplication cannot be pipelined. Finally, the 32 by 32-bit circuit was synthesized.
Ajit Prasad (4634888)
Serial-Parallel Addition Multiplier
5.0 REFERENCES
[1] Xilinx Inc. “Xilinx Software Manuals”, www.xilinx.com, (Current December 20, 2005).
[2] Mano, M. Morris. Digital Design. Prentice Hall: New Jersey, 2002.
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APPENDIX A: VHDL SOURCE
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--------------------------------------------------------------------------------- Module Name:
Full_Adder - Full_Adder_Architecture
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic);
end Full_Adder;
architecture Full_Adder_Architecture of Full_Adder is
-- component declaration
component OR_2
port(A,B: in std_logic;
C : out std_logic);
end component;
component Half_Adder
port(A,B: in std_logic;
S,C: out std_logic);
end component;
signal S1, C1, C2: std_logic;
-- component specification
for U1,U2: Half_Adder use entity work.Half_Adder(Half_Adder_Architecture);
for U3 : OR_2 use entity work.OR_2(OR_2_Architecture);
begin
-- component instantiation
U1: Half_Adder port map(A=>A, B=>B, S=>S1, C=>C2);
U2: Half_Adder port map(A=>S1, B=>Cin, S=>S, C=>C1);
U3: OR_2 port map(A=>C1, B=>C2, C=>Cout);
end Full_Adder_Architecture;
--------------------------------------------------------------------------------- Module Name:
D_Flip_Flop - D_Flip_Flop_Architecture
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Flip_Flop is
Port ( D : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Q : out std_logic;
Qn : out std_logic);
end D_Flip_Flop;
architecture D_Flip_Flop_Architecture of D_Flip_Flop is
-- component declaration
component NAND_2
port(A : in std_logic;
B : in std_logic;
C : out std_logic);
end component;
component NAND_3
port(A : in std_logic;
B : in std_logic;
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C : in std_logic;
D : out std_logic);
end component;
signal Qi,Qni,Ri,Si,Ti,Ui: std_logic;
-- component specification
for U1,U5: NAND_2 use entity work.NAND_2(NAND_2_Architecture);
for U2,U3,U4,U6: NAND_3 use entity work.NAND_3(NAND_3_Architecture);
begin
-- component instantiation
U1: NAND_2 port map (Ti, Si, Ui);
U2: NAND_3 port map (Ui, Resetn, CLK, Si);
U3: NAND_3 port map (Si, CLK, Ti, Ri);
U4: NAND_3 port map (Ri, D, Resetn, Ti);
U5: NAND_2 port map (Qni, Si, Qi);
U6: NAND_3 port map (Qi, Ri, Resetn, Qni);
Q <= Qi;
Qn <= Qni;
end D_Flip_Flop_Architecture;
--------------------------------------------------------------------------------- Module Name:
Parallel_Load_Shift_Register_8 Parallel_Load_Shift_Register_8_Architecture
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Parallel_Load_Shift_Register_8 is
Port ( Load_Data : in std_logic;
Shift_Enable : in std_logic;
Data : in std_logic_vector(7 downto 0);
Resetn : in std_logic;
CLK : in std_logic;
Shift_Out : out std_logic);
end Parallel_Load_Shift_Register_8;
architecture Parallel_Load_Shift_Register_8_Architecture of Parallel_Load_Shift_Register_8 is
-- component declaration
component Multiplexer_2_To_1
port(In0 : in std_logic;
In1 : in std_logic;
S : in std_logic;
O : out std_logic);
end component;
component D_Flip_Flop
port(D : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Q : out std_logic;
Qn : out std_logic);
end component;
component AND_2
port(A : in std_logic;
B : in std_logic;
C : out std_logic);
end component;
component OR_2
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Serial-Parallel Addition Multiplier
port(A : in std_logic;
B : in std_logic;
C : out std_logic);
end component;
signal Di: std_logic_vector(7 downto 0);
signal Qi: std_logic_vector(6 downto 0);
signal CLKi: std_logic_vector(2 downto 0);
-- component specification
for U1,U2: Multiplexer_2_To_1 use entity
work.Multiplexer_2_To_1(Multiplexer_2_To_1_Architecture);
for U3,U4: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);
for U5,U6: AND_2 use entity work.AND_2(AND_2_Architecture);
for U7: OR_2 use entity work.OR_2(OR_2_Architecture);
begin
-- component instantiation
U1: Multiplexer_2_To_1 port map('0', Data(7), Load_Data, Di(7));
U2: Multiplexer_2_To_1 port map(Qi(0), Data(0), Load_Data, Di(0));
U3: D_Flip_Flop port map(Di(7), Resetn, CLKi(0), Qi(6), open);
U4: D_Flip_Flop port map(Di(0), Resetn, CLKi(0), Shift_Out, open);
U5: AND_2 port map(Load_Data, CLK, CLKi(2));
U6: AND_2 port map(Shift_Enable, CLK, CLKi(1));
U7: OR_2 port map(CLKi(2), CLKi(1), CLKi(0));
Registers:
for i in 5 downto 0 generate
begin
U1: Multiplexer_2_To_1 port map(Qi(i+1), Data(i+1), Load_Data, Di(i+1));
U3: D_Flip_Flop port map(Di(i+1), Resetn, CLKi(0), Qi(i), open);
end generate;
end Parallel_Load_Shift_Register_8_Architecture;
--------------------------------------------------------------------------------- Module Name:
Parallel_Load_Parallel_Output_Register_8 Parallel_Load_Parallel_Output_Register_8_Architecture
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Parallel_Load_Parallel_Output_Register_8 is
Port ( Load_Data : in std_logic;
Data : in std_logic_vector(7 downto 0);
Resetn : in std_logic;
CLK : in std_logic;
Data_Out : out std_logic_vector(7 downto 0));
end Parallel_Load_Parallel_Output_Register_8;
architecture Parallel_Load_Parallel_Output_Register_8_Architecture of
Parallel_Load_Parallel_Output_Register_8 is
-- component declaration
component Multiplexer_2_To_1
port(In0 : in std_logic;
In1 : in std_logic;
S : in std_logic;
O : out std_logic);
end component;
component D_Flip_Flop
port(D : in std_logic;
Resetn : in std_logic;
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CLK : in std_logic;
Q : out std_logic;
Qn : out std_logic);
end component;
signal Di,Qi: std_logic_vector(7 downto 0);
for U1: Multiplexer_2_To_1 use entity
work.Multiplexer_2_To_1(Multiplexer_2_To_1_Architecture);
for U2: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);
begin
-- component instantiation
U1: Multiplexer_2_To_1 port map(Qi(7), Data(0), Load_Data, Di(7));
U2: D_Flip_Flop port map(Di(7), Resetn, CLK, Qi(7), open);
Registers:
for i in 6 downto 0 generate
begin
U1: Multiplexer_2_To_1 port map(Qi(i), Data(7-i), Load_Data, Di(i));
U2: D_Flip_Flop port map(Di(i), Resetn, CLK, Qi(i), open);
end generate;
Data_Out <= Qi;
end Parallel_Load_Parallel_Output_Register_8_Architecture;
--------------------------------------------------------------------------------- Module Name:
Serial_Input_Parallel_Output_Shift_Register_16 Serial_Input_Parallel_Output_Shift_Register_16_Architecture
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Serial_Input_Parallel_Output_Shift_Register_16 is
Port ( Data_In : in std_logic;
Shift_Enable : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Data_Out : out std_logic_vector(15 downto 0));
end Serial_Input_Parallel_Output_Shift_Register_16;
architecture Serial_Input_Parallel_Output_Shift_Register_16_Architecture of
Serial_Input_Parallel_Output_Shift_Register_16 is
-- component declaration
component Multiplexer_2_To_1
port(In0 : in std_logic;
In1 : in std_logic;
S : in std_logic;
O : out std_logic);
end component;
component D_Flip_Flop
port(D : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Q : out std_logic;
Qn : out std_logic);
end component;
signal Di,Qi: std_logic_vector(15 downto 0);
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for U1: Multiplexer_2_To_1 use entity
work.Multiplexer_2_To_1(Multiplexer_2_To_1_Architecture);
for U2: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);
begin
-- component instantiation
U1: Multiplexer_2_To_1 port map(Qi(15), Data_In, Shift_Enable, Di(15));
U2: D_Flip_Flop port map(Di(15), Resetn, CLK, Qi(15), open);
Registers:
for i in 14 downto 0 generate
begin
U1: Multiplexer_2_To_1 port map(Qi(i), Qi(i+1), Shift_Enable, Di(i));
U2: D_Flip_Flop port map(Di(i), Resetn, CLK, Qi(i), open);
end generate;
Data_Out <= Qi;
end Serial_Input_Parallel_Output_Shift_Register_16_Architecture;
--------------------------------------------------------------------------------- Module Name:
Multiplier_Controller_8_8 - Multiplier_Controller_8_8_Architecture
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplier_Controller_8_8 is
Port ( Start : in std_logic;
CLK : in std_logic;
Resetn : in std_logic;
Load : out std_logic;
Shift : out std_logic;
Stop : out std_logic;
Counter : out std_logic_vector(3 downto 0);
State : out std_logic_vector(1 downto 0));
end Multiplier_Controller_8_8;
architecture Multiplier_Controller_8_8_Architecture of Multiplier_Controller_8_8 is
-- component declaration
component D_Flip_Flop
port(D : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Q : out std_logic;
Qn : out std_logic);
end component;
component AND_4
port(A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : out std_logic);
end component;
component AND_3
port(A : in std_logic;
B : in std_logic;
C : in std_logic;
D : out std_logic);
end component;
component OR_3
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port(A : in std_logic;
B : in std_logic;
C : in std_logic;
D : out std_logic);
end component;
component OR_2
port(A : in std_logic;
B : in std_logic;
C : out std_logic);
end component;
component INVERTER
port(A : in std_logic;
B : out std_logic);
end component;
component Counter_4
port(Count_Enable : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Count_Out : out std_logic_vector(3 downto 0));
end component;
signal Anext, Bnext, A, B, An, Bn, Startn, ResetC, C, Shifti: std_logic;
signal RAnB, RABn, RSnAB, RSAnBn, RCABn, RAB: std_logic;
signal Counteri: std_logic_vector(3 downto 0);
-- component specification
for U2,U3,U4,U5: AND_4 use entity work.AND_4(AND_4_Architecture);
for U7,U8,U9: AND_3 use entity work.AND_3(AND_3_Architecture);
for U10,U11: OR_3 use entity work.OR_3(OR_3_Architecture);
for U12: OR_2 use entity work.OR_2(OR_2_Architecture);
for U13: INVERTER use entity work.INVERTER(INVERTER_Architecture);
for U14,U15: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);
for U16: Counter_4 use entity work.Counter_4(Counter_4_Architecture);
begin
-- component instantiation
U2: AND_4 port map(Resetn, Startn, A, B, RSnAB);
U3: AND_4 port map(Resetn, Start, An, Bn, RSAnBn);
U4: AND_4 port map(Counteri(3), Counteri(2), Counteri(1), Counteri(0), C);
U5: AND_4 port map(Resetn, C, A, Bn, RCABn);
U7: AND_3 port map(Resetn, An, B, RAnB);
U8: AND_3 port map(Resetn, A, Bn, RABn);
U9: AND_3 port map(Resetn, A, B, RAB);
U10: OR_3 port map(RAnB, RABn, RSnAB, Anext);
U11: OR_3 port map(RSAnBn, RCABn, RAB, Bnext);
U12: OR_2 port map(RABn, RAB, ResetC);
U13: INVERTER port map(Start, Startn);
U14: D_Flip_Flop port map(Anext, Resetn, CLK, A, An);
U15: D_Flip_Flop port map(Bnext, Resetn, CLK, B, Bn);
U16: Counter_4 port map(Shifti, ResetC, CLK, Counteri);
Load <= RAnB;
Shifti <= RABn;
Shift <= Shifti;
Stop <= RAB;
Counter <= Counteri;
State(0) <= B;
State(1) <= A;
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end Multiplier_Controller_8_8_Architecture;
--------------------------------------------------------------------------------- Module Name:
Multiplier_8_8 - Multiplier_8_8_Architecture
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplier_8_8 is
Port ( A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Start : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
C : out std_logic_vector(15 downto 0);
Stop : out std_logic;
Counter : out std_logic_vector(3 downto 0);
Load : out std_logic;
Shift : out std_logic;
Shift_Line : out std_logic_vector(7 downto 0);
Parallel_Line : out std_logic_vector(7 downto 0);
State : out std_logic_vector(1 downto 0));
end Multiplier_8_8;
architecture Multiplier_8_8_Architecture of Multiplier_8_8 is
-- component declaration
component Parallel_Load_Shift_Register_8
port(Load_Data : in std_logic;
Shift_Enable : in std_logic;
Data : in std_logic_vector(7 downto 0);
Resetn : in std_logic;
CLK : in std_logic;
Shift_Out : out std_logic);
end component;
component Parallel_Load_Parallel_Output_Register_8
port(Load_Data : in std_logic;
Data : in std_logic_vector(7 downto 0);
Resetn : in std_logic;
CLK : in std_logic;
Data_Out : out std_logic_vector(7 downto 0));
end component;
component Serial_Input_Parallel_Output_Shift_Register_16
port(Data_in : in std_logic;
Shift_Enable : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Data_Out : out std_logic_vector(15 downto 0));
end component;
component Multiplier_Controller_8_8
port(Start : in std_logic;
CLK : in std_logic;
Resetn : in std_logic;
Load : out std_logic;
Shift : out std_logic;
Stop : out std_logic;
Counter : out std_logic_vector(3 downto 0);
State : out std_logic_vector(1 downto 0));
end component;
component Full_Adder
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port(A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic);
end component;
component D_Flip_Flop
port(D : in std_logic;
Resetn : in std_logic;
CLK : in std_logic;
Q : out std_logic;
Qn : out std_logic);
end component;
component AND_2
port(A : in std_logic;
B : in std_logic;
C : out std_logic);
end component;
component INVERTER
port(A : in std_logic;
B : out std_logic);
end component;
signal A8,B8,C8: std_logic_vector(7 downto 0);
signal A7,B7,C7: std_logic_vector(6 downto 0);
signal A14,B14: std_logic_vector(13 downto 0);
--signal Statei: std_logic_vector(1 downto 0);
--signal Counteri: std_logic_vector(3 downto 0);
signal Loadi,Shifti: std_logic;
-- component specification
for U1: Parallel_Load_Shift_Register_8 use entity
work.Parallel_Load_Shift_Register_8(Parallel_Load_Shift_Register_8_Architecture);
for U2: Parallel_Load_Parallel_Output_Register_8 use entity
work.Parallel_Load_Parallel_Output_Register_8(Parallel_Load_Parallel_Output_Register_8_Archit
ecture);
for U3: Serial_Input_Parallel_Output_Shift_Register_16 use entity
work.Serial_Input_Parallel_Output_Shift_Register_16(Serial_Input_Parallel_Output_Shift_Regist
er_16_Architecture);
for U4: Multiplier_Controller_8_8 use entity
work.Multiplier_Controller_8_8(Multiplier_Controller_8_8_Architecture);
for U5: Full_Adder use entity work.Full_Adder(Full_Adder_Architecture);
for U6: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);
for U7,U8: AND_2 use entity work.AND_2(AND_2_Architecture);
for U9: INVERTER use entity work.INVERTER(INVERTER_Architecture);
begin
-- component instantiation
U1: Parallel_Load_Shift_Register_8 port map(Load_Data => Loadi, Shift_Enable => Shifti,
Data => A, Resetn => Resetn, CLK => CLK, Shift_Out => B8(7));
U2: Parallel_Load_Parallel_Output_Register_8 port map(Load_Data => Loadi, Data => B,
Resetn => Resetn, CLK => CLK, Data_Out => A8);
U3: Serial_Input_Parallel_Output_Shift_Register_16 port map(Data_in => C8(0),
Shift_Enable => Shifti, Resetn => Resetn, CLK => CLK, Data_Out => C);
U4: Multiplier_Controller_8_8 port map(Start => Start, CLK => CLK, Resetn => Resetn,
Load => Loadi, Shift => Shifti, Stop => Stop, Counter => Counter, State => State);
U5: Full_Adder port map(A => C8(7), B => A7(6), Cin => C7(6), S => C8(6), Cout =>
B7(6));
U6: D_Flip_Flop port map(D => B8(7), Resetn => A14(13), CLK => CLK, Q => B8(6), Qn =>
open);
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U7: AND_2 port map(A => A8(7), B => B8(7), C => C8(7));
U8: AND_2 port map(A => Resetn, B => B14(13), C => A14(13));
U9: INVERTER port map(A => Loadi, B => B14(13));
Sum_Carry_Chain:
for i in 5 downto 0 generate
U5: Full_Adder port map(A => C8(i+1), B => A7(i), Cin => C7(i), S => C8(i), Cout
=> B7(i));
U6: D_Flip_Flop port map(D => B8(i+1), Resetn => A14(i+7), CLK => CLK, Q =>
B8(i), Qn => open);
end generate;
Serial_Parallel_Chain:
for i in 6 downto 0 generate
U6: D_Flip_Flop port map(D => B7(i), Resetn => A14(i), CLK => CLK, Q => C7(i), Qn
=> open);
U7: AND_2 port map(A => A8(i), B => B8(i), C => A7(i));
end generate;
Reset_OR_Initialize:
for i in 12 downto 0 generate
U8: AND_2 port map(A => Resetn, B => B14(i), C => A14(i));
U9: INVERTER port map(A => Loadi, B => B14(i));
end generate;
Load <= Loadi;
Shift <= Shifti;
--State <= Statei;
--Counter <= Counteri;
Shift_Line <= B8;
Parallel_Line <= A8;
end Multiplier_8_8_Architecture;
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APPENDIX B: 32 BY 32-BIT MULTIPLIER SYNTHESIS RESULTS
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