Rolando Gonzalez
Redondo Beach, CA (DEN)
08/01/2003
Rolando.Gonzalez@ngc.com
Bibliography for Techniques in Advanced
Switching Theory:
Suggested Background Readings for EE552
Suggested Reading in Synchronous Systems
Decomposition of Boolean Functions
1. R. L. Ashenhurst, “Non-Disjoint Decomposition,” Harvard Computation
Laboratory Report, No. BL-4, Sec. IV, 1953.
2. H. A. Curtis, “Simple Non-Disjunctive Decomposition,” Harvard Computation
Laboratory Report, No. BL-19, Sec. II, 1958.
3. J. P. Roth and R. M. Karp, “Minimization over Boolean Graphs,” IBM Journal of
Research & Development, Vol. 2, pp. 227-238, April 1962.
4. C. Scholl, Functional Decomposition with Applications to FPGA Synthesis.
Kluwer Academic Publishers, 2001.
Binary Decision Diagrams
5. S. B. Akers, “Binary decision diagrams,” IEEE Trans. On Computers, Vol. C-27,
No. 6, June 1978.
6. R. E. Bryant, “Graph-Based algorithms for boolean function manipulation,”
IEEE Trans. On Computers, Vol. C-35, No. 8, August 1986.
7. G. D. Hachtel and F. Somenzi, Logic Synthesis & Verification Algorithms.
Kluwer Academic Publishers, 1996, pp. 219-244.
8. S. Minato, Binary Decision Diagrams and Applications for VLSI CAD. Kluwer
Academic Publishers, 1995.
Linear Logic
9. A. E. A. Almaini, Electronic Logic Systems. London: Prentice Hall, 1994, pp.
478-496.
Metastability
10. T. J. Chaney, "Measured flip-flop responses to marginal triggering", IEEE
Transactions on Computers, Vol. C-32. No. 12, pp.1207-1209, December 1983.
11. P. Horowitz and W. Hill, “Metastable States,” in The Art of Electronics,
Cambridge University Press, 1989, p. 552.
12. H. W. Johnson and M. Graham, High Speed Digital Design. Prentice Hall, 1993,
pp. 120-131.
13. L. Kleeman and A. Cantoni, "On the unavoidability of metastable behavior in
digital systems", IEEE Transactions on Computers, Vol. C-36. No. 1, pp.109-112,
January 1987.
14. L. Kleeman and A. Cantoni, “Metastable behavior in digital systems,” IEEE
Design & Test of Computers, December 1987.
15. L. R. Marino, “General theory of metastable operation,” IEEE Transactions on
Computers, Vol. C-30, pp. 107-115, February 1981.
16. Texas Instruments, “Metastable response in 5-V logic circuits,” February 1997,
http://focus.ti.com/lit/an/sdya006/sdya006.pdf.
Suggested Reading in Asynchronous Systems
Overview of Asynchronous Systems
1. S. Hauck, "Asynchronous design methodologies: An overview," Proceedings of
the IEEE, Vol. 83, No. 1, 1995, pp. 69-93.
2. M. Josephs, S. Nowick, C. Van Berkel. "Modeling and Design of Asynchronous
Circuits,” Proceedings of the IEEE, Vol. 87, No. 2, February 1999.
3. T. H. Meng, Synchronization Design for Digital Systems. Kluwer Academic
Publishers, 1990.
Races and Hazards
4. Armstrong, Friedman, and Menon, “Realization of Asynchronous Sequential
Circuits Without Inserted Delay Elements,” IEEE Trans. On Computers, Vol. C17, pp. 129-134, February 1968.
5. D. B. Armstrong, A.D. Friedman, and P.R. Menon, “Design of asynchronous
circuits assuming unbounded gate delays," IEEE Transactions on Computers, C18, No. 12, December 1969.
6. J. G. Bredeson and P. T. Hulina, “Elimination of static and dynamic hazards for
multiple input changes in combinational switching circuits,” Information and
Control, Vol. 20, pp. 114-224, 1972.
7. S. H. Caldwell, Switching Circuits and Logical Design. New York: John Wiley
& Sons, 1958.
8. E. B. Eichelberger, “Hazard detection in combinational and sequential switching
circuits,” IBM Journal of Research & Development, Vol. 9, pp. 90-98, March
1965.
9. E. B. Eichelberger, “Hazard detection in combinational and sequential switching
circuits,” in Proc. of the 5th Annual Symposium on Switching Circuit Theory and
Logical Design, November 1968.
10. A. D. Friedman and P.R. Menon, “Synthesis of asynchronous sequential circuits
with multiple-input changes,” IEEE Transactions on Computers, C-17, No. 6,
June 1968.
11. R. Hackbart and D. Dietmeyer, “The avoidance and elimination of function
hazards in asynchronous sequential circuits,” IEEE Transactions on Computers,
C-20, No. 2, February 1971.
12. S. H. Unger, Asynchronous Sequential Switching Circuits. New York: WileyInterscience, 1969.
13. S. H. Unger, “Asynchronous sequential switching circuits with unrestricted input
changes,” IEEE Transactions on Computers, C-20, No. 12, December 1971.
14. S. H. Unger, “Hazards, Critical Races, and Metastability,” IEEE Transactions on
Computers, Vol. 44, pp. 754-768, June 1995.
15. K. Y. Yun, S. M. Nowick, and D. L. Dill, "Synthesis of 3D asynchronous state
machines," in Proceedings of ICCD'92, pp. 346-350.
Petri Nets
16. D. Misunas, “Petri nets and speed independent design,” Communications of the
ACM, 16, No. 8, August 1973.
17. T. Murata, “Petri Nets: Properties, Analysis and Applications,” Proceedings of the
IEEE, Vol. 77, No 4, April 1989, pp. 541-580.
18. J. L. Peterson, Petri Net Theory and the Modeling of Systems. New Jersey:
Prentice-Hall, 1981.
19. J. L. Peterson, “Petri nets,” Computing Surveys, Vol. 9, pp. 223-252, September
1977.
20. J. Wang, Timed Petri Nets, Theory and Application. Kluwer Academic
Publishers, 1998.
Micropipelines
1. P. Day and J. V. Woods, "Investigations into Micropipeline Latch Design Styles,"
IEEE Transactions on VLSI Systems, Vol. 3, No. 2, pp. 264-272, June 1995.
2. S. B. Furber and P. Day, "Four-Phase Micropipeline Latch Control Circuits,"
IEEE Transactions on VLSI Systems, Vol. 4, No. 2, pp. 247-253, June 1996.
3. S. B. Furber and J. Liu, "Dynamic Logic in Four-Phase Micropipeline," in
Proceedings of ASYNC '96, pp. 11-16.
4. I. Sutherland, "Micropipelines," in Communications of the ACM, Vol. 32, No. 6,
pp. 720-738, 1989.
5. K. Y. Yun, P. A. Beerel, and J. Arceo, "High-performance two-phase
micropipeline building blocks: double edge-triggered latches and burst-mode
select and toggle circuits," in IEEE Proceedings on Circuits, Devices and
Systems, Vol. 143, No. 5, October 1996, pp. 282-288.
Extended Burst-Mode Circuits
6. K. Y. Yun, “Automatic synthesis of extended burst-mode circuits using
generalized C-elements,” in Proceedings of EURO-DAC, 1996, pp. 290-295.