2.
2.1
The Threshold Voltage
Introduction
As already stated, it is important for the purposes of device
modelling for circuit analysis and design to have a distinct definition of
the threshold of change from weak to strong inversion. In this regard,
the threshold voltage is defined for an n-channel MOSFET as the value
of gate-source voltage, which gives the same concentration of
electrons in the inverted n-type channel as there is of holes in the ptype substrate. At this point, the surface potential of the
semiconductor is equal in magnitude but opposite in polarity to the
Fermi potential in the body substrate, s = -F. An expression for the
threshold voltage in terms of the device parameters will allow an
understanding of the factors which influence it and how it may be
controlled.
2.2
The Depletion Region
When a small gate voltage is applied to the MOSFET, a depletion
region is formed as holes are repelled back into the p-type substrate or
as electrons occupy the vacant states in the valence band at the
surface of the substrate. This gives rise to the depletion region
underneath the oxide as a layer of negatively ionised fixed atoms
shown in Fig. 2.1. This layer is initially considered to be devoid of all
free carriers. It can be shown that the depth of the depletion region is
given as:
Xd 
2εs φs  φF
q NA
where:
s is the permittivity of the semiconductor material
s is the electrostatic potential at the surface of the semiconductoroxide boundary
F is the Fermi potential in the body of the semiconductor substrate
NA is the doping concentration of the semiconductor substrate
q is the magnitude of the charge on the electron.
1
VDS = 0V
VSB = 0V
VGS > 0V
depletion
region
G
B
D
S
n+
n+
pFig. 2.1
Conditions in the MOSFET with depletion region formed
2
The total ionisation charge per unit surface area in this region under
the oxide layer, assuming ionisation of all dopant atoms present in it,
can be obtained as:
Q  q NA Xd   2qNAεs φs  φF
The threshold voltage is reached at the onset of strong inversion in the
induced channel. This occurs when the electrostatic potential at the
surface is equal and opposite to that in the main p-type substrate, s =
-F as shown in Fig. 2.2. At this point, the depletion layer reaches a
maximum depth and further increase in gate-source voltage beyond
the threshold voltage produces negligible increase in the depletion
depth. The total negative ionisation charge per unit surface area in the
depletion region at this point, denoted QB0, is then obtained as:
QB0   2qNAεs  2φF
2.2 Threshold Voltage
There are four principal factors which influence the threshold
voltage and each is considered in turn.
(i) Work Function
The work function of a material is the amount of energy needed to
remove an electron from the Fermi level to free space. The work
function of the material used for the gate, qM, is different from that of
the semiconductor used for the substrate, qS and it is this that gives
rise to the in-built electric field across the oxide layer which develops
when the materials combine to form the MOSFET. The gate can be
fabricated in metal or a highly conducting polysilicon and the effect of
this field across the oxide must be accounted for in determining the
gate-source voltage required to reach strong inversion. The
contribution made to this voltage made by the difference in the work
functions can be found more conveniently as the difference in the
Fermi potentials of the substrate and gate materials. This is referred to
as the gate-to-channel potential, GC , given as:
3
Work Function Component:
Φ GC  Φ S  ΦM  F substate  F gate
Volts,
a -ive voltage
where:
F 
n
kT
ln( i ) for p-type
q
NA
and
F 
N
kT
ln( D ) for n-type
q
ni
material. Note that F sub is negative for p-type material and positive
for n-type material.
(ii) Surface Potential
As has been seen already, when forming a channel the energy
bands must bend at the surface of the semiconductor to make the
surface potential s = -F. This requires a voltage change of -2F which
is positive for the n-channel transistor as F is a negative quantity for
the p-type substrate. Consequently the contribution of band bending
towards the threshold voltage is:
-2F
Surface Potential Component:
Volts
a +ive voltage
(iii) Depletion Charge
Ionisation of the dopant atoms in the depletion region must take
place before a strong-inversion conducting channel can be formed.
This charge is given above per unit area of the MOS capacitor structure
as QB0. An equal and opposite charge must be accumulated on the gate
of the transistor and the voltage associated with forming this charge is
easily obtained from the law of the capacitor Q=CV or V = Q/C as:
Depletion Charge Component:

QB0

COX
2qNA εs  2F
Volts
COX
4
a +ive voltage
Impurity Charge
The boundary between the oxide and the semiconductor in
practice is not perfect due to impurities in the materials and lattice
imperfections. This gives rise to a small amount of positive impurity
charge at the lower edge of the oxide, QOX, per unit area. This needs to
be compensated for by a negative charge at the gate electrode and
therefore makes a contribution to the threshold voltage of:
Impurity Charge Component:

QOX
COX
Volts
a –ive voltage
If all of these contributions are combined then the threshold voltage is
obtained as:
VT0  GC  2F 
QB0 QOX

COX COX
This is a positive voltage for n-channel MOSFETs
5
Volts
VDS = 0V
VSB = 0V
VGS =VT
G
B
D
S
n+
n+
p-
Semiconductor
Oxide
Metal
+ E Field
-
EC
Ei
qF
S = -qF
EFS
EV
qVGS
EF
M
Fig. 2.2
Conditions in the MOSFET at the Threshold, VGS = VT, VDS=0
6
2.4
Body Effect
All consideration of the operation of the n-type MOS transistor
thus far has assumed that the source and body substrate have both
been connected to ground. Under this condition the threshold voltage
is designated VT0 as above. In some circuits, however, the source may
sit at a higher potential than the substrate so that there is a voltage
difference between them, VSB. This means that in forming the
depletion region there is an additional bias so that the surface
potential of s = -F exists on one side of this region while a potential
of VSB exists on the other side. This means that the ionisation charge is
modified so that:
QB   2qNA εS  2F  VSB
The threshold voltage will also be modified to give:
VT  ΦGC  2F 
QB QOX

COX COX
Rearranging this:
VT  ΦGC  2F 
QB0 QOX QB  QB0


COX COX
COX
which can be written:
VT  VT0 
QB  QB0
COX
substituting:
VT  VT0 
2qNAεs  2F  VSB  2qNAεs  2F
COX
7
VT  VT0 
2qNA εs

 2F  VSB 
 2F

COX
which gives the most general form for the threshold voltage as:
VT  VT0  
where  
2.5
2qNA εs
COX

 2F  VSB   2F

is called the body-effect coefficient or body factor.
Technology Considerations
The threshold voltage is perhaps the most variable of all of the
properties of the MOS transistor. Typical values range from around 0.5
to 1.5V and are usually close to 20% of the supply voltage in digital
circuits. It is subject to both manufacturing and temperature
variations. In practice, however, it can be controlled in the fabrication
process. A common practice nowadays is to use Polysilicon as the
material for forming the gate rather than aluminium metal. This lowers
the work function difference between the gate and the substrate and
consequently lowers the threshold voltage. This is helpful in lowvoltage (3V and 3.3V) logic technologies.
Another process used is that of ion implantation into the
substrate just beneath the oxide, which can be used to raise or lower
the threshold voltage. For an n-channel device the implantation of
positive ions lowers the threshold voltage while the implantation of
negative ions increases it. With sufficient ion implantation it is
possible to lower and even reverse the threshold voltage. This means
that depletion mode devices can be fabricated which have a
conducting channel formed with zero gate-source voltage applied, in
contrast to the enhancement type devices already described. This is
useful in analogue and mixed signal circuit design though it does make
the fabrication cycle longer and more expensive, and is therefore
avoided in purely digital technologies.
8