Form 101 Attachment
Part II, Page 8
Personal identification no. (PIN)
Family name of applicant
Ko
PART II
INTRODUCTION
Floating point and fixed point are representative number systems to express real numbers on
computers. Fixed point places a radix point somewhere in the middle of the digits, and is equivalent to
using integers that represent portions of some unit. Floating-point representation basically represents
real numbers in scientific notation. Scientific notation represents numbers as a base number and an
exponent. Fixed point has a fixed range of representation, which limits it from representing very large
numbers or very small numbers. Also, fixed point is prone to a loss of precision when two large numbers
are divided. Floating point, on the other hand, employs a sliding window of precision appropriate to the
scale of the number. IEEE Standard 754 floating point is the most common representation today for real
numbers on computers, including Intel-based PC’s, Macintoshes, and most Unix platforms. Since IEEE
754 binary floating-point standard was adopted in 1985, every microprocessor as well as many
programming languages have defined the floating-point arithmetic to be IEEE 754 compliant.
Financial, commercial and other user-oriented applications make an intensive use of decimal data, but
decimal data cannot be represented accurately using the binary floating-point arithmetic implemented in
hardware in most computers today. Since decimal floating-point is usually implemented in software,
decimal computations are several order of magnitude slower than the binary equivalent computations.
The lack of decimal hardware, only one hardware implementation is available now in [1], is due to the
fact that binary hardware units are a little faster and occupy slightly less area. But the increasing need
for decimal data processing requires efficient implementations of decimal floating-point in hardware.
We aim at the design of efficient hardware units for decimal integer and floating point computations
addition/subtraction, multiplication, fused multiply-add, division and square-root operations in this
research.
RECENT PROGRESS IN RESEARCH RELATED TO THE PROPOSAL
I have been working in the FPGA-related area since 1993. My research work as a member of
technical staff (1993-1998) at Korea Telecom R&D Group, Korea was to design and implement
asynchronous transfer mode (ATM) network interface cards for 155 Mbps and 25.6 Mbps. My major
task on this key national project was to make the interface logic for the microprocessor, Motorola MC
68360, using the Altera FPGA and the VHDL language. The results of that project were successfully
published [5, 12, 13, 16, 17 in Part II, Form 100]. This technique is transferred to Samsung Electronics,
South Korea.
The FPGA/VLSI research group at the University of Rhode Island developed efficient methods that
can be applied to FPGA/VLSI field to detect bad dies. I developed a second order analysis technique and
an adaptive threshold method that enable a more robust way to IDDq testing [1, 11 in Part II, Form 100].
Since 1998, I have been working to minimize the area and reduce the critical path of an FPGA. I
applied the Reed-Muller canonical form to minimize the number of logic blocks of an FPGA [3, 10 in
Part II, Form 100]. I proposed a few XOR-based techniques to reduce the area and the critical path in the
FPGA [2, 4, 6, 7, 8, 9 in Part II, Form 100].
Over the past 4 years, we have developed a fast binary floating-point adder for an FPGA [Ali’s
papers] and applied it to a FPGA-based face detector [Yongsoon’s papers]. This development included
four students: two M.Sc. students and now a Ph.D. student and a M.Sc. student.
LONG TERM OBJECTIVE
Form 101 Attachment
Part II, Page 9
Personal identification no. (PIN)
Family name of applicant
Ko
The long-term objective of this research is that it will contribute to efficient hardware support for
decimal floating-point arithmetic unit on next microprocessors.
SHORT TERM OBJECTIVE
The short-term objectives of this research are to:
1.Provide a comprehensive understanding of the similarities and differences between binary and
decimal floating-point arithmetic in an FPGA environment
2.Develop efficient arithmetic algorithms and hardware designs for decimal floating-point arithmetic
unit including adder, subtractor, multiplier, divider, and fused adder/multiplier
3.Provide the speedup from implementing decimal floating-point arithmetic unit in hardware
4.Investigate the relative costs in terms of area, critical path delay, performance, and power
consumption of decimal floating-point arithmetic units compared to binary floating-point arithmetic
units
5.Choose the better architecture between separate decimal floating-point arithmetic units and
combined binary/decimal floating-point arithmetic units
LITERATURE PERTINENT TO THE PROPOSAL
One of the earliest digital computers, ENIAC, used decimal arithmetic operations. Even if decimal
arithmetic operations use the similar way human beings do the arithmetic, they were quickly replaced by
binary arithmetic, which is represented more naturally, stored efficiently, and manipulated very quickly
in digital computers.
Recently, there are big demands for decimal arithmetic operations for many commercial applications,
including financial analysis, tax calculation, phone bill, currency conversions, and e-commerce.
Consequently, specifications for it have recently been added to the draft revision of the IEEE 754
Standard for Floating-Point Arithmetic.
Currently, binary Floating-Point Arithmetic handles decimal arithmetic-intensive applications.
Consequently, binary floating-point units introduce inaccurate results even if binary FP is faster. Since
many decimal numbers cannot be exactly represented in binary, these applications store data in a
decimal format and process data using decimal arithmetic software. Even if decimal FP arithmetic
software eliminates conversion errors, it is known that decimal FP software is typically 100 to 1,000
times slower than binary FP implemented in hardware.
Therefore, there is an immediate need for hardware implementation of decimal FP arithmetic unit.
Decimal FP arithmetics have been proposed, and often implemented for both hardware and software.
The hardware implementation of Decimal FP can be summarized as follows:
o decimal floating point: algorism for computers
o
METHODS AND PROPOSED APPROACHES
The latest version of the Xilinx package and its software tools will be used in this research since it is
one of the most dominant tools in market now. As of now, Virtex II pro and ISE 5.1i are the latest one in
Xilinx package. Visual C/C++ 6.0 compiler will be used to automate the pre- and post processing steps.
Where possible use will be made of Canadian Microelectronics Cooperation (CMC) design tools that are
available in the department.
Form 101 Attachment
Part II, Page 10
Personal identification no. (PIN)
Family name of applicant
Ko
ANTICIPATED SIGNIFICANCE OF THE WORK
It is proposed to develop XOR-based technology mapping techniques for the efficient realization of
XOR intensive functions in the FPGA. The proposed techniques can efficiently map XOR intensive
applications in the FPGA. One of the best minimization algorithms will be combined with the proposed
technology mapping techniques to make an efficient logic synthesis tool for the FPGA. It can eventually
lead to significant area and delay reduction in the FPGA. Therefore, FPGA designers can use the saved
area for more functions and reduced timing delays will permit higher speed operation. Especially, the
efficient implementation of the AES algorithm is expected to find wide deployment in a huge variety of
products, making efficient implementations a significant priority.
As many XOR intensive applications are emerging, the proposed research will be an important step
forward. In particular, TRLabs has ongoing work on FPGAs as well as a strong interest in
encryption/decryption architectures.
TRAINING OF HIGH QUALITY PERSONNEL
One Ph. D. student (Mr. Mohammed Rumi, M. Sc., Concordia University), and one M. Sc. Student
(Mr. Ali Malik, B. Sc., University of Texas, Austin) are expected to join my research group in January,
2004. During the training period, the students will be provided a wealth of information related to the
computer engineering field particularly in digital logic synthesis, VHDL language and FPGA tools.
REFERENCES