Gate-level Test Generation using
Spectral Methods at Register-Transfer Level
PhD Thesis Proposal,
Nitin Yogi
Abstract - A growing problem in VLSI testing nowadays is the exponential rise in the test
generation complexity, due to the ever growing design complexity of the digital circuits. Another
problem coming to the forefront is the difficulty of dealing with the testability issues in digital
circuits, which is generally left for the end of the design cycle. Test generation at the RegisterTransfer Level (RTL) has been seen with great hopes to alleviate some of these problems. This
research advances a new approach of RTL test generation using spectral methods. By
interpreting the test generation information in the spectral or frequency domain, our method
attempts to achieve reduced test generation times with enhanced gate-level fault coverages. We
also propose a RTL Design-for-Testability (DFT) method to address the issues of testability early
in the design cycle. This proposal explains the method and some preliminary results. Further it
also sketches the research work to be conducted in the near future and a plan for completion of
the thesis.
1. Introduction
With the increase in the integration and the design complexity of the digital circuits, motivated by
the chip cost reduction from the scaling down of the CMOS technology, testing faces several
problems. Two main challenges that VLSI testing has always wrestled with are; reducing the test
generation complexity and generating high quality test sets. With the exponential increase in the
design size nowadays, these problems have only gone from bad to worse.
Several gate level techniques have been developed. Majority of the circuits in the digital world
are sequential. Testability of sequential circuits is affected by low combinational controllability
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and observability of the memory elements. As a means to increase the testability of the circuits
and also to reduce the automatic test pattern generation (ATPG) complexity, design-for-testability
(DFT) techniques like scan are widely used. Scan-based DFT simplifies the test generation of
sequential circuits to combinational test generation. However, there are downsides to using scan.
There is an area overhead and performance penalty associated with it. Also, there are some issues
with the generation and application of at-speed scan tests, which detect delay faults. Launch-onshift (LOS) and launch-on-capture (LOC) are two methods used for at-speed scan testing. Each
method has its pros and cons. LOS has good transition delay fault coverage, but requires
additional hardware for a fast scan enable signal. LOC requires no special scan hardware but it
achieves lower coverage. Since scan test vectors are non-functional tests, the problem of false
paths and multi-cycle paths needs to be considered in the generation of at-speed scan tests, as the
tests can cause unacceptable yield loss by failing functionally good circuits. This requires analysis
of paths using static and dynamic timing analysis tools, which makes the problem complex.
On the other extreme, we have sequential test generation i.e. test generation for sequential circuits
without any DFT technique. With sequential test generation, at-speed functional tests can be
generated as it does not modify the state machine of the circuit. Different works [Maxwell00,
McCluskey00, Nigh97] have attempted to show the effectiveness of functional tests over
structural scan tests in detecting chip faults and hence having a better defect coverage. Thus
functional tests can be said to have better quality that non-functional tests. However, the
complexity of sequential test generation is very high as compared to combinational test
generation. Hence on one end we have scan-based combinational test generation with reduced
complexity, but with low defect coverage and on the other end we have sequential test generation
with high test complexity, but with higher defect coverage. So the challenge in obtaining
affordable high quality (high defect coverage) test vectors is in reducing the complexity of
sequential test generation.
Testing at the Register-Transfer Level (RTL) or higher levels of abstraction has been viewed with
great hope in the past for reducing some of the problems in testing of digital circuits. One main
advantage is the significant reduction in test generation complexity as the amount of information
to be processed is far lower as opposed to that at the gate-level, which consists of millions or
billions of gates and interconnects. Hence RTL test generation seems to offer promise in dealing
with the challenge of reducing sequential test generation complexity. Another advantage of doing
test generation at levels higher than the gate-level is that it becomes possible to deal with the
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testability issues early in the design cycle as opposed to struggling with them later at the gatelevel where the complexity is large.
Although RTL test generation alludes to low test generation complexity, an established method of
test generation does not exist. Several research works have been published on fault models and
test generation at the behavioral level and RTL. Ravi and Jha [Ravi01], Ghosh and Fujita
[Ghosh99], Kim and Hayes [Kim98] and Goloubeva et al. [Goloubeva02] use pre-computed test
sets for RTL constructs like adders, multiplexers, etc., and derive test vectors for the whole
circuit. Pre-computed test sets either make some assumptions about the gate-level synthesis of the
design or use a superset of the actually required test vectors. They use some kind of data structure
or metrics to derive the RTL test sets, which have implications of large memory and computation
overheads. Thaker et al. [Thaker03] show that a set of stuck-at faults of variables in high-level
synthetic operators and at the boundaries of RTL modules serve as a statistical sample for the
gate-level coverage analysis. Recent work by Kang et al. [Kang07] uses a set of stuck-at faults
called the sensitization faults whose detection is implied by the detection of primary input stuckat faults at primary outputs. The coverage of sensitization faults is shown to correlate well with
the stuck-at fault coverage in any gate-level implementation. However test generation effort is
higher for such faults as compared to ordinary stuck-at faults. Many of these methods have
difficulties either in closing the gap between the high level coverage and the fault coverage at the
gate level or suffer from high test generation effort. Hence we need an efficient method of test
generation, which effectively utilizes the RTL information for high fault coverage at the gatelevel with the least effort and complexity.
For several years, research has being conducted on the nature and characteristics of test vectors,
which will provide high quality, high defect coverage test sets. Initially, experiments were
performed using random vectors and were found to give good results. Later a class of random
pattern resistant circuits were discovered [Eichelberger83], which made it difficult to use random
vectors. Research then shifted towards weighted random [Brglez90, Ha92, Wunderlich97] and
other types of property based test generation [Guo99]. Some of these methods did work, but not
satisfactorily for all circuits. In the quest to determine appropriate characteristics of test vectors
with high defect coverage and to find a method of test generation, the proposed research in this
thesis attempts to look at the periodicities required for the test vectors by analyzing information in
the frequency or the spectral domain. We allege that good quality test vectors, which give high
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fault coverage, exhibit certain frequency related characteristics. By preserving these
characteristics good quality high defect coverage test vectors can be generated.
Spectral methods for test generation have a long history since the development of complex VLSI
circuits. In 1983, Susskind [Susskind83] showed that Walsh spectrum can be used for testing a
digital circuit. General properties and applications of digital spectra can be found in the published
literature [Beauchamp84, Falkowski02, Hurst85, Thornton01]. Hsiao and Seth [Hsiao84] further
expanded that work to compact testing. More recently, Giani et al. [Giani01a, Giani01b] have
reported spectral techniques for sequential ATPG and built-in self-test. Hsiao's group at Virginia
Tech has published further work on spectrum-based self test and core test [Chen02, Chen06,
Kasturirangan02]. Khan and Bushnell [Khan06] have designed hardware signature analyzers
using spectral components. Zhang et al. [Zhang04] further refined the method of extracting the
spectra from a digital signal using a selfish gene algorithm. Recent work suggests that wavelet
transforms can also be used for similar application [Devanathan06].
2. Background
In this proposal we describe a method of test generation for gate-level faults utilizing relevant
RTL information. To obtain this RTL information, we define faults at the RTL and generate
vectors to detect these faults. Our method of test generation for the gate-level faults is based on
the premise that the vectors that detect RTL faults reflect important characteristics of the circuit.
These characteristics may include spatial and temporal correlations among the bits of primary
input vector sequences and the necessary sequence length to sensitize paths between primary
inputs and outputs of a sequential circuit. However, any high level test sequence has, besides
containing the relevant information, some amount of noise, which corresponds to the don't care
bits in the tests for the target faults. We analyze the spectrum or frequency information in the
vectors which detect the RTL faults, analyze the noise level, and generate new vectors using the
spectrum to which noise samples are added. We use frequency decomposition, in which any bitstream or signal can be projected on to or represented using a set of orthogonal functions.
We use Walsh functions [Weisstein] for frequency decomposition because they have been used
for testing with effective results. Walsh functions are a set of orthogonal functions. They consist
of trains of square pulses having +1s and -1s as the allowed states and can only change at fixed
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intervals of a unit time step. The Walsh functions include patterns with varying periodicities
which can be likened to the sine and cosine functions in the analogue domain. Hence Walsh
functions can be thought of as digital counterparts of analog frequencies. Figure 2.1 shows the
schematic diagram of Walsh functions of order eight. Any digital bit-stream can be uniquely
represented as a linear combination of the orthogonal Walsh functions. This is analogous to the
analog domain where any continuous signal can be uniquely represented as a linear combination
of the sine and the cosine functions. Thus, by analyzing the digital signals using Walsh functions,
we are actually looking into the frequency or sequency characteristics of the digital waveforms.
Frequencies refer to periodicities for analog signals, while sequencies refer to bit-flipping along
with their periodicities for digital waveforms [Weisstein].
For an order n, i.e., for a sequence of n time steps, there are 2n Walsh functions given by the rows
of a 2n x 2n Hadamard matrix H(n) [Weisstein], when arranged in the so-called didactic order
[Weisstein]. The Hadamard matrix is a symmetric matrix with each row being a unique Walsh
orthogonal function, also called as the basis function bit-streams. Since it consists of only +1s and
-1s, it is a good choice for the signals in VLSI testing (+1 = logic 1, -1 = logic 0). Also,
Time period
Figure 2.1: Walsh functions of order eight
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multiplications can essentially be computed using integer additions and subtractions. Hadamard
matrices can be generated using the following recurrence relation:
 H (n  1) H (n  1) 
H ( n)  

 H (n  1)  H (n  1)
… (1)
where H(0) = 1 and 2n is the dimension of the nth order Hadamard matrix, H(n). For example, for
n = 1 and n = 2, we have:
 1  1
H (1)  

 1  1
… (2)
 1
 1
H (1)  
 1

 1
… (3)
 1  1  1
 1  1  1
 1  1  1

 1  1  1
The Hadamard matrix is an orthogonal matrix, which gives H(n) x H(n)T = n x In, where
superscript
T
means transpose of the matrix and In is the 2n x 2n identity matrix. This simplifies
reconstruction of the test vectors from the spectral domain. Any bit-stream of k bits can be
represented as a linear combination of the basis bit-streams from the Hadamard matrix, H(log2 k).
The multiplicands used are the projections of the object bit-stream on the basis bit-streams. We
shall refer to them as Hadamard coefficients. By analyzing these Hadamard coefficients we will
be able to determine the major contributing basis bit-streams in an original signal, which we shall
regard as important basis bit-stream functions.
3. Spectral RTL Test Generation
In this section we explain the proposed Spectral RTL test generation approach [Yogi06b]. Our
approach consists of the following steps:
1. Spectral characterization
2. Spectral vector generation
3. Test set minimization
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3.1 Spectral Characterization
In this step we retrieve important test related information from the circuit at the RTL. For this we
define faults at the RTL called RTL faults. These faults can be defined as faults from
conventional fault models like stuck-at, transition delay, etc. or can be any other user-defined
fault model. We have experimented with both stuck-at and transition delay faults and have
achieved satisfactory results as our results section will exhibit. The RTL faults are defined as
faults on primary inputs and outputs of the circuit and on inputs and outputs of all RTL modules
which include the memory elements like flip-flops. This RTL fault model is very similar to the
fault model proposed in [Thaker03] by Thaker et. al. except that their fault model also includes
behavioral constructs like variables. Such constructs if available can be incorporated in our fault
model. However behavioral constructs do not always align well with the gate-level
implementation, sometimes losing their identity in the gate-level netlist.
Figure 3.1: RTL faults modeled in a typical sequential circuit
Figure 3.1 shows the modeled RTL faults in a typical sequential circuit. These faults remain
invariant through logic synthesis and thus represent true RTL or higher level faults. We obtain
test vectors which detect these RTL faults at the primary output of the circuit. An RTL ATPG
would be required to generate tests for these faults. In our case, we did not have access to a RTL
ATPG tool. Hence as a substitute, we used a gate-level sequential ATPG tool and used a
synthesized netlist of the RTL circuit as its input. Only the RTL faults, as defined earlier, were
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given to the sequential ATPG tool for test generation. Throughout this proposal, we will use this
substitute methodology to show the efficacy of the proposed technique.
We will refer to the vectors generated for these RTL faults as RTL vectors. When these RTL
vectors are applied to the gate-level netlist, only a fraction of the total gate-level faults are
detected. Hence there is a need to generate more vectors which will have similar characteristics as
the RTL vectors. To determine these characteristics, the RTL vectors are analyzed in the
frequency domain using Hadamard matrix to find the major spectral components. When the RTL
vectors are being applied to the circuit, a different set of bit-streams are being applied to each of
the inputs. Since we are dealing with sequential circuits, there is correlation or periodicity
information among the bits entering each of the inputs and it needs to be extracted. Hence we
shall analyze the bit-streams entering each of the inputs separately.
To analyze a bit-stream, initially the 0s and 1s in a bit-stream are changed to -1s and +1s,
respectively. To find the coefficients for the bit-stream corresponding to an input, the bit-stream
is multiplied with the Hadamard matrix. The multiplication operation is basically a projection of
the bit-stream onto each of the basis bit-streams. A high value of the coefficient corresponds to a
high correlation of the bit-stream to the corresponding basis bit-stream and vice-versa.
Figure 3.2: Spectral analysis of a stream of 8-bits. The essential Walsh component in this bit-stream
has magnitude 6 and is represented by the second row of Hadamard matrix, H(3).
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Figure 3.3: Power spectrum of an input bit-stream obtained from RTL vectors for a test circuit.
Hence basis bit-streams exhibiting high coefficient values are considered as important or essential
components and others are treated as noise.
Figure 3.2 shows an example of generation of coefficients by projecting a bit-stream onto the
basis bit-streams and determining the essential component(s). In this example, a bit-stream of 8
bits (0s and 1s in the original sequence being changed to -1s and +1s) is analyzed by multiplying
by a third order 8 x 8 Hadamard matrix H(3). The resulting matrix gives the Hadamard
coefficients. In this example, we obtained a single coefficient with high correlation, which we
shall treat as an essential component and others will be treated as noise. The determination of a
threshold which separates the essential components from the noise is crucial in retrieving the
required characteristics of the bit-stream. Figure 3.3 shows the normalized power spectrum for a
input signal in a test circuit. The power spectrum was obtained by squaring the spectral
coefficients. The high rising bars show high correlation of the bit-stream with the corresponding
basis bit-streams and these are considered essential. For an arbitrary random bit-stream we would
expect the total power to be distributed equally among all the coefficients. This is represented by
a dotted line in figure 3.3 and is the average noise level. If we use this noise level or a few
multiples of this level as a threshold, then we shall be able to differentiate between the essential
and the noise components.
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The above described spectral analysis is performed for each of the input bit-streams and a
corresponding spectra i.e. a set of spectral coefficients is obtained for each input. For each spectra
corresponding to an input of the circuit, the essential and the noise components are determined
using the threshold level.
3.2 Spectral Vector Generation
As discussed in the previous section, the RTL test vectors detect only a fraction of the total gatelevel faults. Hence we need to generate new test vectors replicating some of the essential
characteristics of the RTL vectors. New test vectors for gate-level faults are generated essentially
by generating new bit-streams entering each of the inputs of the circuit from the respective
spectras of the RTL input bit-streams. The essential spectral coefficients having magnitudes
above some threshold are retained and others, considered noise, are perturbed in terms of
magnitude and/or in phase to generate new coefficients. The amount of perturbation corresponds
to the amount of randomness to be added. Bit-streams can easily be generated from the
coefficients by multiplying the coefficient matrix with the Hadamard matrix again.
Figure 3.4 shows an example of reconstruction of a bit-stream. By generating a new bit-stream
for each input we get a new set of bit-streams or a vector sequence V, different from the original
RTL vector sequence. Suppose the number of spectral components obtained for each input is ‘n’.
We generate ‘M’ different vector sequences, V1, V2, .., VM, each of length n, such that their
coverage as determined by fault simulation of the gate-level circuit either reaches some target
value or simply saturates.
Figure 3.4: Bit-stream generation by perturbing the spectra. Note that the essential component
having a magnitude 6 is not perturbed.
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3.3 Test Set Minimization
From the spectral vector generation step we generate a set of M perturbed vector sequences, V1,
V2, .., VM by adding random noise samples, such that the fault coverage of the combined set for
the gate-level circuit either reaches some target value or simply saturates. However, all of these
sequences are not required as some sequences may be detecting faults already covered by other
sequences. Hence we need to perform a test set minimization step. Given a set of test vector
sequences { V1, V2, … VM}, our goal is to obtain a minimized set of vector sequences {V1, V2, …
VK) such that the fault coverage of the minimized set is equal to the original set. We perform
minimization using an integer linear programming (ILP) formulation, in a similar way as has
been reported in the literature [Drineas03, Kantipudi06, Marques98].
3.3.1 Integer Linear Programming (ILP)
An integer linear programming (ILP) problem is a special case of a linear programming (LP)
problem. An LP problem [Noyes] is an optimization problem in which we minimize or maximize
an objective function for a given a set of constraints. The objective function and constraints are
both expressed as linear functions of a set of variables. A LP problem formulation consists of
three parts: a set of real valued variables are defined, a set of constraints on those variables are
specified and an objective function consisting of a linear function of variables is defined to be
minimized or maximized. The solution consists of values assigned to the variables which satisfy
the constraints and meet the objective function goals. An ILP problem is one, in which the
variables are integers as opposed to being real numbers. LP problems are less complex to solve as
compared to the ILP. The complexity of LP is P class while for ILP, it is NP-hard [Kantipudi07].
An ILP can be converted to an LP, known as relaxed LP, by redefining integer variables as real
numbers. The relaxed LP [Kantipudi07], then leads to an approximate but polynomial time
solution of ILP.
3.3.2 ILP Test Minimization
To perform test set minimization we first do fault simulation of all the generated sequences to
determine the faults detected by each. During fault simulation, at the beginning of each vector
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sequence the complete fault list is restored and the circuit is set to an unknown state. Thus, the
coverage obtained for a sequence remains valid irrespective to the order in which it is applied.
The fault simulator identifies the set of vector sequences that detects each fault.
Next, the ILP formulation for test minimization consists of three parts:
1. Integer variables {xi}; i = 1 to M (total number of sequences). Variables {xi} have the
following properties:
a. One variable is defined for each sequence {Vi}
b. Variables {xi} can take values {0,1}
c. A value ‘0’ signifies that the sequence is to be dropped from the minimized set,
while a value ‘1’ signifies that the sequence is selected.
2. A set of constraints {yj}; j = 1 to F (total number of faults). Constraints {yj} have the
following properties:
a. One constraint is defined for each fault {Fj}
b. To illustrate the constraint, say the fault Fk is detected by sequences V3, V4, and
V11.
Then the corresponding ILP constraint yk is: x3 + x4 + x11 ≥ 1
This constraint means that at least one sequence among V3, V4, and V11 is needed
to detect the fault Fk.
3. An objective function given by:
iM
Minimize  xi
… (5)
i 1
where M is the total number of vector sequences generated. This objective function
signifies that a minimum number of variables in {xi} need to be assigned the value 1,
which means that the least number of sequences needs to be selected.
We used the ILP software contained in the AMPL mathematical programming package
[Fourer93] to perform the test sequence compaction. In the ILP solution, the smallest possible
number of x's is assigned the value 1 and all others are assigned 0. The sequences with their x's
set to 1 form the minimized test set.
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3.3.3 Hybrid LP – ILP
As discussed in Section 3.3.1, the ILP problems have very high computation complexity.
Correspondingly, the time complexity of solving ILP problems is higher than LP problems. Much
research work has been published on reducing the complexity of solving ILP problems by settling
for a sub-optimal solution. As discussed earlier, an ILP can be converted to an LP, known as
relaxed LP, by redefining integer variables as real numbers. The relaxed LP [Kantipudi07], then
leads to an approximate but polynomial time solution of ILP. Here we propose a modified version
of the relaxed LP called the hybrid LP-ILP method [Yogi07b]. The algorithm is as follows:
1.
Formulate the ILP problem
2.
All variables redefined as real [0,1] real variables (LP model)
3.
Loop :
1. Solve the LP
2. Round variables to add constraints
1. Round to 0 if ( 0.0 < variables ≤ 0.1)
2. Round to 1 if ( 0.9 ≤ variables < 1.0)
3. Exit loop if no variables are rounded
4.
Reconvert variables to [0,1] integers and solve ILP
We experimented with this algorithm for minimization of test vectors for multiple fault models on
some combinational and scan-inserted ISCAS’89 benchmark circuits to achieve satisfactory
results. Since we round variables on both sides, i.e., to 0 and to 1, the procedure can lead to an
intermediate solution that may not satisfy all remaining constraints. In such a case, the problem
can be solved by the previously proposed recursive-LP algorithm [Kantipudi07], which
guarantees a solution. We believe that, whenever a solution is possible, the hybrid LP-ILP will be
faster than the recursive-LP.
4. RTL DFT
Test generation for RTL faults has an additional advantage other than characterizing the circuit
for gate-level fault coverage. It reveals the bottlenecks in the testability of the circuit. Analysis of
hard to detect RTL faults gives an idea of the hard to test parts of the circuit. Hence, by
13
improving the testability of such faults, we can expect to increase the testability of the overall
circuit. Furthermore, it helps to introduce testability enhancement in the early stages of the design
and alleviate the possible problems arising toward the end of the design cycle.
The testability of signals can be improved by increasing their controllability and/or observability.
Several methods [Hayes73, Iyengar89] of design for testability add control and observation
points. Adding control points requires adding extra gates in the normal signal paths of the circuit,
which may affect the performance. Also adding control points changes the state machine of the
circuit, thus creating non-functional tests. As discussed in Section 1, we would like to discourage
non-functional vectors to prevent unnecessary yield loss. Hence, we shall constrain ourselves to
addition of observation points because they are less intrusive. One option is to add latches for all
observation points and connect them through a scan-out chain. This structure is often used for
design debugging and can help in improving the fault coverage of tests [Josephson05]. Another
option is to use an XOR tree to condense the logic values at various observation points
[Davidson81, Eichelberger83, Fox77, Rudnick92]. In this case an XOR tree connects together all
hard-to-observe fault sites together and condenses them into a single primary output. Since the
XOR tree requires less hardware, we use it as the RTL design for testability (DFT) methodology
[Yogi07]. Also since it does not modify the state machine of the circuit, it does not create nonfunctional tests. Figure 4.1 shows an example of an XOR tree used to condense hard-to-observe
RTL faults. The hard-to-observe RTL faults are obtained after the RTL test generation and the
analysis of the undetected faults.
Figure 4.1: XOR tree used to condense hard-to-observe RTL faults.
5. Results
We applied our RTL test generation and DFT technique to several benchmark circuits with
satisfactory results. Primarily, we have experimented with the ISCAS’89 sequential benchmark
circuits and the ITC’99 benchmark circuits. The ISCAS’89 benchmark circuits are available as
gate-level netlists. The ITC’99 benchmark circuits are available as high-level behavioral
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descriptions and we synthesized them using the Mentor Graphics synthesis tool Leonardo
Spectrum.
Another circuit we experimented with was a simple accumulator-based processor named Parwan
[Navabi93] to demonstrate our method's effectiveness. As shown in the schematic diagram of
Figure 5.1, it includes the following components: accumulator (AC), arithmetic logic unit (ALU),
shifter unit (SHU), status register (SR), instruction register (IR), program counter (PC), memory
address register (MAR) and a control unit (CTRL). It has an 8-bit databus with a 12-bit address
bus (addressing 4K memory). The circuit has around 800 gates and 53 flip-flops. Currently our
tools do not handle bidirectional pins. Hence, we split the bidirectional buses into separate input
and output buses. Also, we added a reset signal to initialize the circuit for testing. We modeled a
total of 737 RTL faults, which were all the faults on the inputs-outputs of the different
components (e.g. ALU, SHU, etc.), inputs-outputs of the registers (e.g. IR, PC, etc.) and the faults
on tri-state drivers.
As discussed earlier in Section 3.1, in the absence of a RTL ATPG, we use a gate-level sequential
ATPG tool, Mentor Graphics FlexTest [FlexTest04] and use synthesized gate-level netlists of
RTL descriptions. The RTL faults, defined either using stuck-at fault model or transition delay
fault model, are given to FlexTest [FlexTest04] for test generation. We experimented with the
RTL faults defined using the stuck-at fault model for the ISCAS’89 circuits, ITC’99 circuits and
Parwan processor [Yogi06b]. For the Parwan processor we also experimented with RTL faults
defined using the transition delay fault model [Yogi07a]. The following sections describe the
results of RTL spectral test generation for RTL faults defined using stuck-at fault model and
transition delay fault model.
We applied the spectral technique of RTL-ATPG to four ITC'99 RTL benchmark circuits, four
ISCAS'89 benchmark circuits and the PARWAN processor [Navabi93] using the stuck-at fault
model. Three off the four ITC'99 RTL benchmark circuits were synthesized in two ways, by
optimizing area and by optimizing delay.
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Figure 5.1: Schematic diagram of PARWAN processor
5.2 RTL Spectral Test Generation using Stuck-at Fault Model
Test vectors for RTL faults were obtained using the Mentor Graphics tool FlexTest [FlexTest04]
which is a sequential ATPG system with a built in fault simulator. Those RTL vectors were
analyzed for their spectrum, new vector sequences were generated using the technique discussed
in Section 3 and finally they were minimized. Results were obtained on Sun Ultra 5 machines
with 256MB RAM. Table 5.1 shows the characteristics of the RTL test vectors generated for the
circuits. Column 1 lists the circuit name. Here b01-A and b01-D are the area and delay optimized
implementations of the b01 ITC'99 benchmark. ISCAS'89 benchmarks are already at the gatelevel. For s5378 and s9234, we created additional versions by adding a global reset input in the
original circuits. These are denoted with an asterisk (*).
Column 3 of Table 5.1 lists the number of RTL stuck-at faults, which are the faults at the primary
inputs, primary outputs, and the inputs and outputs of ip-ops. Next, in Table 5.1 appear the
number of RTL test vectors, test generation time (CPU s) and the number of spectral components.
For the ITC'99 benchmarks this was done for two gate-level versions, one synthesized with area
optimization and the other with delay optimization. The number of spectral components in the
sixth column is the number of RTL vectors rounded off to the nearest power of 2.
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Table 5.1: Spectral characterization of circuits by RTL vectors.
* global reset added
The last two columns of Table 5.1 show the fault coverages of the RTL vectors. RTL Coverage is
the coverage of just the RTL faults and gate-level coverage is the coverage of all stuck-at faults in
the gate-level implementation. As expected, the gate-level coverage is often lower than the RTL
coverage and falls below the normal requirement of being close to 100%. We will use the RTL
DFT technique to enhance this coverage. The low coverage of the RTL faults, however, may
indicate a testability problem, which could limit our ability to increase the coverage either by the
spectral technique or by gate-level ATPG. As observed in the table, a relatively low RTL
coverage is obtained for the circuit s9234. This was primarily due to the inherent uninitializability
of the circuit. We observe that by adding a global reset signal both the RTL and the gate-level
coverage improved. We further believe that employing the proposed RTL DFT technique for this
circuit will enhance the fault coverages.
Table 5.2: Comparison of RTL ATPG and Sequential gate-level ATPG results
* global reset added
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Table 5.2 gives a comparison of the proposed RTL ATPG method with gate-level sequential
ATPG. The first two columns give the circuit name and the number of gate level single stuck-at
faults. The circuits with an added global reset input are denoted with an asterisk (*). The
performances of RTL ATPG{spectral tests, gate-level ATPG, and random vectors can be
compared by examining the data in the subsequent columns.
For RTL ATPG, the number of vectors is the total number vectors in the compacted test
sequences. Gate-level test coverage provided by the fault simulator of FlexTest [FlexTest04] is
shown in column 2 of Table 5.2. Note that the test coverage of FlexTest is an upward adjusted
coverage, accounting for faults that are found to be untestable as detected. The ATPG time in
column 5 includes the times for RTL characterization (Table 5.1), perturbed spectral sequence
generation, fault simulation, and ILP compaction. Of these, RTL characterization and fault
simulation are the dominant components, the other two being negligible. As we move down in
Table 5.2, circuits become larger and we observe that RTL ATPG provides about the same test
coverage and vector lengths as the gate-level ATPG, but its time increases slower. Moreover, the
RTL faults used for circuit characterization and vector generation are implementation
independent. Notably, the test coverage of random vectors tends to drop as circuits become
larger. s9234 circuit as discussed earlier has uninitializability and testability issues which are
reflected in the results of Table 5.2.
Figure 5.2: Test coverage of RTL ATPG (spectral vectors) for area optimized b11-A circuit.
Figure 5.2 gives the test coverage against the number of vectors for the circuit b11-A, for RTL
spectral ATPG vectors, gate-level ATPG vectors and random vectors. The gate-level coverage of
RTL vectors (generated to cover RTL faults only) are also shown by a point in the graph. As
18
observed the coverage of RTL ATPG is about 2 to 4% higher, vector lengths about double and
CPU times about 30 to 50% when compared to the gate-level ATPG.
We applied the RTL DFT technique to the Parwan processor. After the RTL test generation step,
we analyzed the undetected RTL faults and found all 10 faults classified as unobservable by
FlexTest. The remaining faults were either untestable or potentially tested. We selected the 10
unobservable fault sites as observation points and inserted a tree of nine XOR gates whose output
was made into an added primary output. Thus, a DFT version of the processor was created. All
RTL faults were now either detected or potentially detected by the same original RTL vectors.
Table 5.3: Spectral RTL ATPG for processor circuits
Table 5.3 gives the results of the RTL spectral ATPG method. In these results, faults in the clock
network were not included. We achieve better test coverage as compared to the gate-level
sequential ATPG in lower test generation time. The coverage is slightly lower than 100% because
some faults were potentially testable and were given 50% credit [Raina97]. Since the RTL ATPG
covered almost all faults in the original circuit, the benefit of DFT was small. However, the
benefits of DFT were more for gate-level ATPG and random vectors. The test coverage plots of
the original circuit and the circuit with DFT are shown in Figures 5.3 and 5.4. Observing the
positive results of the RTL DFT technique, we plan to experiment it on circuits like s9234 where
the RTL fault coverage was low.
5.2 RTL Spectral Test Generation for Transition Delay Fault Model
We applied the RTL spectral test generation method using RTL faults defined for the transition
delay fault model on the Parwan processor [Yogi07]. The test vectors for RTL transition delay
faults were obtained using the Mentor Graphics tool FlexTest [FlexTest04]. Those RTL vectors
were analyzed for their spectrum, new vector sequences were generated using the technique
discussed above and finally they were minimized. Results were obtained on Sun Ultra 5 machines
with 256MB RAM.
19
Figure 5.3: Test coverages for the original Parwan circuit [Navabi93].
Figure 5.4: Test coverages for the Parwan circuit.
Table 5.4: Spectral characterization of Parwan by RTL vectors for transition delay fault model.
20
Table 5.4 shows the characteristics of RTL test vectors. Transition delay faults in the clock and
reset network were not included and a 50% credit was given to potentially testable faults
[Raina97]. Coverage is defined as the ratio of the number of detected faults to the total number of
detectable faults as reported by FlexTest. The last column gives the fault coverage of the 160
RTL vectors for collapsed gate-level faults in the entire circuit, excluding clock and reset faults.
After the RTL test generation for the transition delay faults, an examination of the undetected
RTL transition delay faults of the Parwan processor revealed 24 unobservable faults. The
remaining undetected faults were untestable or potentially testable. The circuit used tri-state
drivers for driving buses and to detect their faults we modeled the high-impedance state as the
previous logic state to improve its testability. It was observed that almost all of the undetected
RTL faults were on the terminals of tri-state drivers. This could be because of the functional
constraints of the processor and such faults could be functionally redundant delay faults. We
applied our RTL DFT method, selected the 24 unobservable fault sites as observation points,
condensed them using a 23 XOR gate tree and fed its output to an added output pin. All RTL
transition delay faults were now either detected or potentially detected by the same original RTL
vectors.
Table 5.5: Spectral RTL ATPG for transition delay faults for processor circuits.
Figure 5.6: Stuck-at fault coverage of transition fault vectors.
Table 5.5 gives the results for transition delay faults for Parwan processor. Table 5.6 gives the
corresponding stuck-at fault coverages of the transition delay test vectors. As observed in the
tables, we achieve better test coverage as compared to the gate-level sequential ATPG in lower
21
test generation time for both stuck-at and transition delay faults. Also the stuck-at fault coverages
obtained are close to what we achieved in the earlier section. In most cases though they are
slightly lower than what we obtained in table 5.3 because the transition delay vectors were not
targeted for the stuck-at faults. Note that the highest achievable test coverage cannot be 100% as
there was a small fraction of undetectable faults due to fault-induced uninitializability. These are
possibly (or potentially) testable faults and were given a detection credit of 50% [Raina97].
6. Future Work
6.1 FFT analysis of digital waveforms
Another way of analyzing the digital bit-streams apart from Walsh function is using Discrete
Fourier Transform (DFT) [Weisstein]. A binary bit-stream can be assumed to be a sampled
waveform of an analog signal and represented in the frequency domain. The bit-stream of ‘n’ bits
can be transformed into the frequency domain by performing an ‘n’ point DFT on the signal. In
the frequency domain, the highest frequency represented will be half of the sampling frequency;
the sampling frequency (fs) being the reciprocal of the time period at which bits are being applied.
For example consider a bit stream of length 8 with consecutive flipped bits. In the frequency
domain it will contain a single frequency component at (fs/2). Similarly a constant bit-stream of
0s or 1s will only have a D.C. component at f=0.
We can use the Discrete Fourier Transform (DFT) in place of the Walsh functions and use a
similar methodology for RTL Spectral test generation as has been discussed in the pervious
sections. There are pros and cons of doing so. An advantage of DFT is that it is invariant to time
shifts whereas Walsh functions are not. This means that a time shift of a signal will have the same
spectral decomposition as the original signal for a DFT, but not for Walsh functions. This is a
significant advantage in retrieving the periodicities and bit flipping probabilities of the signals.
The absence of a time shift relation for Walsh functions has repercussions in the convolution
theorem. For a DFT, the products of DFT transforms represent convolution in time domain.
However for Walsh functions, such straightforward relation does not exist. Hence DFT could be
better utilized in characterizing signals and systems than Walsh functions.
22
A disadvantage of DFT over Walsh functions is that, DFT computations are not easy and their
hardware implementations are consequently complex. This makes Walsh functions and their
computations easier and faster in digital hardware. However, if the use of DFT is constrained at
the algorithmic level of test generation rather than using it at the hardware level, DFT could be
efficiently utilized in spectral information retrieval.
In the proposed work we plan to investigate further the different aspects of the two transforms,
viz. DFT and Walsh. Also we would investigate the use of DFT in the previously proposed RTL
spectral test generation method.
6.2 Spectral BIST
A well known technique of testing of digital circuits with system level test control is Built-In Self
Test or BIST. This technique can apply test vectors at-speed and obtain a better defect coverage.
In a typical BIST scheme, additional hardware is inserted to generate test vectors and to sample
the outputs and decide whether the circuit under test is good or bad. One of the biggest challenges
that BIST faces is of generating good quality test vectors. This is because simple hardware test
generators lack the necessary intelligence and information required to generate test vectors with
particular characteristics which efficiently test the circuit. In the past several BIST techniques
have been implemented, which performed satisfactorily for many circuits, but not all. Random
test vector generation is a popular technique where pseudo random bit-streams are generated and
applied to the circuit under test. However, such a technique does not perform well for random
pattern resistant circuits [Eichelberger83]. The technique was then enhanced to weighted random
test vector generation where random vectors were generated with certain probabilities of being
logic ‘0’ or ‘1’ [Brglez90, Ha92, Wunderlich97]. This technique again had its shortcomings.
A spectral BIST technique can be implemented, in which the test generation logic would have the
information to generate vectors of certain characteristics which would test the circuit efficiently.
The characteristic information would primarily be the spectral information, which would carry
with it the relevant periodicity and the bit-flipping probability information. This spectral
information can be obtained using RTL test generation as discussed in the earlier sections. Test
vectors could be generated to cover the RTL faults, and then these vectors could be analyzed
23
using Walsh spectra or DFT to retrieve the spectral information. Figure 6.1 shows an example
DFT of a RTL test bit-stream generated for a test circuit. The middle point of 0 corresponds to
D.C. value and the positive and negative frequencies spread toward either direction. As can be
seen in the figure, the RTL test bit-stream exhibits certain high magnitude frequency components
represented by tall bars. If we are generate a bit-stream from some arbitrary source with similar
frequency characteristics, then we believe we shall be able to test the circuit efficiently. For this,
Magnitude
we propose a test generation scheme for BIST that will try to imitate the spectral characteristics.
- (fs/2)
+ (fs/2)
DC
-ve frequencies.
+ve frequencies
Figure 6.1: Frequency spectrum of a RTL test bit-stream generated for a test circuit.
A possible test generation scheme is shown in figure 6.2. It consists of a Linear Feedback Shift
Register (LFSR) that generates pseudo-random bit-streams, one for each input of the circuit.
These random bit-streams are then passed through a set of spectral filters, which is designed to
amplify/attenuate frequencies based on the spectral information required for each input. One
spectral filter is designed for each input of the circuit. The filtered bit-streams are then applied to
the circuit under test (CUT).
24
A convenient way of implementing a spectral filter would be to use digital filter design
techniques. Primarily there are two techniques of designing digital filters: Infinite Impulse
Spectral Filter
Circuit
Under
Test
(CUT)
MISR
LFSR
Response (IIR) and Finite Impulse Response (FIR) filter design [Weisstein].
Figure 6.2: Proposed test generation technique for BIST.
Infinite Impulse Response (IIR) filter design:
Mathematically, the IIR transfer function can be represented as:
(
)
y(n) = f y(n-1), y(n-2), ….. y(n-k), x(n), x(n-1),x(n-2), … x(n-p) … (1)
where:
y: output of filter
x: input of filter
n: time period
p: order of the filter
The current output y(n) of the filter is a function of one or more previous time period outputs
and/or one or more previous time period inputs.
Finite Impulse Response (FIR) filter design:
The transfer function for an FIR filter can be represented as:
(
)
y(n) = f x(n), x(n-1),x(n-2), … x(n-p) … (2)
25
where
y: output of filter
x: input of filter
n: time period
p: order of the filter
The current output y(n) of the filter is a function of only the inputs.
FIR and IIR filter design techniques have their own advantages and disadvantages. Since IIR
filter transfer function is a function of both the inputs ‘x’ as well as the outputs ‘y’, more memory
elements would be required to store the data bits than for an FIR filter where only the inputs ‘x’
need to be stored. Hence in the proposed method we use an FIR filter.
From Figure 6.2 we observe that the input ‘x’ from previous time periods can be stored in a
LFSR, if we use an external feedback LFSR which has an in-built shift register. Figure 6.3 shows
a schematic diagram of an external feedback LFSR being used as an input to the FIR filter. The
data bits which are generated by the external feedback network constitute the random bit-stream
and would represent the current value of ‘x’. The previous time period values of ‘x’ would be
stored in the shift register.
External feedback network
x(n-2)
x(n-p)
LFSR ((p-1)-bit shift register)
x(n-1)
x(n)
Generated
Random
bit-stream
FIR Filter
(One filter per input of CUT)
To CUT
Figure 6.3: External feedback LFSR for the use of FIR filter design
26
As an example, we consider an FIR filter with an order 31 designed for the frequency spectrum
Gain, dB
shown in Figure 6.1. The frequency response of the designed filter is as shown in Figure 6.4.
(DC)
Normalized Frequency (0 to fs/2) →
(fs/2)
Figure 6.4: Frequency response of FIR filter of order 31
To demonstrate the filtering properties of the designed filter, we generate a random bit-stream in
software and pass it through the designed filter. Figure 6.5 shows the frequency spectrum of the
random bit-stream. The frequency spectrum of the bits obtained at the output of the filter is
shown in Figure 6.6. By comparing Figure 6.1 and Figure 6.6, we find certain similar
characteristics. Thus using the FIR filter, we obtained a bit-stream which has similar spectral
characteristics as the original bit-stream.
We experimented with two ISCAS’89 benchmark circuits, s382 and s526. We generated test
vectors for the RTL stuck-at faults (as defined in previous sections) and obtained the DFT of the
bit-streams going into each of the inputs. We then designed an FIR filter for each input to imitate
the frequency distributions. We generated a total of 65000 random vectors in software, passed
them through the FIR filters designed for each of the inputs and then applied it to the circuit under
test. Tables 6.1 and 6.2 give the results for the two circuits. We compare the number of faults
detected by this method with those detected by Mentor Graphics sequential ATPG tool FlexTest
27
Magnitude
- (fs/2)
+ (fs/2)
DC
-ve frequencies.
+ve frequencies
Magnitude
Figure 6.5: Frequency spectrum of a random bit-stream.
- (fs/2)
+ (fs/2)
DC
-ve frequencies.
+ve frequencies
Figure 6.6: Frequency spectrum of a random bit-stream after passing through FIR filter.
28
and random vectors. As observed in the tables, the proposed method detects equal or greater
number of faults than those detected by FlexTest. The random vectors exhibit a spectrum with no
particular characteristics. The filtered vectors exhibit spectral characteristics conforming to those
of their respective inputs. Thus by shaping the bit-streams to exhibit certain spectral properties, a
significant enhancement in the number of detected faults can be achieved as compared to random
vectors. Figures 6.7 and 6.8 show test coverages versus number of vectors applied, for both the
proposed method and random vectors, for s382 and s526, respectively. With these encouraging
preliminary results we plan to investigate this method further for larger circuits. Also as described
earlier, the random patterns were generated using software. Experimentation on an LFSR-based
implementation of the method is required.
Test Set
No. of
faults
detected
Total no.
of faults
Flextest vectors
Random vectors
Filtered vectors
364
44
364
485
485
485
Table 6.1 Experimental results for s382
Test Set
No. of
faults
detected
Total no.
of faults
Flextest vectors
Random vectors
Filtered vectors
448
55
450
639
639
639
Table 6.2 Experimental results for s526
s382 - Test Coverage vs No. of Vectors
100
Test Coverage
80
60
40
20
0
1
10
100
1000
10000
100000
No .of Vectors
Random
Filtered Random
Figure 6.7: Test coverage versus number of vectors for s382
29
s526 - Test Coverage vs No. of vectors
100
Test coverage
80
60
40
20
0
1
10
100
1000
10000
100000
No. of vectors
Random
Filtered Random
Figure 6.8: Test coverage versus number of vectors for s382
7. Conclusion
In this work we have presented a new method of RTL test generation using spectral techniques.
Test vectors for RTL faults are analyzed using Hadamard matrix to extract important features and
new vectors are generated retaining those features. We observe improved test coverage and lower
test generation time as compared to a sequential gate-level ATPG tool. Since the method is based
on RTL test generation, it has the advantages of lower memory and test generation time
complexities. It enables the testability appraisal at RTL, and hence efforts can be made to
improve testability when the design is conceptualized at higher levels of abstraction. An XOR
observability tree designed at the RT level improved the gate-level fault coverage. Thus, RTL test
methodology effectively reveals the bottlenecks in the testability of the circuit. Further, RTL
ATPG enables the testing of cores for whom only the functional information is known.
As a future work, we plan to pursue the investigation of FFT analysis of bit-streams for RTL
spectral test generation. We plan to probe the idea of a spectral test generator for BIST. This
would involve comparing the BIST aspects of Walsh, DFT and weighted random vectors.
Furthermore we plan on conducting research on BIST signature analysis using Walsh or DFT.
30
Work Time-table
May
2007
June
2007
July
2007
Aug.
2007
Sept.
2007
Oct.
2007
Nov.
2007
Dec.
2007
Jan.
2008
Feb.
2008
Write dissertation
Defend
FFT analysis
of bit-streams
Spectral BIST research
References:
[Beauchamp84] K. G. Beauchamp, Applications of Walsh and Related Functions with an Introduction to
Sequency Theory. Orlando, FL: Academic Press, 1984.
[Brglez90] F. Brglez, C. Gloster, and G. Kedem, “Built-In Self-Test with Weighted Random-Pattern
Hardware," in Proc. IEEE Int. Conf. Computer Design, Sept. 1990, pp. 161-167.
[Chen02] X. Chen and M. S. Hsiao, “Characteristic Faults and Spectral Information for Logic BIST," in
Proc. Int. Conf. on CAD, Nov. 2002, pp. 294-298.
[Chen06] X. Chen and M. S. Hsiao, “Testing Embedded Sequential Cores in Parallel Using SpectrumBased BIST," IEEE Trans. Computers, vol. 55, no. 2, pp. 150-162, Feb. 2006.
[Davidson81] R. P. Davidson et al., “BELLMAC-32 A Self-Testable 32bit Microprocessor," in Proc.
International Test Conf., 1981, pp. 15-20.
[Devanathan06] S. K. Devanathan and M. L. Bushnell, “Sequential Spectral ATPG Using the Wavelet
Transform and Compaction," in Proc. 19th International Conference on VLSI Design, 2006, pp. 407-412.
[Drineas03] P. Drineas and Y. Makris, “Independent Test Sequence Compaction through Integer
Programming," in Proc. Int. Conf. Computer Design, 2003, pp. 380-386.
[Eichelberger83] E. B. Eichelberger and E. Lindbloom, “Random Pattern Coverage Enhancements and
Diagnosis for LSSD Logic Self-Test," IBM Journal Research and Development, vol. 27, no. 3, pp. 265272, May 1983.
[Falkowski02] B. J. Falkowski, “Spectral Testing of Digital Circuits," VLSI Design, vol. 14, no. 1, pp. 83105, 2002.
[FlexTest04] Mentor Graphics, FastScan and FlexTest Reference Manual, 2004.
[Fourer93] R. Fourer, D. M. Gay, and B. W. Kernighan, AMPL: A Modeling Language for Mathematical
Programming. South San Francisco, California: Scientific Press, 1993.
[Fox77] J. R. Fox, “Test-Point Condensation in the Diagnosis of Digital Circuits," Proc. IEE, vol. 124, no.
2, pp. 89-94, Feb. 1977.
[Ghosh99] I. Ghosh and M. Fujita, “Automatic Test Pattern Generation for Functional RTL Circuits Using
Assignment Decision Diagrams," in Proc. 35th Design Automation Conf., 1999, pp. 43-48.
31
[Giani01a] A. Giani, S. Sheng, M. S. Hsiao, and V. D. Agrawal, “Effecient Spectral Techniques for
Sequential ATPG," in Proc. Design, Autom. & Test in Europe (DATE) Conf., 2001, pp. 204-208.
[Giani01b] A. Giani, S. Sheng, M. S. Hsiao, and V. D. Agrawal, “Novel Spectral Methods for Built-In SelfTest in a System-on-a-Chip Environment," in Proc. 19th IEEE VLSI Test Symp., 2001, pp. 163-168.
[Goloubeva02] O. Goloubeva, G. Jervan, Z. Peng, M. Sonza Reorda, and M. Violante, “High-level and
Hierarchical Test Sequence Generation," in Proc. of HLDVT, 2002, pp. 169-174.
[Guo99] Ruifeng Guo; Reddy, S.M.; Pomeranz, I., “PROPTEST: a property based test pattern generator for
sequential circuits using test compaction”, Design Automation Conference, 1999. Proceedings. 36th, Vol.,
Iss., 1999, Pages:653-659
[Ha92] D. S. Ha and S. M. Reddy, “On the Design of Random-Pattern Testable PLA Based on Weighted
Random-Pattern Testing," J. Electron. Testing: Theory and Applications, vol. 3, no. 2, pp. 149-157, May
1992.
[Hayes73] J. P. Hayes and A. D. Friedman, “Test Point Placement to Simplify Fault Detection," in Proc.
Fault Tolerant Computing Symp., 1973, pp. 73-78
[Hsiao84] T.-C. Hsiao and S. C. Seth, “An Analysis of the Use of Rademacher-Walsh Spectrum in
Compact Testing," IEEE Trans. Comput., vol. 33, pp. 934-938, Oct. 1984.
[Hurst85] S. L. Hurst, D. M. Miller, and J. C. Muzio, Spectral Techniques in Digital Logic. Orlando, FL:
Academic Press, 1985.
[Iyengar89] V. S. Iyengar and D. Brand, “Synthesis of Pseudo-Random Pattern Testable Designs," in Proc.
International Test Conf., 1989, pp. 501-508.
[Josephson05] D. Josephson and B. Gottlieb, “Silicon Debug," in D. Gizopoulos, editor, Advances in
Electronic Testing: Challenges and Methodologies, Springer, 2005. Chapter 3.
[Kang07] Jian Kang, Sharad C. Seth, Vijay Gangaram, "Efficient RTL Coverage Metric for Functional Test
Selection," vts, pp. 318-324, 25th IEEE VLSI Test Symposium (VTS'07), 2007.
[Kantipudi06] K. R. Kantipudi and V. D. Agrawal, “On the Size and Generation of Minimal N-Detection
Tests," in Proc. 19th Int. Conf. VLSI Design, 2006, pp. 425-430.
[Kantipudi07] “A Reduced Complexity Algorithm for Minimizing N-Detect Tests”, Kantipudi, K.R.;
Agrawal, V.D., VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems.,
20th International Conference on, Vol., Iss., Jan. 2007 Pages:492-497
[Kasturirangan02] G. Kasturirangan and M. S. Hsiao, “Spectrum-Based BIST in Complex SOCs," in Proc.
20th IEEE VLSI Test Symp., Apr. 2002, pp. 111-116.
[Khan06] O. I. Khan and M. L. Bushnell, “Aliasing Analysis of Spectral Statistical Response Compaction
Techniques," in Proc. 19th International Conference on VLSI Design, 2006, pp. 801-806.
[Kim98] H. Kim and J. P. Hayes, “High-Coverage ATPG for Datapath Circuits with Unimplemented
Blocks," in Proc. International Test Conf., 1998, pp. 577-586.
[Leonardo04] Leonardo Spectrum User’s Guide, 2004.
[Marques98] J. P. Marques-Silva, “Integer Programming Models for Optimization Problems in Test
Generation," in Proc. IEEE Asia-South Pacific Design Automation Conf., 1998, pp. 481-487.
32
[Maxwell00] P. Maxwell, I. Hartanto, and L. Bentz, “Comparing Functional and Structural Test," in Proc.
International Test Conf., 2000, pp. 336-343.
[McCluskey00] E. J. McCluskey, “Stuck-Fault Tests vs. Actual Defects," in Proc. Int. Test Conf., 2000, pp.
336-343.
[Navabi93] Z. Navabi, Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993.
[Nigh97] P. Nigh, W. Needham, K. Butler, P. Maxwell, and R. Aitken, “An Experimental Study
Comparing the Relative Effectiveness of Functional, Scan, IDDq and Delay-Fault Testing," in Proc. IEEE
VLSI Test Symp., 1997, pp. 459-464.
[Noyes] J. Noyes and E. W. Weisstein. Linear Programming. From MathWorld-A Wolfram Web Resource.
http://mathworld.wolfram.com/LinearProgramming.html.
[Raina97] R. Raina, C. Njinda, and R. F. Molyneaux, “How Seriously Do You Take Possible-Detect
Faults?,” in Proc. Intnternational Test Conf., Nov. 1997, pp. 819–828.
[Ravi01] S. Ravi and N. K. Jha, “Fast Test Generation for Circuits with RTL and Gate-Level Views," in
Proc. International Test Conf., 2001, pp. 1068-1077.
[Rudnick92] E. M. Rudnick, V. Chickermane, and J. H. Patel, “Probe Point Insertion for At-Speed Test," in
Proc. IEEE VLSI Test Symp., 1992, pp. 223-228.
[Susskind83] A. K. Susskind, “Testing by verifying Walsh coefficients," IEEE Trans. Computers, vol. 32,
no. 2, pp. 198-201, Feb. 1983.
[Thaker03] P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, “A Test Evaluation Technique for VLSI
Circuits Using Register-Transfer Level Fault Modeling," IEEE Trans. CAD, vol. 22, no. 8, pp. 1104-1113,
Aug. 2003.
[Thornton01] M. A. Thornton, R. Drechsler, and D. M. Miller, Spectral Techniques in VLSI CAD. Boston:
Springer, 2001.
[Weisstein] E. W. Weisstein. From MathWorld-A Wolfram Web Resource. http://mathworld.wolfram.com.
[Wunderlich97] H.-J. Wunderlich, “Self Test using Unequiprobable Random Patterns," in Proc. 17th Int.
Symp. Fault-Tolerant Computing, July 1997, pp. 258-263.
[Yogi06] N. Yogi and V. D. Agrawal, “High-Level Test Generation for Gate-Level Fault Coverage," in
15th IEEE North Atlantic Test Workshop, May 2006.
[Yogi06a] N. Yogi and V. D. Agrawal, “Spectral Characterization of Functional Vectors for Gate-Level
Fault Coverage
Tests," in Proc. 10th VLSI Design and Test Symposium, Aug. 2006, pp. 407-417.
[Yogi06b] N. Yogi and V. D. Agrawal, .Spectral RTL Test Generation for Gate-Level Stuck-at Faults,. in
Proc. 15th Asian Test Symposium, Nov. 2006, pp. 83.88.
[Yogi07] N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors”, in Proc. 20th
International Conf. VLSI Design, Jan. 2007, pp. 473.478.
[Yogi07a] N. Yogi and V. D. Agrawal, “Transition Delay Fault Testing of Microprocessors by Spectral
Method," in Proc. 39th Southwestern Symp. on System Theory, Mar. 2007, pp. 283-287.
33
[Yogi07b] N. Yogi and V. D. Agrawal, “Optimizing Tests for Multiple Fault Models”, in 16th IEEE North
Atlantic Test Workshop, May 2007.
[Zhang04] J. Zhang, M. L. Bushnell, and V. D. Agrawal, “On Random Pattern Generation with the Selfish
Gene Algorithm for Testing Digital Sequential Circuits," in Proc. International Test Conf., 2004, pp. 617626.
Research Papers :
N. Yogi and V. D. Agrawal, “High-Level Test Generation for Gate-Level Fault Coverage," in 15th IEEE
North Atlantic Test Workshop, May 2006.
N. Yogi and V. D. Agrawal, “Spectral Characterization of Functional Vectors for Gate-Level Fault
Coverage Tests," in Proc. 10th VLSI Design and Test Symposium, Aug. 2006, pp. 407-417.
N. Yogi and V. D. Agrawal, .Spectral RTL Test Generation for Gate-Level Stuck-at Faults,. in Proc. 15th
Asian Test Symposium, Nov. 2006, pp. 83.88.
N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors”, in Proc. 20th
International Conf. VLSI Design, Jan. 2007, pp. 473.478.
N. Yogi and V. D. Agrawal, “Transition Delay Fault Testing of Microprocessors by Spectral Method," in
Proc. 39th Southwestern Symp. on System Theory, Mar. 2007, pp. 283-287.
N. Yogi and V. D. Agrawal, “Optimizing Tests for Multiple Fault Models”, in 16th IEEE North Atlantic
Test Workshop, May 2007.
34