Analog SPICE Behavioral Model for Digital I/O Pin
Based on IBIS Model
*Won-Ok Kwon, *Kyoung Park, **Pyung Choi, **Chang-Gean Woo
*Computer Architecture Research Team, Computer & Software Research Laboratory in ETRI
161 Gajeong-dong, Yuseong-gu, Daejeon, 305-350, South KOREA
**School of Electrical Engineering and Computer Science, Kyungpook National University
Daegu, 702-701, South KOREA
Abstract: - IBIS (I/O buffer information specification) model is widely used in signal integrity analysis of
on-board high-speed digital systems. But many other circuit level simulations require conversion of given IBIS
model to equivalent SPICE behavioral model. In this paper, curve-fitting non-linear model algorithm is proposed
to extract more accurate switching time coefficients from pullup and pulldown transistors at IBIS model which has
only one-pair voltage-time table. This algorithm is originated CMOS inverter switching operating characteristics.
The equivalent SPICE behavioral model can be built with these extracted switching time coefficients and the
proposed algorithm is verified through SPICE simulation.
Key-Words: - IBIS, SPICE, Behavioral model, Switching time coefficient, Signal Integrity
1 Introduction
The higher integration density of digital circuits and
clock speed, the more effective simulation that
analyzes signal integrity (SI) on PCB is needed. Such
simulation is needed electrical model that describes
driver and receiver’s behavior of integrated circuit
(IC). For this purpose, IBIS model is made and it is
used to analyze SI on PCB.
Recently, IBIS model becomes standard to express
input/output behavioral characteristics of IC providing
current versus voltage (DC IV), rising and falling
voltage versus time (VT) and packaging information
of I/O pin in type of table information. IBIS model has
many advantages compared to SPICE model. It can
protect proprietary information (IP) about both the
circuit design and the underlying fabrication process
and run much faster than SPICE model. At the same
time no accuracy is sacrificed. So IBIS model has
become widely used among EDA vendors,
semiconductor vendors and system designers, and it
becomes an international standard.
But widely used SPICE-based EDA tools do not
support IBIS model in electronic analysis on chips.
Therefore the conversion of IBIS model into
equivalent SPICE model becomes significant to many
applications. The conversion of IBIS into SPICE
algorithm can make various SI analysis on PCB faster
and more efficiently.
This paper shows concrete method which converts
IBIS model into SPICE behavioral model. And it also
shows new algorithm which extracts switching time
coefficient (STC) to represent dynamic feature of
output buffer.
Generally STC can be extracted accurately from IBIS
model which has two-pair VT table [1]. But this
algorithm has a defect that it can’t apply to IBIS model
with one-pair VT table. On the other hand, paper [2]
shows general STC extraction algorithm from one-pair
VT table. But it has a defect of low accuracy in
compared with STC extracted two-pair VT table. This
paper proposes the curve-fitting type non-linear STC
extraction method which is as accurate as STC
extracted from the two-pair VT table but it can be
extracted from one-pair VT table. And its accuracy
verified through SPICE simulation under some test
load conditions.
SPICE Model
IBIS Model
Extract Swithcing
Time Coefficient
Input Behavioral
Model
Output Behavioral
Model
Test Topology
SPICE Model - IBIS to SPICE Behavioral Model Compare
Fig. 1. Verification flow of IBIS SPICE behavioral
2
Building IBIS analog
behavioral model
SPICE
Vcc
Test fixture
Ipu(t)
2.1 IBIS structure model
Vdie(t)
IBIS output buffer behavioral model widely divides
four elements as Fig. 2. There are pullup transistor,
pulldown transistor, power clamp diode, ground clamp
diode of DC static table information and rising, falling
VT table of dynamic table information and packaging
lumped RLC and pad capacitor.
Iout(t)
R_fix
die
Ipd(t)
V_fix
C_comp
+
-
Fig. 3. IBIS VT table measurement circuit
Vcc
Pullup
1
POWER_clamp
2
3
Rising
Falling
VT table
Pulldown
4
L_pkg
R_pkg
C_comp
C_pkg
GND_clamp
Fig. 2. IBIS output buffer behavioral model
DC IV curve of pullup and pulldown which has no
influences on each transistor is in the steady-state
value. That is, DC IV curve of logic high state is
recorded at the pullup table. DC IV curve of logic low
state is recorded at the pulldown table. DC IV curve of
clamping diode is recorded at power clamp table and
ground clamp table individually.
When the output IBIS model in Fig. 2. is translated
into the analog SPICE behavioral model, DC IV table
represented to G-table which is voltage controlled
current source (VCCS) of SPICE. Packaging lumped
RLC and pad capacitor can be used by SPICE directly.
So all static characteristics can be translated into
SPICE without much trouble. But the main problem is
how to generate a suitable large signal model for
transient simulation based on IBIS dynamic
information, VT table.
Fig. 3. is VT table measurement circuit. In this circuit,
die node voltage, Vdie(t) is measured by timescale
under the condition of eliminating packaging
component and adding specific load, R_fix and V_fix.
Most IBIS model provide VT table information and
optionally over IBIS version 2.1 provide two-pair VT
table information under two specific load conditions.
Two-pair VT table model get the data in two different
load condition at V_fix. And its value is Vcc and
GND. One-pair VT table model get the data in only
one load condition at V_fix. And its value is Vcc or
GND. As the result of paper [1], there is much
difference at transient simulation result between
purely based on a DC behavioral model which don’t
represent switching information of buffer and SPICE
model simulation. Generally, STC which is extracted
from VT table shows dynamic characteristics of
pullup and pulldown transistor. So it is very important
to represent STC effect accurately when IBIS
translates to SPICE behavioral model.
2.2
Analog SPICE behavioral model
When a high-to-low state transition takes place,
transient current has transit process from high
steady-state to low steady-state gradually.[2] During
transition, initial high steady-state current is
correspond to pullup DC IV curve and end of low
steady-state current is correspond to pulldown DC IV
curve. That is, pullup transistor gradually transits from
turn-off state to turn-on and pulldown transistor
gradually transits from turn-on state to turn-off. On the
contrary, a low-to-high state transition will change
from low steady-state to high steady-state through
transition state. That is, at low-to-high transition,
pullup transistor’s STC increases from ‘0’to ‘1’and
pulldown transistor’s STC decreases from ‘1’to ‘0’.
The ‘0’ value of STC means turn-off state of transistor
and ‘1’ means turn-on state. We define STC of pullup
transistor and pulldown transistor as Ku(t) and Kd(t)
respectively. When considering rising and falling case,
STC can be defined as Kur(t), Kdr(t), Kuf(t) and
Kdf(t).
Switching Time Coefficient
DC IV table of pullup and pulldown transistor is
represented by Ipu(V) and Ipd(V) as VCCS. Then
switching transient current of pullup transistor is
represented as Kur(t) · Ipu(V) or Kuf(t) · Ipu(V).
Similarly, switching transient current of pulldown
transistor is represented as Kdr(t)·Ipd(V) or Kdf(t)·
Ipd(V). Fig. 4. shows the analog SPICE behavioral
model of IBIS output buffer behavioral model in Fig.
2.
1.0
Kur(t)
Kdr(t)
Kur(t)+Kdr(t)
0.5
0.0
Vcc
0
5e-10
1e-9
2e-9
2e-9
Time (seconds)
Kur(t)  Ipu (V)
Kuf(t)  Ipu (V)
Fairchild Semiconductor Corporation
16-bit VCX Buffer
IBIS Model of 74VCX162244MTD (3.3V) 48 TSSOP (MTD) Package
Ipc(V)
VCCS
VCCS
L_pkg
Kdr(t)  Ipd (V)
Kdf(t)  Ipd (V)
R_pkg
C_comp
Output Pin
C_pkg
Igc(V)
Fig. 4. IBIS analog SPICE behavioral model
2.3
Switching time coefficient extraction
method
We find the extraction method of four STC that
multiplied to the pullup and pulldown transistor’s DC
IV table. By using circuit equation in Fig. 3., transient
current Iout(t) can be expressed formula (1).

V (t)-V fix 
d

I out(t)   Ccomp Vdie(t)  die


dt
R
fix


(1)
And in Fig. 4. Iout(t) is equal to formula (2).
I out(t)  Kux(t )  I pu (Vdie )  Kdx(t )  I pd (Vdie )
 I pc (Vdie )  I gc (Vdie )
(2)
Fig. 5. Switching time coefficient extracted from
2-Pair method
Two unknown variables, Kux(t) and Kdx(t) can be
solved under two different VT table condition at
simultaneous equation of formula (1) and (2). In Fig.
5. shows STC extracted from 74VCX162244 IBIS
model which is Fairchild Semiconductor’s 16bit
buffer.
Unknown variables, Kux(t) and Kdx(t) can be solved
easily from simultaneous equation if two-pair VT
table is given. But it is impossible to solve
simultaneous equation if only one-pair VT table is
given. Actually many semiconductor vendors still
provide only one-pair VT table IBIS model. To solve
these equations, we can simply think about steady
state equation. Formula (3) represents linearized
switching process using steady state of STC. This is
the initial and final condition during switching. Such
STC extraction method is called linear method.
Kux(t )  Kdx(t )  1
(3)
But linear method has low accuracy disadvantage
because it can’t represent practical switching process.
In real case Fig. 5., sum of Kur(t) and Kdr(t) is not 1
during switching time. Only when initial and steady
state, sum of Kur(t) and Kdr(t) close to 1. So we can
see linear method is not a accurate method to extract
STC.
This paper proposes non-linear method using
switching characteristic of CMOS buffer extract more
accurate STC in case only one-pair VT.
Fig. 6. shows switching state change of CMOS
inverter. When low-to-high switching, NMOS
transistor(Mn) state changes to linear region passing
through saturation region and PMOS(Mp) transistor
state changes to saturation region passing through
linear region. And the change of STC is equals to
change of gate voltage, VGS of MOSFET [2].
MOSFET drain current is proportional to gate voltage,
VGS by first order in linear region and by second order
in saturation region. Drain current follows formula (4)
in NMOS’s saturation region and it follows formula
(5) in linear region.

(4)
I D  K (VGS  Vth ) 2
2

V 2 DS 
I D   (VGS  Vth )VDS 
2 

(5)
The MOS transistor’s drain current relates with gate
voltage and it is proportional to STC. So STC can be
used at formula (4) and (5) instead of VGS.
Fig. 7. shows curve fitting type STC using CMOS
inverter’s switching characteristic. This paper defines
this extraction STC method as non-linear method.
VIN
VCC
VIN
2.4
VCC
VCC-|VTP|
Mp
VOUT
Mn
VOUT+VTN
VOUT-|VTP|
VTN
MP: Cut off
MN: Linear
MP: Saturation
MN: Linear
MP: Saturation
MN: Saturation
MP: Linear
MN: Saturation
MP: Linear
MN: Cut off
(a)
(b)
Fig. 6. Inverter characteristic (a) Inverter circuit (b)
Inverter switching state changing
Kur(t), Kdf(t)
Time Coefficient
Kdr(t), Kuf(t)
0.6
Linear Method
0.4
Non-Linear Method
0.2
0.0
Pf
50%
Output structure
We get three type of SCT, 2-pair model, non-linear
model and linear model. Now we verify each STC’s
accuracy by SPICE simulation. We put into values at
Fig. 4. SPICE structure. This is the prototype of output
structure which is proposed by Bob Ross.[4]
3 SPICE simulation result
This paper performed simulation using HSPICE
model of 74AC244SC IBIS model used as memory
address
driver,
clock
driver
and
bus
transmitter/receiver which was provided Fairchild
Semiconductor Corporation. And the 74ACT244SC
IBIS model basically provide with two-pair VT table.
Three behavioral models and SPICE model simulation
output are compared each other. We select three test
simulation load condition; VT table loads, datasheet
standard load, transmission line and receiver load as
Fig. 8.
1.0
0.8
As above mentioned, during the rising process, pullup
transistor STC, Kur(t) change from ‘0’ to ‘1’ and
pulldown transistor STC, Kdr(t) change from ‘1’ to ‘0’.
The other way, when the falling process Kuf(t) change
from ‘1’ to ‘0’ and Kdf(t) change from ‘0’ to ‘1’.
In non-linear method, STC value changes like inverter
switching characteristic. So Kur(t) and Kuf(t) follow
PMOS transistor’s transition process. Similarly Kdr(t)
and Kdf(t) follow NMOS transistor’ transition process.
For example, Kdf(t) change from cut-off region to
linear region passing through saturation region. And
Kdf(t) value curve follows proportional equation each
region.
And Pf point is set up 50% of switching time because
turn-off process takes less time than turn-on process of
general CMOS buffer. So Kdr(t) and Kuf(t) value
close to ‘0’ in the middle of switching time.
100%
Switching Time
Fig. 7. Switching time coefficients of linear method
and non-linear method
Vcc
5
Vcc
R_fixture
4
500 Ohm
DUT
V_fixture +
-
30pF
(a) (b)
(c)
Vcc
Vcc
Z0=50, T0=1ns
DUT
Voltage [V]
DUT
3
2
2-Pair model
Linear model
Non-Linear model
SPICE model
1
DUT
0
(d)
0
2x10-9
4x10-9
6x10-9
8x10-9
10x10-9
Time [sec]
Fig. 8. IBIS SPICE behavioral model test load (a)(b)
IBIS VT table load (c) Standard datasheet load (d)
Driver and receiver load
5
4
4
3
Voltage [V]
5
3
Voltage [V]
(c) Rising VT table (V_fix=3.3V, R_fix=75)
2-Pair model
Linear model
Non-Linear model
SPICE model
2
1
2
1
0
2-Pair model
Linear model
Non-Linear model
SPICE model
-1
0
0
2x10-9
4x10-9
6x10-9
8x10-9
10x10-9
Time [sec]
-1
0
2x10-9
4x10-9
6x10-9
8x10-9
10x10-9
Time [sec]
(d) Rising VT table (V_fix=0V, R_fix=75)
Fig. 9. VT table load condition simulation results
(a) Rising VT table (V_fix=0V, R_fix=75)
Fig. 9. shows simulation result about four different
VT table load condition. The measure an index of
model accuracy is how close to SPICE model. We can
see 2-pair model is most correspondent to SPICE
model. It’s very reasonable result. But linear model
which use only one-pair VT table, has much difference
compared with SPICE model. Non-linear model that
this paper proposed shows shorter delay than linear
model and shows good performance in all VT load
conditions. But it is still some performance gap
compared with 2-pair model.
5
Voltage [V]
4
3
2-Pair model
Linear model
Non-Linear model
SPICE model
2
1
0
0
2x10-9
4x10-9
6x10-9
8x10-9
Time [sec]
(b) Falling VT table (V_fix=3.3V, R_fix=75)
10x10-9
The standard datasheet test load condition is using
30pF capacitor and 500register as Fig.8. And the
simulation result shows in Fig. 10. In this case, 2-pair
model and non-linear model shows similar accuracy.
And linear model still has much delay.
Fig. 11. shows simulation result using transmission
line (Z0=50, td=1nS) and receiver load. Also 2-pair
model and non-linear model shows better performance
than linear model. So when only one-pair VT table
given, we can get more accurate result using
non-linear model.
7
6
5
Voltage [V]
4
3
2
1
2-Pair model
Linear model
Non-Linear model
SPICE model
0
-1
-2
0
5x10-9
10x10-9
15x10-9
can only get one-pair VT table. In this case, we usually
use linear method to solve STC. But this method can’t
represent accurately switching characteristic of output
buffer. So this paper proposed more accurate
extraction STC algorithm than linear method when
given one-pair VT table. We called this method is
non-linear method. The STC of non-linear method is
extracted from operation characteristic of NMOS and
PMOS of CMOS invert. The drain current is
proportion to VGS and VGS is proportion to STC. So
STC effects on NMOS and PMOS transistor just like
VGS. We extract STC value by using this relation and
do simulation using real IBIS model and compared
with SPICE model result. The result shows that
non-linear model more accurate than linear model
when given one-pair VT table. So this non-linear
algorithm useful STC extraction at IBIS model with
one-pair VT table.
20x10-9
Time [sec]
Fig. 10. Standard datasheet test load simulation result
7
6
5
Voltage [V]
4
3
2
1
0
2-Pair method
Non-linear method
Linear method
SPICE model
-1
-2
0
5x10-9
10x10-9
15x10-9
20x10-9
25x10-9
30x10-9
Time [sec]
Fig. 11. Driver and receiver simulation result
4 Conclusion
The IBIS has used in many signal integrity simulations.
For more various circuit simulation, IBIS table data
need to convert SPICE behavioral model. At this
conversion processor, STC which is represented
transistor’s transient characteristic factor extraction is
very important to make accurate SPICE behavioral
model. When IBIS model provide two-pair VT table,
STC can be solved accurately. But in many case we
References:
[1] Ying Wang, Han Ngee Tan, "The Development of
Analog SPICE Behavioral Model Based on IBIS
Model", 9th Great Lakes Symposium on VLSI,
101-104, 1999.
[2] Peivand F. Tehrani, Yuzhe Chen, Jiayuan Fang,
extraction of Transient Behavioral Model of
Digital I/O Buffers from IBIS, 46th IEEE
Electronic Components&Technology Conference,
Orlando, May 28-31, 1996, pp. 1009-1015.
[3] Derrick Duehren, Will Hobbs, Arpad Muranyi,
Robin Rosenbaum, "I/O buffer modeling spec
simplifies simulation for high-speed systems",
Intel corporation, Sep. 1994.
[4] Charies H. Small, "IBIS vs. SPICE : has one
emerged as the best for board-level simulation?",
Electronic systems, June 1999.
[5] Arpad Muranyi, "Introduction to IBIS models and
IBIS model making", Intel Corporation, April
1999.
[6] Syed B. Huq, "Effective Signal Integrity Analysis
using IBIS Models" DesignCon2000 Outstanding
Paper Award, Feb. 2000.
[7] I/O Buffer Information Specification IBIS Version
2.1, Dec. 1995.
[8] Muhanmmand H. Rashid, "SPICE for Circuits and
Electronics Using PSpice", 1990.