3. A Top-Level View of Computer Function and Interconnection
True or False:
1. T/F - The buses that connect different parts of the processor can be
hierarchical to improve the performance.
ANS: T
2. T/F - Instructions are also executed out-of-order in the Von Neumann
machine.
ANS: F
3. T/F - Instead of hard-wiring the units, the software is used to interpret and
execute instructions in a general purpose system.
ANS: T
4. T/F - The program counter stores the address of the next instruction to be
executed.
ANS: T
5. T/F - The fetched instructions are stored in the Accumulator register.
ANS: F
6. T/F - The next address calculation needs an accumulator.
ANS: T
7. T/F - Interrupts are parts of the program that can cause the processor to
stop.
ANS: F
8. T/F - All interrupts are handled by the interrupt handler.
ANS: T
9. T/F - Multiple interrupts cannot be handled by the processor.
ANS: F
10. T/F - I/O modules can have direct access to the memory.
ANS: T
11. T/F - Interconnect lines that connect between different units of the
processor can only transmit bit by bit information.
ANS: F
12. T/F - If a module needs to transmit data, the data is sent through the
buses immediately.
ANS: F
13. T/F - Data transfer between modules/units cannot be controlled.
ANS: F
14. T/F - The PCI bus is used for all high speed I/O transfers.
ANS: T
15. T/F - Interrupt request is a PCI command.
ANS: F
16. T/F - The PCI card can have pins for error reporting.
ANS: T
Multiple Choice Questions:
1. How are data and instructions stored in the Von Neumann architecture?
A. In separate memories
B. Dual ported memory
C. Unified read-write memory
D. None of the above
ANS: C
2. What are the parts of an instruction cycle ?
A. Fetch and Execute Cycle
B. Fetch, decode and execute cycles
C. Decode and Store cycle
D. Fetch, decode, execute and store.
ANS: A
3. Where is the fetched instruction stored?
A. Instruction register
B. Program Counter
C. Instruction buffer register
D. None of the above
ANS: A
4. The only data register in the processor is
A. Store register
B. Data Buffer register
C. Accumulator
D. Value register
ANS: C
5. What are the register(s) involved in reading & writing data/instruction to the
memory?
A. Memory address and memory buffer register
B. Store register
C. Program counter
D. Write back and Instruction register
ANS: A
6. Which of the following is not a state of the instruction cycle?
A. Operand address calculation
B. Data write back
C. Instruction fetch
D. None of the above.
ANS: B
7. Which of the following is a type of interrupt?
A. I/O interrupt
B. Program Interrupt
C. Hardware/power failure
D. All of the above
ANS: D
8. Which of the following approach is used to handle multiple interrupts?
A. Parallel interrupt processing
B. Disable interrupts and priority assignment
C. Interrupt wait
D. None of the above.
ANS: B
9. What are the interconnection wires not in the bus structure?
A. Data lines
B. Instruction lines
C. Address lines
D. Control lines
ANS: B
10. List a few pins that are not in the memory, but present in the I/O module
A. Control signals
B. Interrupt Signals
C. External data
D. B & C above
ANS: D
11. To which of the following buses is the memory connected to?
A. High-performance bus
B. Control bus
C. System Bus
D. Interface bus
ANS: C
12. The local bus connects which two components of the system?
A. Memory and I/O module
B. Processor and cache
C. Cache and Register bank
D. None of the above
ANS: B
13. What signals are used to validate data and instructions?
A. Timing signals
B. Control signals
C. Acknowledgement signals
D. Interrupt signals
ANS: A
14. In which type of timing does the clock act as a reference?
A. Interrupt timing
B. Asynchronous timing
C. Synchronous timing
D. Sequential timing
ANS: C
15. Which of the following is not a PCI bus functional group?
A. Error correcting pins
B. System pins
C. Arbitration pins
D. Interface control pins
ANS: A
16. Which of the following is a bus arbitration scheme?
A. Round-robin
B. Priority
C. First come first serve
D. All of the above.
ANS: D
Fill up the blanks:
1. The PCI makes use of a _____________ and ____________ scheme for
arbitration
ANS: centralized; synchronous
2. Every data transfer consists of a _______________ phase and one or more
______________ phases.
ANS: address; data
3. _________________ is scheme where arbitration is done while the bus
master transfers data.
ANS: Hidden arbitration
4. ______________ command is used to broadcast message to more than one
receiver.
ANS: Special cycle
5. Reset and test pins fall under the _____________ category.
ANS: System pins
6. _______________ is where the occurrence of one event is referenced with the
previous one.
ANS: Asynchronous timing
7. The method of using same bus lines for multiple purposes is called
____________.
ANS: Time multiplexing
8. Physical dedication refers to the use of ____________ connecting a ________.
ANS: Multiple buses; subset of modules
9. The small computer system interface is used to connect ______________ to
the buses.
ANS: Disk drives
10. ___________ are used to designate the source or destination of the data on
the data bus.
ANS: Address lines
11. ____________________ is the connection of paths connecting the various
modules of the system.
ANS: Interconnection structure
12. _________________ is the operation used y the I/O to access the memory.
ANS: Direct Memory Access (DMA)
13. _____________ holds the starting address of an interrupt handler routine.
ANS: Program counter (PC)
14. ____________ are primarily provided to improve the efficiency of the system.
ANS: Interrupts
15. __________________ is responsible for allocating time on the bus.
ANS: Bus arbiter
16. ____________________ is a backbone of a desktop and _______________
is the backbone of a server system.
ANS: PCI bus; System bus