Personal statement
Zhi.LIU
Department of computer science and technology, Tsinghua University
I have a U-turn in Computer Science Department, Tsinghua University, by turning myself a student
admitted by artistic talents (I am a semi professional trumpet player), to a graduate with top20#
ranking. From this process, I understand a lot about myself and more importantly identified my
interests in computer aided design for VLSI.
In Tsinghua, competing with more than 30 first prize winners of various competition in mathematics,
physics or informatics, pressure is everywhere. Fortunately, my math background gave me confidence.
I got 1st in multivariable calculus, top 5 in linear algebra and geometry II, top 5 in probabilistic
mathematics. My performance made me believe, no one is perfect, and I do have my strength.
I knew my weakness, compared with my classmates. I was a bad programmer at the beginning, and
have no computer experience before college. Rather than run away, I choose to face it, even with the
most stupid way. For each programming problem, I just learn the algorithm and then keep debugging
until it works well. The first time I learned quick sort, I spend half a day to let it work. To make my
programming ability stronger, I self-learned data structures one year earlier than scheduled and did all
the programming problems. At last, I got 100 in introduction of computer programming, 99 in Java
design and training, 92 in c++ design and training. Greatly encouraged, I applied the similar aggressive
attitude everywhere, no matter in study or research work . While learning electronics, I gained the
methodology of using Gaussian theorem to solve electrical fields. Beyond calculating capacitance
under the simplest model at the textbook consisting of only ideal conductors, I made an attempt to
compute the capacitance between two cubic conductors by extending the method from 2D case to 3D
case introduced by L.Coz, in which I learned the differentiate equations by myself to solve the Laplace
equation.
At second year, I had taken a Student Research Training course, in which my advisor showed me the
Fastplace algorithm for placement. It's a hierarchical algorithm employing quadratic placement
approach iteratively to spread the overlapped cells, which can be solved efficiently by some analytical
techniques; in the next stage, it borrowed an heuristic greedy algorithm to local refine the bin
utilization; the last stage, the algorithm enumerate the elements in search space to find the optimal
solution for reducing the wire length. Fascinated by the art of optimization algorithm, I raised interest
in the area of VLSI physical design automation.
My interest drove me to learn the book "ALGORITHM FOR VLSI PHYSICAL DESIGN AUTOMATION"
written by Sherwani. From that book, I accumulated more knowledge of placement algorithms.
Min-cut based algorithms take a divide and conquer approach, recursively applying min-cut bisection
to embed the netlist into the layout region. Analytical placement techniques are quite efficient, for
they directly solve mathematical equations using fast computer solver. In analytical methods, forces
based on the current cell distribution are often applied to iteratively reduce cell overlaps. Iterative
algorithms like simulated annealing algorithm and simulated evolution algorithm try to find the
optimal solution by simulating natural processes resemble placement problems. The two algorithms
can both produce optimal or near optimal solutions; however, they are computation intensive. For the
simulating algorithm, it has been proved that it will converge for infinite time, and the chance for the
program to get rid of local optimal solution enable it to find optimal solutions.
As primary designer and programmer, I together with my teammates successfully designed and
implemented a five stage pipeline CPU core on FPGA board which supports THU operating system.
Starting from a blank paper, I draw the whole picture of our CPU by myself, and then together with my
teammates improved the design’s organization. My first version design failed since on our FPGA board,
only one part can be used as RAM which can only be read or write at the same time, and if an
instruction write the result to it, then the instruction pointer must wait to read. This fault aroused my
attention to the specific hardware. And in fact, I thought that in the low lever, an excellent engineer
must take advantage of the hardware.
Besides the course work, I have joined electrical design automation lab to implement a 3D parasitic
capacitance extractor. Presently, it is used widely only as a library-building tool in the industry, and
there is need to improve the efficiency and scalability of the 3D field solver. Our project focused on the
floating random walk based algorithm, since it is suitable to compute the self capacitance in a
complicated net. I implemented the floating random algorithm and found it really time consuming for
its low converging rate O(1/sqrt(N))). For my future work, I propose to make it running on a distributed
system by leveraging parallel computing techniques. The nature that every random walk is
independent sparks my idea and for this property the parallel program may gain a very high accelerate
ratio which can improve the scalability.
My research interest is in the various fields in computer aided design of VLSI. With the increase in
circuit performance and density in deep sub-micrometer designs, interconnect parasitic effects
become increasingly important. Due to growing chip complexity, hierarchical extraction has become
an important topic Thus in my future careers, I plan to find and improve modern 3D field solver to
make it faster without loss of accuracy by hierarchical methods.
I am also interested in placement algorithm. Although many placement algorithms have been
developed, most of them encounter problems when the scale of the circuit grows. Also, typically some
program produces a result with length of wire always 1.3 or more times the optimal solution. Thus,
the improvement should be made to meet the challenge caused by growing size in industry. I plan to
improve conventional algorithms.
Besides, I am also like to do research about the routing problem in VLSI. As the semiconductor
industry enters to the era of deep sub-micrometer. The delay coursed by routing plays a more and
more important role. Since the routing problem is NP complete, there is a critical need to find
approximate algorithms with better intergality gap while keep fast, I would like to devote myself in
finding fast routing algortithms.
As the top three program in VLSI across the America, the electrical and computer engineering in
Purdue trains outstanding industry leaders and engineers with solid knowledge background and
innovative spirit. This is exactly my dreamed future. Besides, as the strong relationship between your
school and the big companies, I'd like to do research works aiming at solving practical problems in this
companies. Within the academic environment in Purdue, I will get more knowledge about VLSI and
strong ability in designing, implementing CAD algorithms and tools, I can also obtain diverse
edification both academically and socially, and this will help me to move to leading place in the
industry. Therefore, Purdue is undoubtedly my first choice. I'd like to pursue a Master degree in ECE as
my next step to realize my career goal.