十二、研究計畫內容：
(一)近五年內主要研究成果說明。
A. 總計畫暨子計劃六主持人近五年內主要研究成果
1.
研發「以二元樹方法設計之特定應用系統單晶片網路」將發表於國際期刊 IEICE Transactions on
Fundamentals of Electronics, Communications and Computer Sciences, 2006 [1]。
2.
研發低功率 ASIP 系統單晶片網路路由器獲 2005 民生電子研討會大會最佳論文獎[18]。
3.
研發即時多媒體應用的多核心可重置式硬體平台獲邀發表於國際期刊 The journal papers of Avtometriya,
Russia, 2005.[2]
4.
研發有效率的小波視訊編碼架構。相關論文發表於 IEICE Transactions on Information and Systems, 2004
[3]。
5.
研發模糊邏輯色彩修正(color correction)之動態管線硬體設計。相關論文發表於 IEEE Trans on C&S, 2003
[6]。
6.
研發非同步電路設計自動化方法。相關論文發表於 IEEE Trans on C&S, 2002 [7]。
7.
發展灰色推論預測移動向量估計法之硬體架構與實現。相關論文發表於 IEEE Trans on C&S, 2002 [8]。
8.
研發動態管線(dynamic pipeline)硬體設計演算法。此項研究榮獲中華民國專利[40]，並獲得美國專利
[43]。研究成果亦已獲得宏碁龍騰博士論文最優獎。
9.
研發 SoC 系統化階層式介面電路設計法則。此項研究榮獲教育部大學院校矽智產 IC 設計 FPGA 組優勝
獎及 Soft IP 組佳作獎，相關論文發表於 VLSI Design/CAD Symposium, 2001[29]。
10. 研發快速有效的語音辨識晶片，此項研究榮獲全國微電腦硬體設計競賽優等獎，相關論文發表於 VLSI
Design/CAD Symposium, 2001[38]。
11. 研發算術編碼之動態管線硬體架構與晶片實現。相關論文發表於 IEEE Trans on C&S, 2001 [9]。
12. 模糊邏輯(fuzzy logic)理論之研究與模糊控制器架構實現。相關論文發表於 IEEE Trans on VLSI, Jan.,
2000 [12]。
13. 發展具高媒體壓縮率之適應性算術編碼演算法與其硬體實現。相關論文發表於 International Journal for
Fuzzy Sets and Systems, 2000 [11], IEEE Trans on Comm., 1999 [17]。
14. 研發固定寬度(fixed-width)平行乘法器，此項研究榮獲中華民國專利[42]，相關論文發表於 IEEE Trans on
C&S, 1999。
15. 研發模糊推論預測移動向量估計法應用於視訊壓縮編碼。此項研究已榮獲中華民國專利[44]。研究成果
亦已獲宏碁龍騰博士論文獎。相關論文發表於 IEEE Trans. on System, Man, and Cybernetics, 2001 [10]。
16. 發展模糊推論預測移動向量估計法之硬體架構與實現。相關論文發表於 IEEE Trans on C&S, 1999 [11]。
17. 研發灰色推論預測移動向量估計法應用於視訊壓縮編碼。相關論文發表於 IEEE Trans on C&S for Video
Technology, 1999 [15]。
18. 研究模糊邏輯色彩修正(color correction)法之演算法與硬體架構。相關論文發表於 IEEE Trans on C&S,
1999 [13]。
19. 研製 FPGA 快速軟硬體共同模擬之驗證系統，達到軟硬體系統單晶片性能及功能共同模擬驗證目的。
20. 研發高效能正反轉換小波硬體架構，適用於最新影像壓縮標準 JPEG2000 之系統晶片中。相關論文發表
於 IEEE International Symposium On Circuits and Systems, 2001[37]。
21. 發展小波視訊壓縮編碼系統與其 SoC 設計。此項研究榮獲旺宏金矽獎第一屆半導體設計與應用大賽優
勝獎與教育部大學院校矽智產 IC 設計 FPGA 組優勝獎，其相關論文亦榮獲中國電機工程學會青年論文
獎第一名。並發表相關論文於 VLSI Design/CAD Symposium, 2001 [35][37], 2000 [39]。
A.1 Journal papers:
1. Yuan-Long Jeang, Jer-Min Jou, Win-Hsien Huang, “A Binary Tree Based Methodology for Designing an
Application Specific Network-on-Chip (ASNOC)”, IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, 2006.
表 C012
第 1 頁，共 9頁
Jer Min Jou, Chien-Ming Sun, Hong-Yi Su, Shih-Hsun Hsu and Ming-Chao Lee “Run-Time Multi-tile
Reconfigurable Hardware Platform Design for Multimedia Applications,” The invited journal papers of
Avtometriya, Russia, 2005.
3. Y.-H. Shiau, J.M. Jou, and C.-C. Liu, “Efficient Architectures for the Biothogonal Wavelet Transform by
Filter Bank and Lifting Scheme,” IEICE Transactions on Information and Systems, July, 2004.
4. Y.-H. Shiau and J.M. Jou, "A High-Performance Tree-Block Pipelining Architecture for Separable 2-D
Inverse Discrete Wavelet Transform," IEICE Transactions on Information and Systems, pp. 1966-1975,
2003.
5. Yeu-Horng Shiau, J.M. Jou, and Chin-Chi Liu, "Efficient Architectures for the Biorthogonal Wavelet
Transform by Filter Bank and Lifting Scheme," accepted by IEICE Transactions on Information and
Systems, December, 2003.
6. J.M. Jou, S.R. Kuang, and Y.-H. Shiau "Dynamic Pipelined Architecture for Fuzzy Color Correction," to
be published on IEEE Trans. on VLSI, 2003.
7. R.-D. Chen and J.M. Jou, "STG-level Decomposition and Resynthesis of Speed-independent Circuits,"
IEEE Transactions on Circuits & Systems Part I, pp.1151-1163, Dec., 2002, USA.
8. J.M. Jou, Y.-H. Shiau, P.-Y. Chen, and S.-R. Kuang, "A Low Cost Gray Prediction Search Chip for Motion
Estimation," IEEE Transactions on Circuits & Systems Part I, pp.1151-1163, 2002, USA.
9. S.-R. Kuang, J. M. Jou, R.-D. Chen, Y.-H. Shiau, "Dynamic Pipeline Design of an Adaptive Binary Arithmetic
Coder," IEEE Trans. on Circuits & Systems Part II, pp.813-825, Sept. 2001, USA.
10. J.M. Jou, and P.-Y. Chen, "An Efficient Block-Matching Algorithm Based on Fuzzy Reasoning," IEEE Trans.
on System, Man, and Cybernetics, Vol. 31, no. 2, pp.253-259, April, 2001, USA.
11. J.M. Jou and P.-Y. Chen "Adaptive Arithmetic Coding Using Fuzzy Reasoning and Gray Theory,"
International Journal for Fuzzy Sets and Systems, vol.114, no.2, pp.239-254, 2000.
12. J.M. Jou, P.-Y. Chen and S.-F. Yang, "An Adaptive Fuzzy Logic Controller: Its VLSI Architecture and
Applications," IEEE Trans. on VLSI, vol. 8, no. 1, pp.52-60, Jan. 2000, USA.
13. J.M. Jou, S.-R. Kuang and R. D. Chen "A New Efficient Fuzzy Algorithm for Color Correction," IEEE Trans.
on Circuits & Systems Part I, vol. 46, no. 6, pp.773~775, 1999.
14. P.-Y. Chen, and J.M. Jou "A Fast-Search Motion Estimation Method and its VLSI Architecture," IEEE Trans.
On Circuits and Systems Part II, vol. 46, no. 9, pp.1233-1240, 1999.
15. J.M. Jou, P.-Y. Chen, and J.-M. Sun "The Gray Prediction Search Algorithm for Block Motion Estimation,"
IEEE Transactions on Circuits & Systems for Video Technology, vol.9, no.6, pp.843-848, 1999, USA.
16. J.M. Jou, S.-R. Kuang, and R. D. Chen, “Design of Low-Error Fixed-Width Multipliers for DSP
Applications,” IEEE Transactions on Circuits & Systems Part II, vol.46, no.6, pp.836-842, June 1999.
17. J.M. Jou and P.-Y. Chen "A Fast and Efficient lossless Data Compression Method," IEEE Trans. On
Communications, vol.47, no.9, pp.1278-1283, 1999.
A.2 Conference papers:
18. Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee, Chien-Ming Sun and Hung-Wei Yang, “Design of a New
Pipelined Router for NoC”, 2005 Workshop on Consumer Electronics and Signal Processing, November, 17 –
18, 2005.
19. Zi-Lun Wang, Jer-Min Jou, Shih-Hsun Hsu , Ming-Chao Lee, Chien-Ming Sun and Hung-Wei Yang,
“Design of a Low Power ASIP for Network-on-Chip Routing”, 2005 Workshop on Consumer Electronics and
Signal Processing, November, 17 – 18, 2005.
20. Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee and Chien-Ming Sun, “Design of a New Pipelined Router for
NoC”, 2005 National Computer Symposium, December, 15 – 16, 2005.
21. Hao-I Yang, Jer-Min Jou, Chin-Ming Sun, Shih-Hsun Hsu, Ming-Chao Lee, “Design of A Run-time
Reconfigurable Superscalar System Platform For NoC” Proceedings of the 2005 VLSI Design/CAD
Symposium, 2005.
22. Jer Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Ming-Chao Lee, Ye-Xuan Yan, Hong-Yi Su, and Haoi Yang,
“A Multi-tile Reconfigurable Platform Design for DSP Applications,” ACIT-SIP 2005, Novosibirsk, Russia,
June 20-24, 2005.
2.
表 C012
第 2 頁，共 9頁
23. Shih-Lun Chen, Jer-Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Haoi Yang, Hong-Yi Su,"Reconfigurable
Processor Core Design for Network-on-a-Chip," International Computer Symposium, 2004.
24. Chien-Ming Sun, Jer Min Jou, Hong-Yi Su, Ye-Xuan Yan, and Haoi Yang, "Design of a Multi-tile
Reconfigurable Platform for DSP Applications, " Proceedings of Workshop on Consumer Electronics, 2004.
25. Shih-Hsun Hsu, Jer-Min Jou, and Yuan-Chin Wu, "New Routing Algorithms and Router Architecture Design
for NoC," Proceedings of the 2004 VLSI Design/CAD Symposium, 2004.
26. Ye-Xuan Yan, Jer-Min Jou, Yuan-Chin Wu, and Shih-Hsun Hsu, "A Field Programmable DSP Platform
Design," Proceedings of the 2004 VLSI Design/CAD Symposium, 2004.
27. Jer-Min Jou, "Reconfigurable SoC Architectures," Proceedings of the 2003 VLSI Design/CAD
Symposium, 2003.
28. J.M. Jou et. al., "System Design of NoC", Proceedings of the 2003 MiddleEast Circuits & Systems
Conference, 2003.
29. Jun-Sheng Zheng, Jer-Min Jou and Yeu-Horng Shiau, "Hierarchical Interface Design Methodology : Using
Real -Time MPEG 1Audio layer3 codec as a case," Proceedings of the 2002 VLSI Design/CAD Symposium,
pp.301-304, 2002.
30. Tzeng-Yi Lin, Jer-Min Jou, Shiann-Rong Kuang and Yeu-Horng Shiau, "Hardware Implementation of
Network Layer Protocol Transform Between IP and ATM Applied in Edge Router," Proceedings of the 2002
VLSI Design/CAD Symposium, pp.322-325, 2002.
31. Yu-Chia Chen, Yeu-Horng Shiau, Shiann-Rong Kuang, and Jer-Min Jou, "Design of An Integrated MAC IP
for IEEE 1394 and Ethernet," Proceedings of the 2002 VLSI Design/CAD Symposium, pp.326-329, 2002.
32. Kuang-Li Wu, Jer-Min Jou, and Yeu-Horng Shiau, "Bus Wrapper Design Methodology in the SoC,"
Proceedings of the 2002 VLSI Design/CAD Symposium, pp. 524-527, 2002.
33. 周哲民, 蕭宇宏, 張博皓, 陳昱嘉, "家用網路影像傳輸 IP 及單晶片系統之設計與研製," Proceedings of
Workshop on Consumer Electronics, 2002.
34. K.-M. Wu and J.M. Jou, "A Hierarchical Interface Design Methodology and Models for SoC IP Integration,"
The 12th VLSI Design/CAD Symposium, pp. B2-8, 2001.
35. Y.-H. Shiau, P.-H. Chang, S.-R. Kuang, and J.-M. Jou, "Hardware Software Co-design and Implementation of
Wavelet-based Video Compression System," The 12th VLSI Design/CAD Symposium, pp. B2-4, 2001.
36. Y.-H. Shiau, Y.-T. Hu, S.-R. Kuang, Jer-Min Jou, "System Design of JPEG2000 Still Image Compression
Coder," The 12th VLSI Design/CAD Symposium, pp. B2-2, 2001.
37. J. M. Jou, Y.-H. Shiau, and C.-C. Liu, "Efficient VLSI Architectures for the Biorthogonal Wavelet Transform
by Filter Bank and Lifting Scheme," IEEE International Symposium On Circuits and Systems, pp. 529-533,
2001.
38. W.-S. Huang, J.M. Jou, Y.-H. Shiau, "Efficient Modular Hardware Design For Continuous Speech
Recognition," The 12th VLSI Design/CAD Symposium, pp. C3-1, 2001.
39. J.M. Jou, Y.-H. Shiau, and Y.-S. Hsieh, "The Chip Implementation and HW/SW Co-simulation of A
DWT-based Coding System," The 11th VLSI Design/CAD Symposium, pp. 45-48, 2000.
40. C.-J. Huang, Y.-H. Shiau, and J. M. Jou, "A High Speed and Area-Efficient Survivor Path Architecture for
HMM Based Speech Recognition," The 11th VLSI Design/CAD Symposium, pp. 49-52, 2000.
A.3 智慧財產權(專利)及應用成果
41. 周哲民 et. al. "高時效動態管線化電路設計法",中華民國專利, no.137795, 2001.
42. 周哲民 et. al. "低誤差固定寬度(Fixed-width)二補數平行乘法器", 中華民國專利, no.117044, 2000。
43. 周哲民 et. al. "高時效動態管線化電路設計法", 美國專利 2002.
44. 周哲民 et. al. "高效能影像移動向量之模糊邏輯估計法", 中華民國專利, 2003.
B. 子計劃一主持人近五年內主要研究工作：
B.1 榮譽
1.
福特汽車公司,亨利福特技術奬 (1999)。
B.2 專利
表 C012
第 3 頁，共 9頁
2.
V.Tran,S-F Lei, K.Hsueh and F.Charette , 2001 "Method and Apparatus for Identifying sound in a Composite
sound signal," USA Patent No. 6182018.
C. 子計劃二主持人近五年內主要研究成果：
包含七篇論文發表於國際性期刊中、五篇論文發表於國際性或全國性會議中、以及取得二項
中華民國專利，詳列如下：
C.1 Journal papers
[1] Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, and Ren-Der Chen, “Design of A Dynamic Pipelined
Architecture for Fuzzy Color Correction”, IEEE Transactions on VLSI Systems, Vol. 10, No. 6, pp. 924-929,
December 2002. (SCI Expanded, EI)
[2] Jer-Min Jou, Yeu-Horng Shiau, Pei-Yin Chen, and Shiann-Rong Kuang, “A Low Cost Gray Prediction Search
Chip for Motion Estimation”, IEEE Transactions on Circuits & Systems Part I, Vol. 49, No. 7, pp. 928-938, July
2002. (SCI)
[3] Shiann-Rong Kuang, Jer-Min Jou, Ren-Der Chen, and Yeu-Horng Shiau, “Dynamic Pipeline Design of an
Adaptive Binary Arithmetic Coder,” IEEE Transactions on Circuits & Systems Part II, Vol. 48, No. 9, pp.
813-825, September 2001. (SCI)
[4] Jer-Min Jou, Shiann-Rong Kuang, and Ren-Der Chen, “A New Efficient Fuzzy Algorithm for Color Correction,”
IEEE Transactions on Circuits & Systems Part I, Vol. 46, No. 6, pp. 773-775, June 1999. (SCI)
[5] Jer-Min Jou, Shiann-Rong Kuang, and Ren-Der Chen, “Design of Low-Error Fixed-Width Multipliers for DSP
Applications,” IEEE Transactions on Circuits & Systems Part II, Vol. 46,No. 6, pp. 836-842, June 1999. (SCI)
[6] Shiann-Rong Kuang, Jer-Min Jou, and Yuh-Lin Chen, “The Design of an Adaptive On-Line Binary Arithmetic
Coding Chip,” IEEE Transactions on Circuits & Systems Part I, Vol. 45, No. 7, pp. 693-706, July 1998. (SCI)
C.2 Conference papers
[1] Shiann-Rong Kuang, Chin-Yang Chen and Ren-Zheng Liao, “Partitioning and Pipelined Scheduling of
Embedded System Using Integer Linear Programming,” The 11th International Conference on Parallel and
Distributed Systems, Vol. 2, pp. 37-41, July 2005.
[2] Jiun-Ping Wang and Shiann-Rong Kuang, “Design of Parallelized Controllers for High-performance
Controller-Datapath System,” The 9th IEEE International Workshop on Cellular Neural Networks and Their
Applications, pp. 257-260, May 2005.
[3] Shiann-Rong Kuang, Kuo-Chin Huang, Ju-Kai Teng, and Jin-Lin Liu, “System Architecture Synthesis of
Embedded System for Multimedia Applications,” International Computer Symposium, 2004.
[4] Tso-Bing Juang, Shen-Fu Hsiao, Shiann-Rong Kuang, and Ming-Yu Tsai, “Low-Error Carry-Free Fixed-Width
Multipliers and Their Application to DCT/IDCT,” IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 1,
pp. 457-460, Dec. 2004.
[5] Shiann-Rong Kuang, Shu-You Liu, Jin-Lin Liu, and Jiun-Ping Wang, “Implementation of Video Encoding
System with Hardware/Software Codesign,” Workshop on Consumer Electronics and Signal Processing, 2004.
[6] Shiann-Rong Kuang, Shao-Hean Hsu, Shu-You Liu, and Kuo-Chin Huang, "Low-cost Two's Complement
Multipliers Using Signed Binary Digits for High-speed Digital Systems," National Computer Symposium, pp.
1879-1885, 2003.
[7] Shiann-Rong Kuang, Yi-Jun Wang, and Pei-Yin Chen, "Design of Low-Error Truncated Redundant Binary
Signed-Digit Multipliers for DSP Applications," The 16th European Conference on Circuits Theory and Design,
2003.
[8] Pei-Yin Chen, Shiann-Rong Kuang, and Chia-Hsien Cheng, "VLSI Architecture for Lifting Discrete Wavelet
Transform," The 13th VLSI Design/CAD Symposium, pp. 359-362, 2002.
[9] Jer-Min Jou, Shiann-Rong Kuang, and Kuang-Ming Wu, "A Hierarchical Interface Design Methodology and
Models for SoC IP Integration," IEEE International Symposium on Circuits and Systems, Vol. II, pp. 360-363,
2002.
[10] Yeu-Horng Shiau, Yu-Tzung Hu, Shiann-Rong Kuang, and Jer-Min Jou, “System Design of JPEG2000 Still
Image Compression Coder,” The 12th VLSI Design/CAD Symposium, 2001.
表 C012
第 4 頁，共 9頁
[11] Jer-Min Jou, Shiann-Rong Kuang, and Yeu-Horng Shiau, “A New Pipelined Architecture for Fuzzy Color
Correction,” Asia and South Pacific Design Automation Conference, pp. 209-212, 1999.
C.3 專利
1. 鄺獻榮 et. al. , ”低誤差固定寬度（fixed-width）二補數平行乘法器”, 中華民國專利第 117044 號，專利
期間 89/7/1～107/8/4。
2. 鄺獻榮 et. al. , ”一種使用於高時效電路設計之動態管線化方法”, 中華民國專利第 137795 號。
D. 子計劃三共同主持人近五年內主要研究成果
D.1 Journals papers：
1 Yuan-Long Jeang, Gwo-Jia Jong, Cheng-Hong Yang “Functional Mapping from Assembly to
Verilog, ”Journal of National Kaohsiung University of Applied Sciences, Dec., 2000.
2 Gwo-Jia Jong, Yuan-Long Jeang, Te-Jen Su,”The Simulation of Cochannel FM Interference Using the
Matlab,” Journal of National Kaohsiung University of Applied Sciences, Dec 2000.
3 Cheng-Hong Yang, Ching-Hsing Luo, Yuan-Long Jeang , Gwo-Jia Jon “A Novel Approach to Adaptive
Morse Code Recognition for Disabled Persons” Mathematics and Computers in Simulation, 26 May 2000.
4 Li-Cheng Jin, Liang-Bi Chen, Pin-Tsen Lin, Yuan-Long Jeang, Cheng-Hong Yang, and Bin-Yih Liao, “ A
Fuzzy-based Personality Bid Web System for Used Products”, Journal of Commercial Modernization, Dec.
2001.
5 Yuan-Long Jeang, Cheng-Hong Yang, Gwo-Jia Jong, Tsong-Yi Chen, and Nan-Long Tsai, “A Synthesizer
for Infinite Nested Loops Under Timing/Cost Constraints”, Journal of National Kaohsiung University of
Applied Sciences, Dec 2001.
6 Pei-Ju Chao, Gwo-Jia Jong, Yuan-Long Jeang, Te-Jen Su, “The Noise Cancellation System of the
Amplitude-Lock Loop with Cochannel FM Interface”, Journal of National Kaohsiung University of Applied
Sciences, Dec 2002.
7 Yuan-Long Jeang, Gwo-Jia Jong, Cheng-Hong Yang, “Load-then-Go II: An Intelligent Soft IP Generator
for Micro-processor Core”, Journal of National Kaohsiung University of Applied Sciences, Dec 2002.
8 Yuan-Long Jeang, Jer-Min Jou, Win-Hsien Huang, “A Binary Tree Based Methodology for Designing an
Application Specific Network-on-Chip (ASNOC)”, to be published on Dec. in IEICE Transactions on
Fundamentals of Electronics, Communications and Computer Sciences.
D.2 Conference papers:
1. Yuan-Long Jeang, Chen-Pung Liu, “High Performance and Low Cost Greater-by-N and Different-by-N
Comparators for N is Fixed or Reprogrammable”, Proceedings of the 16th VLSI Design/CAD Symposium,
August, 2005.
2. Yuan-Long Jeang, Jen-Wei Hsieh, Yong-Zong Lin, “An Efficient Code Compression/ Decompression
System Based on Field Partitioning”, Proceedings of The 20th Commemorative International technical
Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005), July 4-7, 2005, Jeju,
Korea.
3. Yuan-Long Jeang, Je-Jia Liu, “A High Performance and Low Cost Real-time Address Tracer for
Embedded Microprocessors”, Proceedings of the 16th VLSI Design/CAD Symposium, Aug. 2005.
4. Yuan-Long
Jeang,
Jen-Wei
Hsieh,
Yong-Zong
Lin,
“An
Efficient
Instruction
Compression/Decompression System Based on Field Partitioning”, 2005 IEEE International Midwest
Symposium on Circuits and Systems, Aug. 7-10, 2005.
5. Hung-Yu Wang, Yuan-Long Jeang, I-Pin Lin, Chao-Hsiung Owe, Chun-Yueh Hwang, “Versatile
Multifunction Universal Voltage-Mode Filter”, 2005 IEEE International Midwest Symposium on Circuits
and Systems, Aug. 7-10, 2005.
6. Yuan-Long Jeang, Kai-Jyun liang, Jiun-Haw Tu, Jain-Zhou Hwang, Ping-Show Cheng, “An Embedded
Wavelet Image Coding Algorithm and Its Hardware Implementation Based on Zero-Block and Array
(EZBA)”, 2005 IEEE International Midwest Symposium on Circuits and Systems, Aug. 7-10, 2005.
7. Yuan-Long Jeang, Je-Jia Liu, “A High Performance Real-time Address Tracing Compressor for
Embedded Microprocessors”, 2005 IEEE International Midwest Symposium on Circuits and Systems,
Aug. 7-10, 2005.
8. Yuan-Long Jeang, Liang-Bi Chen, Jiun-Hau Tu, In-Jer Huang, “An Efficient and Low power Systolic
Squarer”, 2005 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT),
Apr. 27-29, 2005.
9. I-Pin Lin, Hung-Yu Wang, Chao-Hsiung Owe and Yuan-Long Jeang, “A Straightforward Proof of
Network Transformations”, 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004),
Dec. 2004, Tainan, Taiwan
10. Yuan-Long Jeang, Win-Hsien Huang, Wei-Feng Fang, Jain-Zhou Huang, Nan-Long Tsai, “An
表 C012
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11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
表 C012
Application Specific Network-on-Chip (ASNOC) Design with Binary Tree Architecture”, The 12th
Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2004), Oct.,
2004, Japan.
Yuan-Long Jeang, Win-Hsien Huang, Wei-Feng Fang, “A Binary Tree Architecture for Application
Specific Network on Chip (ASNOC) Design”, 2004 IEEE Asia-Pacific Conference on Circuits and
Systems (APCCAS 2004).
Yuan-Long Jeang, Win-Hsien Huang, Wei-Feng Fang, Jain-Zhou Huang, Nan-Long Tsai, “An
Application Specific Network-on-Chip Design Based on Binary Tree Architecture”, The 15th VLSI
Design/CAD Symposium, August 2004.
Yuan-Long Jeang, Gwo-Yang Wu, Liang-Bi Chen, “A Microcontroller IP Generator for SOC Platform”,
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC2004), Aug. 2004.
歐朝雄、林逸斌、蔣元隆、王鴻猷，”應用在光感測系統前置放大器之 CCII 放大電路”, 2004 年中華
民國自動控制研討會，Mar.2004, p312~p317..
Yuan-Long Jeang, Liang-Bi Chen, “A Generator for Retargetable/Reconfigurable Embedded In-Circuit
Emulator for SOC Testing/Debugging”, 2003 International Conference on Informatics, Cybernetics, and
Systems, Kaohsiung, Taiwan, Dec.2003
Yuan-Long Jeang, Liang-Bi Chen, Yi-Ting Chou, Hsin-Chia Su, “An Embedded In-Circuit Emulator
Generator for SOC Platform”, 2003 IEEE International Conference on Field-Programmable Technology,
Tokyo, Dec. 2003.
Yuan-Long Jeang, Liang-Bi Chen, Chia-Pin Huang, Yu-Hsiang Hsu, Ming-Yu Yeh, and Kai-Ming Yang,
“Design of FPGA-based Adaptive Remote Calibration Control System”, IEEE International Conference
on Field-Programmable Technology, Tokyo, Dec. 2003.
Yuan-Long Jeang, Liang-Bi Chen, Yi-Ting Chou, Hsin-Chia Su, Gwo-Yang Wu, and Ye-Pin Lin, “An
Embedded In-Circuit Emulator Generator for SOC Design Platform”, Proceedings of The 14th VLSI
Design/CAD Symposium, August 2003.
Yuan-Long Jeang, Liang-Bi Chen, and Gwo-Yang Wu, “Design of the Internet-based Remote Control
Servo System Using FPGA”, Proceedings of the Conference on Automation Control, Taiwan, pp.167-172,
2003.
Liang-Bi Chen, Gwo -Yang Wu, Yuan-Long Jeang, Gwo-Jia Jong, “An Adaptive PCM Codec Module
for Nondeterministic Working Environment”, Proceedings of the 2002 National Symposium on
Telecommunications, Taiwan, Vol.2, pp92~97, 2002.
陳良弼、吳國陽、蔣元隆、鐘國家，”應用於非定型工作環境之可調適性碼調變編解碼選擇模組”, 2002
全國電信研討會。
Liang-Bi Chen, Gwo -Yang Wu, Yuan-Long Jeang, Kuei-Iou Kang, “Design of Video with Wireless
DSP in Registration System at a Hospital”, Proceedings of the 2002 Conference on Biomedical
Engineering and Technology, Taiwan, pp. D3.77-D3.78, 2002.
陳良弼、蔣元隆、吳國陽、康饋佑，”無線 DSP 子母影像電視應用在看診掛號系統之研究”, 2002 生
物醫學工程科技研討會/國科會醫工學門成果發表會。
Gwo-Yang Wu, Liang-Bi Chen, Yuan-Long Jeang, Gwo-Jia Jong, “An Optimal PCM Codec Soft IP
Generator and its Application”, 2002 IEEE International Conference on Field-Programmable Technology,
Dec. 2002.
Liang-Bi Chen, Gwo-Yang Wu, Yuan-Long Jeang, Gwo-Jia Jong, “An Optimal PCM Codec”, The 13th
VLSI Design/CAD Symposium, August 2002.
Yuan-Long Jeang, Cheng-Hong Yang, Gwo-Jia Jong, Tsong-I Chen, Nan-Long Tsai “A Synthesizer for
C Program Containing Infinite Nested Loops With Conditional Branches under Timing/Cost Constraints”
The 12th VLSI Design/CAD Symposium, August 2001.
Cheng-Hong Yang, Cheng-Huei Yang, Yuan-Long Jeang, Gwo-Jia Jong, and Tsong-Yi Chen “Apply
Neural Networks To Morse Code Recognition” Proc. of the 2000 Informational Computer Symposium,
Chiayi, 21-26, 2001.
Cheng-Hong Yang, Cheng-Huei Yang, Yuan-Long Jeang, Gwo-Jia Jong, and Tsong-Yi Chen, ”Apply
Neural Networks To Morse Code Recognition” Proc of the 2000 International Computer Symposium,
2000.
Gwo-Jia Jong, A.M. Pettigrew, Te-Jen Su, Yuan-Long Jeang, ”The Simulation of Cochannel FM
Interference Using The Amplitude-locked Loop,” Proceedings of the Fifth Symposium on Computer &
Communication Technology, 2000.
Yuan-Long Jeang, Gwo-Jia Jong, Cheng-Hong Yang, Gwo-Yang Wu, and Liang-Bi
Chen.”Load-then-Go: A Retargetable Soft-IP Generator for Microprocessors.” Proceedings of the 11 th
VLSI Design/CAD Symposium, Aug. 2000.
第 6 頁，共 9頁
E. 子計劃四共同主持人近五年內主要研究成果
E.1 專利
1. Wen-Yuan Chen and Chih-Hung Kuo, “Apparatus and method for echo cancellation,” US patent
US5970154. Issued Date Oct. 19, 1999.
2. 郭致宏，陳文源, “應用聽覺效應之回音消除方法及裝置," 中華民國專利, 00338867, 1998/08~2017/09
E.2 papers
[1] Chih-Hung Kuo, Meiyin Shen and C.-C. Jay Kuo, “Fast inter-prediction mode decision and motion search
for H.264,”Proc. IEEE International Conference on Multimedia & Expo 2004, June 2004, Taipei, Taiwan.
[2] Chih-Hung Kuo, Meiyin Shen and C.-C. Jay Kuo, “An enhanced fast variable block-size motion estimation
scheme for H.264 ,”Proc. SPIE Visual Communications and Image Processing 2004, January, 2004, in Proc.
SPIE Vol 5308, pp. 440-451.
[3]Chih-Hung Kuo, Meiyin Shen and C.-C. Jay Kuo, “Fast variable-block-size motion compensation algorithm
forH.264 video coding,” Proc. SPIE ITCom 2003, September 2003, Orlando, Florida, in Proc. SPIE Vol. 5241.
(EI)
[4]Chih-Hung Kuo and C. -C. Jay Kuo, “ Embedded space-time coding for wireless broadcast with
heterogeneous receivers,”Proc. IEEE Global Telecommunications Conference, 2002, Taipei, Taiwan, Vol 2 , pp
1749 –1753. (EI)
[5]Chih-Hung Kuo and C.-C. Jay Kuo, “Embedded differential space-time coding for wireless broadcast,”
Proc. SPIE ITCom 2002, Nov 2002, in Proc. SPIE Vol 4869, pp 85-96. (EI)
[6]Chih-Hung Kuo, Chang-Su Kim and C.-C. Jay Kuo, “Robust video transmission over wideband wireless
channel using space-time coded OFDM systems,” Proc. IEEE Wireless Communications and Networking
Conference 2002, Mar 2002 , Vol 2, pp 931 –936.
[7]Chih-Hung Kuo, Chang-Su Kim, Robert Ku, and C.-C. Jay Kuo, “Embedded space-time coding for wireless
broadcast,”Proc. SPIE Visual Communications and Image Procssing 2002, January 20-25, 2002, San Jose, CA,
Vol 4671 II, pp 967-977. (EI)
[8]Chih-Hung Kuo, Chang-Su Kim, and C.-C. Jay Kuo, “Layered video transmission over space-time-coded
systems,”Proc. Conference on Applications of Digital Image Processing XXXV, SPIE's 46th Annual Meeting,
SanDiego, CA, July 29-August 3, 2001 in Proc SPIE Vol 4472, pp 482-491. (EI)
F. 子計劃五主持人近五年重要研究成果列舉如下：
F.1 Journals papers:
1. Pei-Yin Chen, “VLSI implementation for 1-D multi-level lifting-based wavelet transform,” IEEE Trans. on
Computer, vol. 53, no. 4, pp. 386-398, April 2004 (SCI).
2. Pei-Yin Chen, “An efficient prediction algorithm for image vector quantization,” IEEE Trans. on Systems,
Man, and Cybernetics, Part B, vol. 34, no. 1, pp. 740-746, Feb. 2004 (SCI).
3. Pei-Yin Chen, “VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform,” IEICE
Trans. on Fundamentals, vol E87-A, no. 1, pp. 275-279, Jan. 2004 (SCI).
4. Pei-Yin Chen, and Ren-Der Chen, “An index coding algorithm for image vector quantization,”IEEE Trans.
on Consumer Electronics, vol. 49, no. 4, pp. 1513-1520, Nov. 2003 (SCI).
5. Pei-Yin Chen, “VLSI implementation for fuzzy membership-function generator,” IEICE Trans. on
Information and Systems, vol. E86-D, no. 6, pp. 1122-1125, June 2003 (SCI).
6. Pei-Yin Chen, “A fuzzy search block-matching chip for motion estimation,” Integration, the VLSI Journal,
vol. 32, pp. 133-147, Nov. 2002 (SCI).
7. Pei-Yin Chen, “VLSI implementation of lifting discrete wavelet transform using the 5/3 filter,” IEICE, pp.
1893-1897, Dec. 2002 (SCI).
8. Pei-Yin Chen, Shung-Chih Chen, Chi-Yung Shao, and Wen-Chu Chen, “An Efficient VLC Coding
Algorithm and Its VLSI Architecture,” Journal of Southern Taiwan University of Technology, No. 27, pp.
21-38, Dec., 2002.
9. Jer Min Jou, Yeu-Horng Shiau and Pei-Yin Chen, Shiann-Rong Kuang, “A low cost gray prediction search
chip for motion estimation,” IEEE Transactions on Circuits & Systems-Part I, vol. 49, no. 7, pp. 928-938,
July 2002 (SCI).
10. Jau-Ling Chen and Pei-Yin Chen, “An efficient gray search algorithm for the estimation of motion vectors,”
IEEE Trans. on Systems, Man, and Cybernetics, Part C, vol. 31, no. 2, pp. 242-248, May 2001 (SCI).
11. Pei-Yin Chen and Jer Min Jou, “An efficient blocking-matching algorithm based on fuzzy reasoning,” IEEE
Trans. on Systems, Man, and Cybernetics, Part B, vol. 31, no. 2, pp. 253-258, April 2001 (SCI).
12. Yun-Teng Roan and Pei-Yin Chen, “A fuzzy search algorithm for the estimation of motion vectors,” IEEE
Trans. on Broadcasting, vol. 46, pp. 121-127, 2000 (SCI).
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13. Pei-Yin Chen and Jer Min Jou, “Adaptive Arithmetic Coding Using Fuzzy Reasoning and Gray Prediction,”
Fuzzy Sets and Systems, vol. 114, no. 2, pp. 239-254, 2000 (SCI).
14. Jer Min Jou, Pei-Yin Chen and Sheng-Fu Yang, “An Adaptive Fuzzy Logic Controller: Its VLSI
Architecture and Applications”, IEEE Trans. on VLSI Systems, vol. 8, no. 1, pp. 52-60, 2000 (SCI).
15. Pei-Yin Chen and Jer Min Jou, “A Fast-Search Motion Estimation Method and Its VLSI Architecture,” IEEE
Trans. on Circuits & Systems-Part II, vol. 46, no. 9, pp. 1233-1240, 1999 (SCI).
16. Jer Min Jou, Pei-Yin Chen and Jian-Ming Sun, “The Grey Prediction Search Algorithm for Block Motion
Estimation,” IEEE Trans. on Circuits and System for Video Technology, vol. 9, no. 6, pp. 843-848, 1999
(SCI).
17. Jer Min Jou and Pei-Yin Chen, “A Fast and Efficient Lossless Data Compression Method,” IEEE Trans. on
Communications, vol. 47, pp. 1278-1283, 1999 (SCI).
F.2 Conference papers:
18. Shian-De Chen, Pei-Yin Chen, Yung-Ming Wang “A Flexible Genetic Algorithm Chip,” National Computer
Symposium, Taiwan pp. 253-257, 2003.
19. Pei-Yin Chen, Shung-Chih Chen and Yung-Ming Wang “A Flexible VLSI of Genetic Algorithm,” Workshop
on Consumer Electronics, Taiwan pp. 50-53, 2003.
20. Wen-Ta Huang, Yi-Heng Chang and Pei-Yin Chen, “VLSI Architecture of 2-D 3-level Lifting-Based
Discrete Wavelet Transform,” The Proceedings of CECA2003, Penghu, Taiwan pp. 287-290, 2003.
21. Shiann-Rong Kuang, Yi-Jun Wang and Pei-Yin Chen, “Area Efficient Multipliers Based on Redundant
Binary Signed-Digit Booth Encoding for Image Compression,” The Proceedings of CECA2003, Penghu,
Taiwan pp. 314-319, 2003.
22. 陳文鉅,雷朝聖, 陳培殷, “高效率變動長度碼之編解碼硬體實現,” The Proceedings of CECA2003,
Penghu, Taiwan pp. 320-325, 2003.
23. Chao-Tang Yu, Pei-Yin Chen and Jia-Kuan Huang, “A Fast Search Algorithm for Image Vector Quantization
Using Sum Pyramid of Codewords,” The Proceedings of CECA2003, Penghu, Taiwan pp. 326-331, 2003.
24. 蕭裕益, 陳培殷, “適應性誤差訊號編解碼演算法及其 VLSI 硬體設計,” The Proceedings of CECA2003,
Penghu, Taiwan pp. 332-336, 2003.
25. Pei-Yin Chen, Shiann-Rong Kuang and Chia-Hsien Cheng, “VLSI architecture for lifting discrete wavelet
transform,” The 2002 VLSI Design/CAD Symposium, Taiwan, pp. 359-362, 2002.
26. Pei-Yin Chen, Shung-Chih Chen and Che-Yen Hu and, “A lossless vector-quantized index coding method
and its VLSI architecture for 2D still image,” The 2002 VLSI Design/CAD Symposium, Taiwan, pp. 472-475,
2002.
27. Yi-Heng Chang and Pei-Yin Chen, “VLSI architecture of 2-D 3-level lifting-based discrete wavelet
transform,” Workshop on Consumer Electronics, Taiwan, pp. 47-51, 2002.
28. Chih-Yu Ke and Pei-Yin Chen, “A novel genetic algorithm processor,” Workshop on Consumer Electronics,
Taiwan, pp. 55-58, 2002.
29. Ming-He Wang and Pei-Yin Chen, “Two VLSI architectures for fuzzy membership-function generators,”
Workshop on Consumer Electronics, Taiwan, pp. 233-237, 2002.
30. Chia-Hsien Cheng and Pei-Yin Chen, “Design and implementation of lifting discrete wavelet transform,”
International Conference on Fundamentals of Electronics Communications and Computer Sciences, Japan,
pp. 6.1-6.4, 2002.
31. Pei-Yin Chen and C.-Y. Hu, “An efficient on-line lossless vector-quantized index coder,” International
Conference on Fundamentals of Electronics Communications and Computer Sciences, Japan, pp.
20.27-20.30, 2002.
32. Jau-Ling Chen and Pei-Yin Chen, “A fast-search motion estimation method and its VLSI architecture,” Proc.
of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 1, pp. 164-167, 2000.
33. Jau-Ling Chen and Pei-Yin Chen, “A new search algorithm for block motion estimation,” IEEE
International Conference on Multimedia and Expo (ICME2000), pp. 979-982, 2000.
34. Y.-T. Roan and Pei-Yin Chen, “A fast-search motion estimation method,” IEEE International Conference on
Systems, Man, and Cybernetics, pp. 1568-1573, 2000.
35. Pei-Yin Chen and Shung-Chih Chen, “A New Search Algorithm for Block Motion Estimation,” 15th
Technological and Vocational Education Conference of R. O. C, pp. 155-160, 2000.
36. Shung-Chih Chen and Pei-Yin Chen, “Heuristic Block Distortion Measure in Block Motion Estimation,”
15th Technological and Vocational Education Conference of R. O. C, pp. 209-216, 2000.
37. Jer Min Jou, Pei-Yin Chen and Yeu-Horng Shiau and Ming-Shiang Liang, “A Scalable Pipelined
Architecture for Separable 2-D Discrete Wavelet Transform,” Asia and South Pacific Design Automation
Conference, pp. 205-208, 1999.
38. Jer Min Jou, Pei-Yin Chen and Jian-Ming Sun, “A Grey Prediction Motion Estimator for Digital Image
Processing,” IEEE International Conference on Electronics, Circuits and Systems, pp. 701-704, 1999.
39. Pei-Yin Chen, Jer Min Jou and Shung-Chih Chen, “An Efficient Search Algorithm for Block-Matching
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Motion Estimation,” 14th Technological and Vocational Education Conference of R. O. C, pp. 209-217,
1999.
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