Asymmetrical IV Characteristics and Junction Regions in Implantation Defined Surround Gate Vertical MOSFETs L. Tan1, M. M. A. Hakim2, T. Uchino2, W. Redman-White2, P Ashburn2 and S. Hall1 1 University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK 2 University of Southampton, Southampton, SO17 1BJ, UK, Email:firstname.lastname@example.org Abstract This paper investigates the asymmetrical characteristics of junctions and their nearby regions in surround gate vertical MOSFETs. The devices have channel lengths defined by implantation, with processes to address some device performance limitations. A ‘junction stop’ process allows optimization of short channel effects by reducing the junction asymmetry but it also induces additional resistance in the top junction. The fillet local oxidation process serves to reduce overlap capacitances however it also induces asymmetry to the top and bottom junction resistances. Non-uniform interface state density down the channel results in asymmetrical subthreshold characteristic. Using a large tilt angle implantation to dope the body can also introduce asymmetry of drain field induced phenomena such as DIBL and impact ionization. 1. Introduction Our previous research has demonstrated a number of innovations that can effectively address some device performance limitations of submicron vertical surround gate MOSFET (VMOSTs) for RF applications. The gate to drain/source overlap capacitance is reduced by a fillet local oxidation process termed ‘FILOX’ , shortchannel effects by a junction stop structure (JS) [2, 3] and parasitic bipolar effects by a SiGe layer . Nevertheless these novel processes inevitably cause some side effects such as asymmetrical FILOX thickness at the top and bottom of the pillar and native thin oxides at the junction stop structure beneath the polysilicon drain. Additionally any over-etching during definition of the gate electrode can induce significant interface state density Dit at the pillar top . Combining these effects with native asymmetrical junction features of VMOSTs, the transfer and output characteristics can be highly asymmetrical under drain on top (DoT) and source on top (SoT) bias conditions. In this paper, we explore and further by analyzing the physics underlying asymmetrical characteristics of the aforementioned VMOSTs, which are not seen in planar devices. In the VMOST-JS section, the reduced asymmetrical SCE and the more prominent series resistance effect on Ion limitation in SoT are discussed. In the VMOST-FILOX section, the effects on series resistances, arising from asymmetrical FILOX thicknesses at the pillar top and bottom are discussed. Additionally, the cause of asymmetrical sub-threshold slope is believed to be related to excessive Dit induced by over-etch related gate damage. Finally, in devices with body doping formed by large tilt angle implantation, the asymmetrical drain field related phenomenon body lowering (DIBL) and impact ionization are investigated. 2. IV Asymmetry in VMOST with a Junction Stop 2.1 Improved DIBL Asymmetry In VMOST-JS as shown in Fig.1, the junction stop structure allows formation of a shallow junction at the pillar top thus mitigating the problems of charge sharing (CS) and DIBL. Furthermore, the JS structure prevents junction dopant penetration into the centre of the pillar, which could exacerbate bulk punch through. The fabrication process of VMOST-JS is described in , where it is demonstrated that the deep top junction apparent in conventional vertical MOSFET is reduced and can be almost symmetrical with the bottom junction depth. In order to study the improvement on SCE, the device is simulated in ATLAS, Silvaco with the model validated against an experimental device . Simulations are conducted to allow comparison of a conventional VMOST with varying bottom junction, to a lateral MOSFET with varying, symmetrical junction depths. Results are shown in Fig.2. We see that the DIBL of conventional VMOST in DoT mode is higher than that in SoT due to the deep top junction. Physically, the effect is due to the enhanced penetration of drain field and commensurate increase of the channel surface potential and resultant lowering of the source-channel barrier height. The VMOST-JS can be engineered to produce symmetrical shallow junctions (30nm after RTA), which yields acceptable DIBL 120mV and CS 130mV for DoT mode. The conventional VMOST in the SoT mode exhibits similar DIBL performance to the VMOST-JS. However, the CS is not reduced therefore a junction stop is advantageous for overall SCE suppression. The asymmetry of the DIBL effect in DoT and SoT is also decreased thanks to the JS structure. Fig.1 Vertical MOSFET structure with a junction stop. 80 60 40 20 0 0.20 0.18 0.18 0.16 0.16 0.14 0.14 0.12 0.12 0.10 Lateral MOSFET VMOST with DoT VMOST with SoT VMOST-JS in DoT VMOST-JS in SoT 0.10 CS (V) DIBL (V) 100 0.08 0.08 0.06 0 20 40 60 80 100 Drain/Source Junction Depths (nm) Fig.2 Asymmetry of DIBL in conventional VMOST and improvement on DIBL and CS in VMOST-JS. L=70nm, tox=2.5nm, Na=7x1017cm-3 2.2 Effect of Additional Top Junction Resistance The transfer characteristics of experimental VMOSTJS are demonstrated in Fig.3. The device has a high boron doping density of 3x1018cm-3 therefore the DIBL is suppressed in both SoT and DoT mode. The channel length is estimated to be 80nm and gate oxide thickness is 2.5nm. A striking aspect of the transfer characteristics is that the on-current (Ion) in DoT mode is 7.5 times higher than SoT whilst other operating regions almost overlap. This suggests a presence of an additional series resistance apparent in the top junction. As a result, in SoT mode when biased with high drain voltage, the effective gatesource voltage is reduced compared to DoT mode. The on-current asymmetry can also be explained by the asymmetry of VT: 1.15Vin DoT and 1.3V in SoT. The fitting of simulations to experimental data suggests that this additional resistance needs to be about 80K Ω/um to give agreement for Ion in SoT mode. The cause of resistance is suggested to be related to the presence of a thin unintentional native oxide layer beneath the polysilicon drain spacer and the silicon body. 3. IV Asymmetry in VMOST with FILOX Process Ids (A/um) 1 0.1 SoT ( Vds=1.0 V ) 0.01 SoT ( Vds=0.1 V ) 1E-3 DoT ( Vds=1.0 V ) 1E-4 DoT ( Vds=0.1 V ) 1E-5 Simulated SoT (Vds=1V wihtout Radd) 1E-6 Radd=80.0K Ohm/um 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 -3 -2 -1 0 1 2 3 Vgs (V) Fig.3 Transfer characteristics of fabricated device and simulated device L= 80nm, tox=2.5nm, Na=3x1018cm-3. Fig.4 a) A vMOST-FILOX structure (L=100nm) with an equivalent circuit of resistance components; (b) top and bottom junctions; 3.1 Rd and Rs Asymmetry It is known that the device electrical performance and reliability depends more on the source resistance Rs than the drain resistance Rd . Therefore it is also important to investigate the asymmetrical characteristics of drain (top) and source (bottom) resistances of the junction regions, including the influence of the FILOX structure. The resistance components of the bottom junctions are delineated and shown in Fig .4. (We recall that FILOX is self-aligned process that allows a thick oxide grown between the gate to source/drain regions. The device fabrication process is described in  with a 0o tilt source/drain arsenic implant and a 40s RTA at 1100 oC.) We extract the series resistances by considering the impedance of a MOSFET two port system . In this study DoT mode is used. The suitability of the frequency range for extraction is shown by the plot of extracted resistances versus frequency in Fig.5. The frequency dependence due to the parasitic junction capacitances indicate that the method is valid when the test signal frequency is below 1 GHz*. Rs is higher than Rd because the thicker FILOX encroachment above Racc1 in the bottom junction serves to reduce the accumulation layer charge density therefore increasing Racc1, as shown in Fig.4a. A junction surface potential based resistance analytical model* has been developed, which fits the experimental data as shown in Fig.6. The model is used to show that the difference in FILOX thicknesses above the two junctions needs to be on average 7nm in order to explain the asymmetry in Racc1. The analytical modelling also reveals that Racc1 is the dominant component in the junction series resistance. To clarify the influence of FILOX thickness on the series resistance, we carried out extraction of Rd and Rs from the devices, with FILOX thicknesses varied from 20nm to 60nm. The results are illustrated and compared in Fig.6 which shows that series resistances experience a dramatic increase when FILOX thickness increases from 50nm to 60nm. Furthermore, for a 60nm FILOX thickness, the analytical model indicates that, compared to 50nm FILOX, the dramatic increase of Rs is mainly due to * Extraction method and analytical model will be described in the slides. Rs Rd 1150 1100 Series Resistance (ohm/um) Series Resistance (Ohim/um) 1200 1050 1000 950 900 850 800 0 2 4 6 8 10 7500 Rs FILOX 40nm Rd FILOX 40nm Rs FILOX 50nm Rd FILOX 50nm Rs FILOX 60nm Rd FILOX 60nm 6250 Analytical Rs Rs FILOX 20nm Rd FILOX 20nm Rs FILOX 30nm Rd FILOX 30nm 10000 8750 FILOX 40nm 5000 3750 2500 1250 0 1.0 1.5 enhanced encroachment that results in thickening of the oxide above Racc1. The smaller increase of Rd is mainly due to the associated reduction of junction doping level as a result of the screening effect associated with drain/source implantation, of thicker FILOX The devices with thinner FILOX show much less variation in series resistances especially for gate bias above 2.0V. The variation is mainly caused by varying junction doping level for devices with different FILOX thicknesses. The small differences also indicate less asymmetry between Rs and Rd due to significantly less FILOX encroachment into the sidewall near the bottom and top junction boundary. In turn, this results in less variation of Racc1. We observe that using a longer RTA or larger tilt angle drain/source implantation is a necessary process step to extend the junction around the bottom corner and further into the pillar to avoid compromise of series resistance by FILOX encroachment. Consequently the Rd and Rs values and the asymmetry between them are significantly reduced. 3.2 Sub-threshold Slope Asymmetry Before the final metal deposition and RTA, a polysilicon gate track etch is necessary to allow the gate spacer to surround the pillar without covering the entire pillar top. However, over-etching of the polysilicon can induce plasma damage on the thin gate oxide especially at the top of the pillar. As a result, the top segment of the thin gate oxide is exposing during the gate etch and a high level of interface state density Dit can be induced , as shown in Fig.7a. The pillar bottom segment is immune to the damage due to the thicker FILOX and un-etched segment of the polysilicon gate. Simulation of the subthreshold characteristics in DoT and SoT modes is shown in Fig.7b where Dit = 1x1012cm-3 was placed down 50% of the channel length from the pillar top. Dit is acceptor type with a discrete energy level of 0.4eV away from the conduction band. An asymmetry of sub-threshold characteristics in these two modes is evident. In DoT mode, the sub-threshold slope S is hardly affected by Dit whereas it is significant in SoT. The spatial effect of Dit on S for SoT mode is then demonstrated in Fig.8 where the deeper the Dit spreads 2.5 3.0 Fig.6 Rd, Rs vs. Vgs, 0o S/D implant, 40s RTA, Vds=0V along the channel, the more degraded is S. Consequently, the threshold voltage is increased also. In Fig.8, we explore the influence on VT of increasing Dit level and also extending the states further along the channel. 3.3 DIBL and Impact Ionization Asymmetry Introduced by Angled Body Implantation VMOST-FILOX devices were fabricated with boron dopants implanted using a 45o tilt angle into the vertical pillar sidewalls before poly-gate deposition to form a highly doped body. A striking feature of these devices is the asymmetry of the DIBL values, channel modulation and impact ionization in SoT and DoT. In Fig.9 (a), the transfer characteristic shows the DIBL value for DoT is about 190mV while no DIBL can be seen in SoT mode. In Fig.9 (b), the output characteristics show that the channel length modulation for DoT mode is more pronounced compared to SoT. The breakdown voltage in DoT mode is 2.25 V while that for SoT is 5.0 V. Fig.10 shows the substrate current at high drain biases. DoT mode exhibits about four times higher current than that of SoT. The latter points all suggest that the boron doping level at the pillar top is higher than that at the pillar bottom. The DIBL and channel length modulation are both suppressed in SoT due to a high barrier height at the source end caused by a high boron doping level at the pillar top. Meanwhile at the pillar bottom end, the lower boron 0.01 S o T V d s = 1. 5 V D o T V d s = 1. 5 V 1E-4 1E-6 Ids (A/um) Fig.5 Rd & Rs vs. frequency, FILOX=40nm, 0o S/D implant, 40s RTA, Vgs=1V, Vds=0V 2.0 Vgs (V) Frequency (GHz) 1E-8 1E-10 1E-12 1E-14 1E-16 1E-18 -1.0 -0.5 0.0 0.5 1.0 1.5 Vgs (V) Fig.7 (a) Dit contour in VMOST-FILOX structure; (b) SoT and DoT comparison where high Dit spreads into 50% of the channel from pillar top. 1 All in SoT 0.01 6 1E-8 0 % of L ( High Dit) 1E-10 20 % of L ( High Dit) 1E-12 35 % of L ( High Dit) SoT Vds=4V Vds=3V Vds=2V Higher S & VT 1E-6 Isub (uA) Ids (A/um) 1E-4 DoT 8 Vds=4V Vds=3V Vds=2V 4 2 50 % of L ( High Dit) 1E-14 100 % of L ( High Dit) 1E-16 0 Low Dit only 1E-18 -1.0 -0.5 0.0 0.5 1.0 1.5 -2 -1 0 1 2 3 4 Vgs (V) Vgs (V) Fig. 8 The high Dit (1x1012cm-2) effect on the subthreshold characteristics whereas the low Dit has a level of 5x1010cm-2. Fig. 10 Isub comparison for DoT and SoT modes References doping level induces a small E max. Consequently, the impact ionization and in turn, the substrate current and the avalanche breakdown are suppressed in SoT. The cause of this non-uniformity is likely to be related to a shadowing effect during the angled body implantation where the dopant cannot efficiently reach the pillar bottom due to adjacent pillars. 4. Conclusion In this work, the asymmetrical IV characteristics of implantation defined VMOSTs in DoT and SoT are investigated. The physical asymmetries of the junction and its nearby regions and profiles are explored to explain the variants of IV related asymmetries such as asymmetrical SCE in conventional VMOST, Ion in VMOST-JS, Rd and Rs in VMOS-FILOX, sub-threshold slopes in VMOS-FILOX, DIBL, CLM and impact ionization in VMOST-FILOX with an angled body implantation. The aforementioned asymmetries are studied in relation to the associated fabrication processes which were devised to improve device performances. Acknowledgement: This work was supported by the Engineering and Physical Science Research Council, UK. 1E-3 Vds=0.1 Vds=1.5 Vds=0.1 Vds=1.5 1E-4 1E-5 SoT SoT DoT DoT (A/um) 1E-7 1E-8 1E-9 ds I DoT SoT 0.8 I d s ( m A ) 1E-6 V V V V 0.6 0.4 1E-10 0.2 1E-11 1E-12 1E-13 0.0 1E-14 -3 -2 -1 0 Vgs (V) 1 2 3 0 1 2 3 4 5 6 Vds(V) Fig.9 (a) transfer and (b) output characteristics in both SoT and DoT modes; tox=2.6nm, L=100nm  V. D. Kunz, T. Uchino, C. H. Groot, P. Ashburn, D. C. Donaghy, E. Gili, S. Hall, Y. Wang, P. L. F. Hemment, “Reduction of parasitic capacitance in vertical MOSFET’s by fillet local oxidation (FILOX)”, IEEE Trans. on Electron Devices, vol. 50, pp. 1480-1487, June 2003.  D. C. Donaghy, S. Hall, C. H. Groot, V. D. Kunz, P. Ashburn, “Design of a 50nm vertical MOSFET incorporating a dielectric pocket”, IEEE Trans. on Electron Devices, vol.ED-51, pp. 158-161, Jan. 2004  E. Gili, T.Uchino, M. M. Al Hakim, C.H. de Groot, O. Buiu, S. Hall, P. Ashburn, “Shallow Junctions on Pillar Sidewalls for sub-100 nm Vertical MOSFETs”, IEEE Electron Device Letts., vol.EDL -27 pp. 692– 695, Aug. 2006.  V. D. Kunz, C. H. Groot, P. Ashburn, S. Hall, “Gain Control in SiGe HBTs by the Introduction of Germanium into Polysilicon Emitters”, IEEE Trans. on Electron Devices, vol.ED-50, pp. 1481-1486, June 2003.  M. M. A. Hakim, L. Tan, T. Uchino, O. Buiu, W. Redman-White, S. Hall, P. Ashburn, “Improved Subthreshold Slope in RF Vertical MOSFET using a Frame Gate Architecture”, Accepted by ESSDERC, 2008.  L. Tan, O. Buiu, S. Hall, E. Gili, T. Uchino, P. Ashburn, “The Influence of Junction Depth on Short Channel Effects in Vertical Sidewall MOSFETs”, Accepted by Solid State Electronics, March 2008.  J.F. Chen, J. Tao, P. Fang, C. Hu, “Performance and reliability comparison between Asymmetry and symmetric LDD devices and logic gates”, IEEE J Solid-State Circuits, vol. 34(3), pp.367-71 1999.  E. Torres-Rios, R. Torres-Torres, G. Valdovinos-Fierro, E.A. Gutiérrez-D., “A Method to Determine the Gate Bias-Dependent and Gate Bias-Independent Components of MOSFET Series Resistance From SParameters”, IEEE Trans. on Electron Devices, vol. 53, no. 3, pp.571-573, March 2006.