Max Dreo
Vincent Luu
Julian Warchall
Team Avengers Project Proposal
Problem
Digital circuits that operate in the subthreshold region are driven by much weaker currents
than those that operate for values above VT. Because of this, subthreshold circuits are
characterized by longer propagation delays and lower power consumption. Due to being
dependent on the threshold voltage for operating in the subthreshold region, subthreshold
circuits are impacted heavily by process variations.
We will analyze different structures and techniques for designing flip flops at subthreshold
voltages. In these regions, process variations in individual transistors, specifically variations in
transistors’ threshold voltages, can cause registers to become unstable or operate incorrectly.
We will analyze the effects of the variations of transistor threshold voltages and account for this
factor when designing a flip flop topology.
Approach
Our approach is to extensively review subthreshold circuit design literature in order to get a
feel for the best techniques and design strategies which yield circuits resilient to variations in
threshold voltage between individual transistors. Once we have a grasp of common techniques,
we will design various flip flop architectures and simulate them with Monte Carlo
randomization of the transistors’ threshold voltages. Ideally, we can then produce a single flip
flop architecture that functions correctly within certain limits on a Gaussian distribution of
threshold voltages.
We will also look at the metrics that will be affected by our new flip flop architecture. As we
complete and test our simulations, we will measure delay, power consumption and leakage
power. We will compare our design to the basic master slave flip flop in order to show the
tradeoffs in implementing our flip flop design.
Design
Our plan is to apply sub-threshold design techniques from research papers to come up with a
novel flip flop design that is robust to variations in transistor threshold voltage. Preliminary
research into the topic indicates that dynamic flip flop architectures are not appropriate for
sub-threshold operation due to their dependence on short clock cycles to hold intermittent
values (Alstad, 2008). Sub-threshold circuits are generally used for low-power applications
where the clock speed is minimized. Therefore, we will select a static flip flop architecture to
use as the basis of our design.
Some articles indicate that the PowerPC 603 architecture and the SAFF (sense amp flip flop) are
suitable for ultra-low-power operation (Zhang, 2007 and Jin, 2011). These two designs should
be a good starting point from which to design a novel flip flop architecture. Another author
conducted a comprehensive review of research papers in the area of sub-threshold design
(Radfar, 2012). To improve stability under PVT variations, many techniques have been
employed, including transistor stacking, upsizing, and body biasing. Our design may implement
some of these techniques.
Expected Outcomes
A flip flop design that is robust to variations in transistor threshold voltage and functions well at
subthreshold power supply levels is expected as a result of this research. We also expect to
have a table comparing the metric values of our flip flop design to those of a basic flip flop.
Novelty
We believe that this will be a unique study on variations of threshold voltage and the impact of
these variations on designing a new flip flop in the subthreshold region. We have seen many
publications that propose different structures for a flip flop in subthreshold, but we believe it
would be more valuable to provide one that covers variations in threshold voltages. Our work
will result in a robust flip flop design.
Preliminary Simulations
Prior to our first design review, we conducted preliminary simulations of two standard flip flop
architectures at low voltages. At a clock frequency of 1 MHz, we achieved the following results
at different Vdd values:
For a static master slave pass gate flip flop design:
Vdd (mV)
250 300 350 400 450 500
750
1,000 1,250
avg i (nA)
123.60 146.70 166.90 190.30 214.80 240.60 419.80 750.70 1,323.00
leak i (nA)
13.40 15.24 17.64 17.32 19.59 8.16 48.26 86.15 200.10
clock t (ns)
30.55 30.28 30.17 30.14 30.13 30.12 30.12 30.10 30.10
q t (ns)
31.54 30.71 30.40 30.25 30.23 30.16 30.13 30.11 30.11
delay (ns)
0.99 0.43 0.23 0.11 0.10 0.04 0.01 0.01 0.01
Avg power (nW) 30.90 44.01 58.415 76.12 96.66 120.30 314.85 750.70 1,653.75
For a static master slave clocked inverter flip flop design:
Vdd (mV)
250 300 350 400 450
500 750 1,000 1,250
avg i (nA)
145.60 173.00 200.80 229.50 259.30 291.60 522.60 974.20 1,750.00
leak i (nA)
19.33 22.00 24.63 29.22 31.59 55.13 76.30 108.21 269.80
clock t (ns)
25.39 25.15 25.08 25.05 25.01 25.00 24.99 24.98 24.98
q t (ns)
26.20 25.38 25.18 25.12 25.07 25.04 25.00 24.99 24.98
delay (ns)
0.81 0.23 0.10 0.07 0.06
0.04 0.01 0.01 0.00
Avg power (nW) 36.40 51.90 70.28 91.80 116.685 145.80 391.95 974.20 2,187.50
Voltages much below 250 mV resulted in non-functionality. We may reduce the frequency to
500 kHz and re-simulate to see if we can operate at 100mV.
These results do not include any simulation of transistor threshold voltage variations. We will
use simulation results with threshold voltage variations to help our design. Full Monte Carlo
testing of our final flip flop design will measure these metrics with variations taken into
account. We wanted baseline metrics to compare our flip flop design values against.
Timeline
By 10/19 – Simulate our register at varying VT values to solve for metrics and functionality
By 10/26 – Start implementing/optimizing sub-threshold techniques into our register topology
By 11/02 – Continue simulations on new flip flop design
By 11/09 – Prepare for Design Review 2
By 11/16 – Finalize our Design and prepare for final presentation
By 11/30 – Wrap up Final Paper and Presentation
Task breakdown
Most of our work is done together in a group; we assign tasks to individuals to get
accomplished on a weekly basis. We have a group meeting weekly to discuss ideas and
problems with our flip flop design. Then, we assign tasks to be accomplished until the next
meeting and regroup to exchange our findings.
References
Alstad, H.P.; Aunet, S., "Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm
CMOS Technology," Design and Diagnostics of Electronic Circuits and Systems, 2008. 11th IEEE
Workshop on , pp.1-4, 16-18 April 2008.
URL:http://ieeexplore.ieee.org.proxy.its.virginia.edu/stamp/stamp.jsp?tp=&arnumber=4538745
&isnumber=4538735
Jin, Wei; Lu, Sheng; He, Weifeng; Mao, Zhigang, "Robust design of sub-threshold flip-flop cells
for wireless sensor network," VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th
International Conference on, pp.440-443, 3-5 Oct. 2011.
URL:http://ieeexplore.ieee.org.proxy.its.virginia.edu/stamp/stamp.jsp?tp=&arnumber=6081623
&isnumber=6081592
Radfar, Mohsen, Shah, Kriyang, and Singh, Jugdutt, “Recent Subthreshold Design Techniques,”
Active and Passive Electronic Components, vol. 2012, Article ID 926753, 11 pages, 2012.
URL:http://www.hindawi.com/journals/apec/2012/926753/cta/
Zhang, Jianjun; Sun, Yihe, "Low-Power, High-Performance and Low Clock Swing D Flip-Flops with
Single Power Supply," Electron Devices and Solid-State Circuits, 2007. IEEE Conference on,
pp.855-858, 20-22 Dec. 2007.
URL:http://ieeexplore.ieee.org.proxy.its.virginia.edu/stamp/stamp.jsp?tp=&arnumber=4450260
&isnumber=4450045