David J. Bumstead___________________________________________________
David Bumstead
eMatter Design Services
Hardware/Software Design
10157 Ute Hwy.
Longmont, CO 80504
Phone: 303 990-9113
Cell: 805 657-2916
Email: dave@davebumstead.org
Web Site: www.davebumstead.org
Picture at right: Me in middle climbing
Mt. Whitney with 2 friends 6/20/2002
just after 99 switchbacks.
OBJECTIVE:
Be part of a team doing ASIC Design, FPGA Design, Hardware Design, Analog Design,
Embedded Software Design, Test Development, or Corporate Apps Engineer.
SKILLS CHART:
Total Experience per skill
Date Started Working
Date Finished Working
Hardware Design Digital (yrs.)
Hardware Design Digital (gates)
Hardware Design Analog (yrs.)
Hardware Design Analog (parts)
Embedded Software Design (yrs.)
Embedded Software Design (lines)
ASIC Design Standard Cell (yrs.)
ASIC Design Standard Cell (chips)
ASIC Design Custom Cell (yrs.)
ASIC Design Custom Cell (chips)
Software Design (yrs.)
Software Design (lines)
Test Development (yrs.)
Test Development (projects)
Corporate Apps Engineer (yrs.)
Corporate Apps Engineer
(projects)
Total Years per company
9.75
38942
0.75
826
2.25
4096
1
1
4
3
1
310
6
8
1.5
012004
062004
042000
092002
0.5
535
0.25
3000
0.25
291
0.25
2048
072000
082001
021996
111999
121982
021996
061980
071981
071979
061980
061973
061979
1
4500
3
6000
0.5
2000
1
2000
4
21442
2
2048
2
4
1
1
4
3
1
310
4
4
1
5
26.25
0.5
0.75
4
1
0.5
3
13
1
1
EDUCATION:
9-4-1976 MS EE Computers University of Southern California
6-8-1973 BS EE California State University at Fullerton
6-8-1973 BA Math Westmont College, Santa Barbara, CA.
SECURITY CLEARANCE LEVEL:
Secret
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David J. Bumstead___________________________________________________
SPECIAL ACCOPLISHMENTS:
In 1989 Delco Systems Operations chose to sub contract a job out to a high tech company in
Silicon Valley to design our Magic V 1750 Computer Custom ASIC. The job was taking a very
long time to complete. And the job that was originally estimated at 1 year grew to 2 and 3. Finally
Delco decided to pull the job back from the high tech company in Silicon Valley and do it in
house. In early 1992 about 5 of Delco’s engineers began working on it. The first task, of creating
a speed vector was estimated at 18 man-months to complete. I took the job on and was able to
complete it in 1 man-month. That is the accomplishment I am most proud of. We were able to
tape out the MVSC chip in 6 months.
TECHNOLOGIES:
EMBEDDED PROCESSOR’S/ASSEMBLER’S USED (Most recent to oldest)
Microchip PIC Microcontroller (PIC16F876) using MPASM assembler and MPLAB-SIM
simulator, Intel Microcomputer 8031, Zilog Z80 CPU, Rockwell (R6502) Microcomputer, Hughes
HMC-1632 Microprocessor which uses AMD’s AM2901 4-bit slice Processor for 32 bit width and
also using a System 370 Cross assembler to assemble the code on an IBM 370 computer.
FPGA’S/ASIC’S USED (Most recent to oldest)
Actel A54SX172A2BG256I(.25um/.22um), Xilinx XC4008E, IBM-SA12 Gate Array(.18um),
National Semiconductor Custom ASIC Designed with Genesil(.65um, .72um, .8um, 1.5um, 2um,
3um), LSI Logic 5000 series Gate Array.
DIGITAL DESIGN TOOLS USED (Most recent to oldest)
Protel Designer, Actel Libero IDE, MPLAB ICD, Xilinx Foundation Express, Altera Max Plus
II, Quartus, DX Designer, Verilog, VHDL, Modelsim, Blast, Genesil.
ANALOG/EMI/SIGNAL INTEGRITY TOOLS USED (Most recent to oldest)
XTK, Eplanner, Quiet Expert, ACGrade, Hyperlynx, Qspice, Microsim Pspice.
IEEE STANDARD BUSSES USED (Most recent to oldest)
PC-104, VME, PC ATX, PC XT, PC AT, ISA, EISA, RS 232, RS 422, PI-BUS, 1553.
SOFTWARE/OPERATING SYSTEMS USED (Most recent to oldest)
Binview, DacAnalyze, MS Windows (XP, 2000,NT), MS-Office (Word, Access, Excel,
Outlook, Powerpoint, Project, FrontPage, Publisher, InfoPath), Visio, MFC,MS Visual C++, MS
Visual Basic.net, Lab View, Matlab, Clarify, Perl, AWK, SQL, X-Windows, HTML, LINUX, UNIX,
Solaris, Lotus (123, ccMail), PL/1, Fortran, Basic, C, DB2, TSO, VAX/VMS
EXPERIENCE:
1-2010 to 6-2010
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eMatter,
Scientist
David J. Bumstead
10157 Ute Hwy,
Longmont, CO 80504
Reviewed the Transmission Lines Chapter (15) of the book “High Speed Digital Design –
A Handbook of Black Magic by Howard Johnson and Martin Graham
Shortcomings of ordinary point to point wiring
Signal distortion in regular point to point wiring
EMI in point to point wiring
Crosstalk in point to point wiring
Infinite uniform transmission line
Ideal distortionless, lossless, transmission line
Lossy transmission lines
Low-loss transmission lines
RC transmission lines
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David J. Bumstead___________________________________________________
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Skin Effect
Attended the International Test Conference in 1992 which was in Baltimore Maryland.
Went online to the proceedings of the International Test Conference 2002, Session 3
Logic BIST, Paper 3.1 EFFICIENT PATTERN MAPPING FOR DETERMINISTIC LOGIC
BIST by Valentin Gherman, Hans-Jachim Wunderlich, Harald Vranken
Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines
advantages of deterministic external testing and pseudo-random LBIST. Unfortunately
previously published DLBIST methods are unsuited for large IC’s since computing time
and memory consumption of the DLBIST synthesis algorithms increase exponentially, or
at least cubically, with the circuit size.
1-2008 to 12-2009
$20/hr.
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WEBUILDN,
Maintenance/Builder
Dan Bumstead Supervisor
40700 Gibbel Rd,
Hemet, CA 92544
For the Bumstead Probate Property (40 acres) weed wacked 40’ around 3 buildings for
fire protection, kept oak tree limbs from touching power lines and buildings, split and
stacked oak fire wood, fixed leak in main water pipe whenever it happened, initially
cleared plumbing clog in toilet that had been there for years.
Installed new drain pipe to septic tank and new pipe to dry well.
For the Bumstead Probate Property (40 acres) in SH, installed new peaked roof in
kitchen with sunroof, installed new wiring thru out and installed electrical panel on
adjacent wall.
For the Bumstead Probate Property (40 acres) in WH, installed new roof, decking, pine
boards for inside ceiling, 6” insulation in ceiling, new hardwood floor throughout, new
toilet, drained the septic tank.
Designed a custom home with 5449 sq ft. under roof area with a 3D design tool and
converted it to a real house with Cobs Homes Owner/Builder Services for my home at
1162 Combs Rd (www.cobshomes.com). And sold the lot and plans for $220,000.
1-2004 to 6-2004
$55/hr.
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325 SE Sheridan Rd.
Sheridan, OR 97378
Installed siding, painting inside and out, installed landscaping, rehung doors.
7-2004 to 1-2008
$20/hr.
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WEBUILDN,
Builder
Dan Bumstead Supervisor
INNOVATIVE INTEGRATION INC.,
Mixed Signal Design Contractor
Ken Hanson Supervisor
2655 Park Center Dr.
Simi Valley, CA 93065
Designed and checked out the analog part of the ATK Controller board which has 16 fully
redundant (primary and redundant) analog inputs (differential or single ended) at 3 KHz
sample rate (84 KHz into FPGA), and 16 of 17 analog outputs (differential or single
ended) using Orcad.
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Did a trade study for the Delta-Sigma design of the DAC which included a Spice analysis
on DAC which used the delta-sigma approach in which a high frequency pulse train (~12
MHz clock) with the proper ratio of 1’s to 0’s is applied to a filter that eliminates the high
frequency switching components to obtain the desired output voltage and reduced board
area.
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Used the Actel FPGA for its rad hardness and user friendliness.
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Did the post-layout simulation using Modelsim at three temperatures (-40 C, 0 C, and +85
C) and compared with data taken by the layout tool Designer which was a static timing
analyzer.
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It was first pass success to better than 5 places of the decimal.
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David J. Bumstead___________________________________________________
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Did parts selection for the military (883B) and rad hard version.
Analyzed the data using Binview, Innovative Integration’s analog data analysis tool.
Did the spectral analysis using a spectrum analyzer and the DacAnalyze program which
extracts the signal to noise ratio (SNR) and total harmonic distortion (THD).
4-2000 to 7-2000
1-2002 to 9-2002
$55/Hr.
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879 Ward Dr.
Santa Barbara, CA 93111
Led a trade study to determine whether we should use RS422 or RS485. Because of the
risk to schedule of using RS485, we decided to use 1 transmit and 5 individual receives for
the SSBL interface.
Provided my input to program manager, Dennis Schumann’s schedule, showing where I
could contribute most to the entire program.
Designed and checked out the SSBL Controller board which had all digital components.
Designed a program for a Microchip PIC Microcontroller (PIC16F876) to respond to
commands via RS232, including BIT, calibration, read calibration data, and respond to
RTOC interrupts containing 2048 lines of code in PIC assembly language.
Added special loader code, and reassembled using MPASM assembler which was part of
the MPLAB IDE Microchip PIC lab Integrated Development Environment.
Did simulation of the code with an integrated simulator to MPLAB called MPLAB-SIM.
Designed a mixed signal PWB board, called the DSP/MUX board, VME format, which
contained dual TMS320C6701 floating point DSP modules running at 160 Mhz for a
throughput of 2 Gflop which resided on either side of the board.
Used dual A to D part, AD9260, providing 16 bit precision running at 2.5 MHz with 416 KHz
frame sync.
Designed a Sync signal that resynced the External Sync with the sample frequency.
Designed and checked out the prototype and the first production unit.
Wrote a board description, board check, and data sheet which are a customer requirement.
Used Foundation 2.1i Design Software to design a Xilinx XC4008E FPGA and associated
PWB for Sonatech's new SSBL Sonar. Wrote timing constraints for the design.
7-2000 to 8-2001
$87,000/yr.
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SONATECH INC.
Mixed Signal Design Contractor
Vic Welker Supervisor
INNOVEDA INC.
Corporate Applications Engineer
Chuck Berman Supervisor
1369 Del Norte Rd
Camarillo, CA 93010-8437
Handled customer support calls for the high speed tools (XTK and PCB interfaces) and input
problems into Clarify database.
Solved difficult problems by duplicating the problem on my computer. And if the problem
was a defect in our code, worked with our software developers to identify it as such and
solve the problem.
Attended Bug Review meetings to report the latest cases and get input from the developers
on most recent fixes.
Wrote Application Notes and Technology Tips.
Was responsible for testing of the new version of the high speed tools for EPD2.0 on the
SUN, HP, and NT platforms.
Helped customers create correct IBIS models.
Created and debugged demos for all high speed tools including the XTK Post Layout
Tutorial
2-1996 to 11-1999
$72,696/Yr.
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HUGHES SPACE AND COMM.
Sr. Staff Engineer
Dan Bunke Supervisor
4
2260 E. Imperial Hwy.
El Segundo, CA 90245
02/12/16 6:32 AM
David J. Bumstead___________________________________________________
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Created a VHDL Testbench to create the Rounder, Flip-flop and other macro cells for ICO
and GEO which were used by ASIC designers at the next level.
Used Synopsys for synthesis and Modelsim for simulation, and veccomp for comparing RTL
level to the gate level.
Wrote AWK scripts for automating the design methodology on both the Suns and the HP's.
Wrote scripts in AWK to import timing data from 3 different fab lines for determining worst
case timing for the IBM SA-12 Standard Cell ASIC (.18um gate length and 2347 total pins)
that were fabbed with Honeywell, LMFS, and MED.
Created the schematic and did checkout for the FCCT slice which was a 9”x12” PWB with
14 layers containing 2 IBM SA-12 ASIC’s which performed the CCT function, 2 1533
interfaces, 2 ADC’s, 2 power valid circuits, and 2 pulse circuits in a primary and redundant
mode running at 80 MHz and using PECL clocks.
Checked out an analog power valid circuit, analyzed it with Pspice, and built a breadboard,
and checked it out.
Designed a test for our DAC part (AD9720) and traveled to Lawrence Livermore Labs to test
it for radiation tolerance.
Led a team of engineers and wrote the final FMEA report for the Return Processor for both
ICO and GEO projects which specified all single point faults and resulting failure mode which
was 300 pages.
Used MATLAB to write a test for and find the error rate for a special signal.
12-1982 to 2-1996
$72,696./Yr.
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6767 Hollister Ave.
Goleta, CA 93117
Performed logic compilation, layout, simulation, and timing analysis for 2 of the 3 Custom
ASIC's (.65um, .72um, .8um, 1.5um, 2um, 3um), which comprise the system (MVSC, MIU,
and CBC) using Genesil Silicon Compiler.
Created the speed vectors for these chips and probed the chip to validate the timing data.
Performed layout and mengen for Delco’s first Custom ASIC Test Chip using Genesil.
Performed a full set of parametric tests for Delco’s first Custom ASIC Test Chip at National
Semiconductor.
Modified the existing code of Genesil written in C to provide a proper solution to the User DV
errors of incorrect line widths which was 50 lines of code.
Provided the successful respin method for MIU by becoming familiar with the 26 subroutines
in the current MIU written in the GSL Simulator language and reprogramming them to do the
intended respin with 24 hrs which consisted of 260 lines of code.
Designed the Address Unit of the new M6 Computer which had a1750 Architecture and was
an advanced version containing a separate FPU using Verilog and containing 3000 gates.
Wrote tests to checkout of an engine monitor system (EMS) which categorized the vibration
of jet engines for diagnostic purposes which used a TI 32010 DSP to analyze accelerometer
data. The tests were for the dual port RAM.
Designed a Universal Bubble Memory Controller ASIC capable of interfacing to 6 different
bubble memories and several different computers which used LSI Logic’s 5000 series Gate
Array. Coded the firmware for the timing section which specified the timing of the driver
signals for the Bubble Memory. It was a complete success with first silicon.
6-1980 to 7-1981
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DELCO SYSTEMS OPERATIONS,
Senior Design Engineer
Richard Streufert Supervisor
Steven Peltan Supervisor
NATIONAL SEMICONDUCTOR,
Bubble Memory Applications
George Reyling Supervisor
2900 Semiconductor Dr.
Santa Clara, CA 95051
Sell customers on the benefits of using Bubble Memory over existing memory technology.
Give presentations to NATIONAL'S Sales Representatives and interested companies
across the nation.
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David J. Bumstead___________________________________________________
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Did evaluation of NATIONAL'S Bubble Memory controller chip NBC82851 and three
support chips: DS3615-Bubble Memory Function Driver, DS3616 Memory Coil Driver, and
DS3617 Bubble Memory Sense Amplifier.
Designed and built a Bubble Memory Demonstration Unit used by sales representatives to
fully demonstrate as well as test and repair all NATIONAL'S present Bubble Memory
products.
7-1979 to 6-1980
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PO Box 3310
Fullerton, CA 92634
CUSTOM VACUUM DIVISION
Draftsman
Berwyn Lovelady Supervisor
1115 W Struck Ave.
Orange, CA. 92667
Did drafting for all the parts in the catalog (2000) using isometric templates. Created the
installation drawings to show installers how to install the dental vacuum systems.
Substituted on the manufacturing floor as needed creating new parts and doing assembly of
new items. Also did a turn at Shipping and Receiving.
9-1967 to 6-1970
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HUGHES AIRCRAFT COMPANY
Member of the Technical Class
Hal Root Supervisor
Designed and did checkout of the I/0 Unit, containing 5 digital cards, for the Digital
Television Graphics (DITEG) system (14,998 gates total) which was the first TV based
radar for the Navy.
Wrote a 2048 line by 32 bit program executed on a Hughes HMC-1632 Microprocessor (
which uses AMD’s AM2901 4-bit slice Processor) to fully test the capability of the DITEG
system.
Taught an in-house class on programming the Hughes HMC-1632 Microprocessor.
Designed and did checkout of 2 digital cards for the Automated Status Board (ASTAB)
system (6444 gates total). I created my own unique font (9x11) for the Navy in one of the
cards and provided video muxing of 16 possible channels in the other.
DITEG interfaced to 4’ x 6’ Liquid Crystal Displays, the navy’s new digital radar display.
The Hughes requirements for documentation of the ASTAB design is extensive and included
power, operation, functional theory, block diagrams, timing diagrams, word diagrams, logic
equations, firmware, circuit card assemblies, schematics, and support drawings for a total of
511 pages of which I did a major part.
DITEG had a similar equipment manual of 1916 pages of which I provided a major role.
6-1970 to 6-1973
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Anaheim, CA
Designed and checked out a Bubble Memory board RLM658 capable of storing up to 256K
bytes in Bubble Memory and used a Rockwell R6502 Microprocessor. The board had 50
MSI chips which is equivalent to 2000 gates of logic.
Did the system level design of both the 6502 code and the host file/utility programs.
6-1973 to 7-1979
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ROCKWELL INTERNATIONAL
Project Engineer - RMS Project
WESTMONT COLLEGE
Custodian
955 La Paz Rd.
Santa Barbara, CA. 93108
Cleaned toilets, washed floors, dusted, and did maintenance on Kerr Hall and many other
buildings on campus.
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David J. Bumstead___________________________________________________
ADDITIONAL COURSES:
Digital Systems Testing and Testable Design – Abramovici, Breuer, Friedman
Infrared System Engineering – Hughes Aircraft
Genesil Silicon Design – Delco Systems Operations
Artificial Intelligence – Delco Systems Operations
Inertial Navigation – Delco Systems Operations
Built-In Test for VLSI (BIST)– Delco Systems Operations
Satellite Communications Systems Engineering: LEO, MEO, GEO – Hughes Space and Com.
Altera Optimizing Designs for 20K Devices – Hughes Space and Com.
ASIC Synthesis using Synopsys – University of Phoenix Online
Microsim PSpice Workshop – Hughes Space and Comm.
Signal Integrity Analysis with XTK – Innoveda Inc.
Interconnect Planning with ePlanner – Innoveda Inc.
Accelerating SOPC Design Flow – Mentor Graphics / Altera
High-Speed Digital Design A Handbook of Black Magic – Howard Johnson and Martin Graham
PROFESSIONAL REFERENCES:
Dan Bumstead
Open Door Community Church
PO Box 65
Sheridan, OR 97378
Pastor/Builder
Voice:
Web:
Email:
Ken Hanson
Innovative Integration Inc.
2655 Park Center
Simi Valley, CA 93065
Principal Engineer
Voice:
Vic Welker
Sonatech Inc.
879 Ward Dr.
Santa Barbara, CA 93111
Sr. Design Engineer
Voice:
Chuck Berman
Mentor Graphics Inc
1369 Del Norte Rd.
Camarillo, CA 93010-8437
Corp Apps Mgr.
Ben Kim
Sonatech Inc.
879 Ward Dr.
Santa Barbara, CA 93111
Sr. Design Engineer
Voice:
Steven Peltan
Synopsys Inc.
700 E. Middlefield Rd.
Mountain View, CA 94043-4033
Field Technical Rep
Voice:
Fax:
Email:
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