1
EXPERIMENT 01
RTL Circuits
Objectives
1. Examine the RTL characteristics.
2. Familiarize with the internal working of the RTL circuits.
3. Design and analyze an RTL inverter and determine its input-output
characteristics, Propagation delay, and noise margins.
Required Equipments





Oscilloscope
Power supply
Function generator
Digital Multimeter
Bread-Board o Protoboard
Required Parts list





10 K ¼-watt resistor.
0.1 F capacitor
470  ¼-watt resistor.
2N2222 NPN silicon transistor, or equivalent
1N4001 Diode semiconductor
Background
Resistor-Transistor Logic (RTL) refers to the obsolete technology for designing
and fabricating digital circuits that employ logic gates consisting of nothing but
transistors and resistors. RTL gates are now seldom used, if at all, in modern digital
electronics design because it has several drawbacks, such as bulkiness, low speed, limited
fan-out, and poor noise margin. A basic understanding of what RTL is, however, would
be helpful to any engineer who wishes to get familiarized with TTL, which for the past
many years has become widely used in digital devices such as logic gates, latches,
buffers, counters, and the like.
Basically, RTL replaces the diode switch with a transistor switch. If a +5V signal
(logic 1) is applied to the base of the transistor (through an appropriate resistor to limit
base-emitter forward voltage and current), the transistor turns fully on and grounds the
output signal. The output signal rise to +5 volts if the input is grounded (logic 0), the
transistor is off. In this way, the transistor does invert the logic sense of the signal, but it
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also ensures that the output voltage will always be a valid logic level under all
circumstances.
RTL gates also exhibit limited 'fan-outs'. The fan-out of a gate is the ability of its
output to drive several other gates. The more gates it can drive, the higher is its fan-out.
The fan-out of a gate is limited by the current that its output can supply to the gate inputs
connected to it when the output is at logic '1', since at this state it must be able to drive
the connected input transistors into saturation.
Another weakness of an RTL gate is its poor noise margin. The noise margin of a
logic gate for logic level “0”, Δ0, is defined as the difference between the maximum input
voltage that it will recognize as a “0” (VIL) and the maximum voltage that may be applied
to it as a “0” (VOL of the driving gate connected to it). For logic level '1', the noise
margin Δ1 is the difference between the minimum input voltage that may be applied to it
as a '1' (VOH of the driving gate connected to it) and the minimum input voltage that it
will recognize as a '1' (VIH). Mathematically, Δ0 = VIL-VOL and Δ1 = VOH-VIH. Any
noise that causes a noise margin to be overcome will result in a “0” being erroneously
read as a '1' or vice versa. In other words, noise margin is a measure of the immunity of a
gate from reading an input logic level incorrectly.
In an RTL circuit, the collector output of the driving transistor is directly
connected to the base resistor of the driven transistor. Circuit analysis would easily show
that in such an arrangement, the differences between VIL and VOL, and between VOH and
VIH, are not that large. This is why RTL gates are known to have poor noise margins in
comparison to DTL and TTL gates.
Some years ago, when RTL ICs were the standard logic devices used in both
commercial and experimental digital circuits, transistors typically had a forward current
gain of about 30. With improved manufacturing techniques, modern transistors show
current gains of 100 or more. There is also far less variation between transistors of a
given type. As a result, we can tolerate a much lower input current to drive the transistor
reliably into saturation. The resistor values in the schematic diagram reflect the
capabilities of modern transistors; they are significantly higher than the values used in
RTL ICs, allowing working circuits to be built that require far less operating current.
RTL Inverter
The output signal of a NOT logic gate
(Inverter) is the complement of the input signal. That
is, when the input signal is low “0”, the output signal
is high “1” and vice versa. A NOT gate can be easily
obtained by means of an inverting amplifier circuit as
shown in Figure 1.
3
Voltage Transfer Characteristic
The voltage transfer characteristic (VTC) is nothing but a sketch of the output
voltage as a function of the input voltage. In this case, the input voltage is increase from 0
to its maximum value (VBB). When the input voltage is zero, the transistor is OFF and the
output voltage is 5 V. This is the maximum output voltage that we can obtain for this
circuit. Let us label this voltage as VOH. The transistor remains in its cutoff state (OFF) as
long as the input voltage is less than 0.6 V.
Transistor operation characteristics
 Base-to-emitter cut-in (turn-ON) voltage VBE(ON) = 0.6 V
 Base-to-emitter voltage in the active region VBE = 0.7 V
 Base-to-emitter voltage in the saturation region VBE(sat) = 0.8 V
 Collector-to-emitter voltage in the saturation region VCE(sat) = 0.2 V
As soon as the input voltage reaches 0.6 V, the transistor is ready to turn ON.
Thus, 0.6 V is the maximum input voltage that we can apply to the transistor and keep it
in its cutoff mode. Let us label it as VIL. These voltages are shown in Figure 2.
Figure 2: Transfer characteristic of an RTL Inverter
When the input voltage increases above 0.6 V, the transistor enters its active
region. As soon as the input voltage goes above 0.7 V, the base-to-emitter voltage in the
active region is 0.7 V. The remainder of the applied voltage is the voltage drop across
RB, which results in the base current and thereby the collector current. As the collector
4
current begins to flow in the transistor, the output voltage begins its decline. As the input
voltage increases, the base current increases, the collector current increases, and the
collector-to-emitter voltage decreases. The operation in the active region continues until
the collector-to-emitter voltage becomes equal to its saturation voltage. The transistor is
now at the verge of saturation. The collector current is 10.21 mA. If  = 100, the base
current is 0.1021 mA. Let us denote the input voltage that forces the transistor to enter the
saturation region as VIH. Note that VIH is the minimum value of the high-input voltage
and is given as
If we denote the corresponding low output voltage as VOL, then VOL = VCE(sat) =
0.2 V. These voltages are also shown in Figure 2. As the input voltage increases above
1.82 V, the output remains at 0.2 V and the transistor goes into deep saturation. The
operation in the deep saturation region continues until the input voltage reaches its
maximum value.
SUMMARY: In the above discussion we have defined some terminology pertaining to
the RTL circuit. We will use this terminology for all types of gates. Therefore, let us
formally define it.
Voltage Transfer Characteristic
VOH = Nominal High Output Voltage
This is the output voltage that corresponds to logic 1 (high) and it may vary with the
loading and temperature. The manufacturers usually specify its minimum value in order
to compensate for the component tolerances and variations in the loading conditions.
VOL = Nominal Low Output Voltage
This is the gate output voltage that corresponds to logic 0 (low). The manufacturers
usually specify its maximum value.
VIH = High input voltage at which |dvo/dt| = 1
The minimum input voltage that is interpreted as logic 1 (high) by the gate.
VIL = Low input voltage at which |dvo/dt| = 0
The maximum input voltage that is interpreted as logic 0 (low) by the gate.
Transition Region: The region between VIL and VIH is called the transition region.
Transition region is mostly the active region and it is the forbidden region for the
logic circuit. The input voltage should either be low (less than or equal to VIL) or high
(greater than or equal to VIH). If there is a random noise in the system, it should be small
enough such that it does not drive the transistor into the forbidden region.
Transition Width: It is the difference between the two input voltages (VIH – VIL). For
RTL gate, the transition width is 1.22 V.
5
Logic Swing: The difference between the two output voltages (VOH – VOL) is designated
as the logic swing. For the RTL under discussion, the logic swing is 4.8 V.
Noise Margins
The input signal to a gain can be corrupted by some unwanted and unexpected
signal. If the gate is not properly designed the unwanted signal can force the gate to
malfunction. A noise margin is the figure of merit for the gate. If the noise margin is high
the gate is less susceptible to malfunction. We define the noise margin for each level of
the input signal. Thus, we have the definitions for the lower- and upper-noise margins for
the low- and high-level of the input signal.
These margins are defined as follows:
The Lower Noise Margin: NML = VIL – VOL
By definition, it is the difference between the maximum allowed input voltage
that can be interpreted as low by the gate and the actual low output voltage of the
preceding stage driving the gate. For the RTL circuit we just analyzed, the maximum
input voltage that can be interpreted by the gate as low is 0.6 V. The gate usually receives
the input signal from the other gate whose minimum output is 0.2 V. Then the lower
noise margin is 0.4V=(0.6V – 0.2V). Keep in mind that each gate generates a random
noise voltage, however small it may be. For the RTL gate under discussion, the largest
random noise voltage that can corrupt the low input signal is 0.4 V. The reason, of
course, is that when the random noise voltage is added to the input voltage, the total
voltage should be less than or equal to the maximum input voltage that is interpreted as
low by the gate. Since the actual input signal voltage is 0.2 V, the maximum input
voltage that can be added to it is 0.4 V, which is simply the lower noise margin.
The Upper Noise Margin: NMH = VOH – VIH
By definition, it is the difference between the actual output voltage of the
preceding stage driving the gate and the minimum value of the input voltage that can be
interpreted as high by the gate. For the RTL gate under discussion, the maximum input
voltage is VBB=5 V. The minimum input voltage that the gate can interpret as high is 1.82
V. Then, the upper noise margin is 3.18 V = (5V – 1.82V). This simply means that the
largest random noise voltage that the gate can tolerate is 3.18 V. The logic circuit should
still be able to interpret the input voltage as high when the upper noise margin is
subtracted from the input signal. All our discussion pertains to a single RTL circuit.
When it is used as a driver for other gates, its noise margins are bound to change, as we
will show later.
6
Dynamic Response of Logic Gates
An important figure of merit to describe logic gates is their response in the time
domain.
The rise and fall times, tf and tr, are measured at the 10% and 90% points on the
transitions between the two states as shown by the following expressions:
V10% = VL + 0.1ΔV
V90% = VL + 0.9ΔV = VH – 0.1ΔV
Where ΔV = VH – VL. Rise and fall times usually have unequal values; the characteristic
shapes of the input and the output waveforms also differ.
Propagation Delay
•
Propagation delay describes the amount of time between a change at the 50%
point input to cause a change at the 50% point of the output described by the
following:
V50% 
VH  VL
2
7
•
The high-to-low propagation delay,
τPHL, and the low-to-high propagation delay,
τPLH, are usually not equal, but can be described as an average value:
P 
 PLH   PHL
2
8
Pre – Laboratory
RTL Inverter Propagation Delay
In this laboratory the concept of propagation delay is addressed for the RTL
inverter using PSPICE to simulate Transient behavior. The RTL inverter circuit is shown
in Figure 5.
Figure 5: RTL Inverter Schematic Circuit
Circuit description and specific parameters
The input voltage
vin is a PULSE waveform with an amplitude of 5V, the rise time
(TR) and fall time (TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of
200 NS and a period (PER) of approximately 500 NS.
The transistor used in all simulations will be a 2N2222 with the following model
parameters for both Netlist and Schematic circuit.
.MODEL parameters for the npn transistor are:
IS=1E-14 A, BF=50, VAF=80 V, TF=0.45NS, TR=5NS, CJE=7.6PF, CJC=3PF, RB=13,
RC=6.2
9
Pre – Laboratory Procedure
1. Use PSPICE1 to get the transient response for the circuit shown in Figure 5.
2. Plot both Vin and VCE as outputs superimposed on the same plot.
3. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the
report's questions.
4. Determine
τPHL and τPLH for the simulation and record the values in the report's
questions.
5. Print the plot.
Pre – Laboratory Report
1. What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
2. Calculate
τPLH and τPHL for the simulation.
τPLH = __________________
τPHL = _________
3. What is the propagation delay of the gate?
τP = _________
1
First become familiar with the MicroSim PSPICE software installed on the PC Lab (INCADEL or
CRAY). Refer to the manual for PSPICE for getting started in the construction of a circuit, adding
Specific
Parameters
for
Transient
https://ece.uprm.edu/seminarios/.
Analysis
and
for
other
tips
for
plots
or
visit
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Laboratory Procedure
RTL Inverter Voltage Transfer Characteristic
1. Wire the circuit shown in Figure 6.
2. With your Multimeter, measure the base-emitter, base-collector, collector-emitter,
and collector DC voltages, with respect to ground, and measure the base and
collector DC currents, recording your values in table 1 of the report.
3. Use the Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the Xaxis sensitivity at 0.5 Volts/division.
4. Adjust the X zero reference to the screen center and the Y reference below the
center.
5. The input VS is a sine wave from a function generator with a peak amplitude of 5
Volts and frequency of 100 Hertz.
6. Draw a rough sketch of the characteristic displayed on the oscilloscope in the
Graphic 1(Indicate the scales that were used) of the report and ask the question.
7. Determine VIL, VIH, VOL, and VOH for the VTC displayed on the oscilloscope and
record the values in the report's questions.
Figure 6
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Laboratory Report
Table 1
DC Parameters
IC
IB
VC
VBC
VBE
VCE
Graphic 1
Measured Measured
Valued
Valued
Vin = 0V Vin = 5V
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1. Record the values of VS corresponding to the VC values given below from the
transfer curve displayed on the oscilloscope.
VC = 4V
Vin =______V.
VC = 3V
Vin =______V.
VC = 2V
Vin =______V.
2. What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
3. What are the noise margins for the Gate?
NMH = ____________
NML = ____________
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EXPERIMENT 02
7400 Standard NAND Gate: Transient Analysis and Voltage Transfer
Characteristic.
Objectives
4. Examine the TTL characteristics.
5. Familiarize with electrical properties of logic gates built from bipolar transistors
(TTL).
6. Build and test logic gate networks for measure its voltage transfer characteristics,
Propagation delay, Fan-Out, and power dissipation of the 7400 TTL NAND.
Required Equipments





Oscilloscope
Power supply
Function generator
Digital Multimeter
Bread-Board o Protoboard
Required Parts list






1 200  ¼-watt resistor
1 510  ¼-watt resistor
2 1 K ¼-watt resistors
1 10 K potentiometer
1 1N4148 Diode
1 7400 TTL NAND gate
Background
Now that we have studied the characteristics of the saturating transistor inverter,
we have the knowledge in place to understand the behavior of the transistor-transistor
logic or TTL. For years, TTL has been a workhorse technology for implementing digital
functions and for providing “glue logic” necessary in microprocessor system design. TTL
is interesting from another point of view since it is the only circuit that we shall encounter
that makes use of transistors operating in all four regions of operation—forward-active,
inverse-active, saturation, and cutoff.
The classical TTL inverter shown in Figure 1 solves is the typically circuit found
in TTL unit logic in which several identical gates are packaged together in a single dualin-line package, or DIP. Transistor Q1 controls the supply of base current to Q2. Input
voltage Vi causes the current iB1 to switch between either the base-emitter diode or the
base-collector diode of Q1. Q2 forces the output low to VCESAT2. The load resistor is an
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active pull-up circuit formed by transistor Q4 and diode D1. Q3 and D1 are required to
ensure that Q4 is turned off when Q2 is turned on and vice versa.
Figure 1
A complete standard Two-input TTL NAND gate is shown in the schematic in
Figure 2. If any one of the two input emitters is low, then the base current to transistor Q3
will be zero and the output will be high, yielding Y = AB .
15
Figure 2
In this lab, you will know the electrical properties of logic gates built from bipolar
transistors (TTL)
Power Dissipation
Power dissipation is the power lost in the transistors of a logic gate. Since modern
integrated circuits involve millions of transistors, it is important to minimize this power
loss (the very first Pentium CPU had 3.2 million transistors).
y measuring the input characteristics and the transfer characteristics of all the
chips, we can assess the power loss of each chip. The current flowing into a gate at any
point is a good indication of power dissipation. To assess the amount of power dissipated
by a gate at a specific state, we simply measure the current flowing into the gate at that
state. A comparison of the output voltage to the input voltage during a change in state of
a logic gate can provide information on how much power is lost as the gate switches. In
the plot of output voltage versus input voltage, the slope indicates the amount of power
dissipation. A steeper slope indicates smaller power dissipation.
Pre-Laboratory Procedure
Perform the following simulations for the 7400 TTL NAND of the Figure 2.
1. DC transfer characteristics: Use the DC command to step Vin from 0 to 5V in
16
0.1V increments. Obtain the plot of the DC transfer curve Vout versus Vin using
PROBE.
2. Transient response: Carry out a transient simulation and obtain the plot of Vin
and Vout using PROBE. Use Vin as a PULSE waveform with an amplitude of 5
Volts, rise and fall times equal to 2 NS and delay time equal to 0 NS, set the pulse
duration for 50 NS and pulse period for 100 NS.
Pre-Laboratory Report
1. For the 7400 TTL NAND gate, determine VIH, VOH, VIL, VOL and the break
points from the DC simulations.
2. From the transient simulations, determine τPHL and τPLH and calculate the average
propagation delays for TTL NAND gate.
3. Calculate the average power dissipation for the circuit.
Laboratory Procedure
Part A: Electric Characteristics
1. Assemble the circuit in Figure 3 using the 7400.
a. Mount the 7400 (TTL) carefully and firmly with the pins in the center rows of
your breadboard. Connect the 5-volt DC supply to VCC and connect ground
to GND of the 7400.
b. Connect pin 1 to the +5V supply via the 1kΩ resistor, connect pin 2 to one of
the probes of the digital Multimeter (DMM), and leave the other probe
unconnected. Use the DMM to measure the input current when the second
probe is connected to +5V via the 1kΩ resistor (pin 2 is pulled high), and
when the second probe is connect to ground via the 510Ω resistor (pin 2 is
pulled low). Use the DMM to measure the output voltage at pin 3 as the input
voltage is changed. Record the readings, indicating the polarities, in the Table
1 of the report.
c. Remove the 7400, and replace it with the 74LS00 and repeat step a and b. You
can use the same circuit configuration because the pin locations for all two
chips are exactly the same.
17
Figure 3
2. Assemble the circuit in Figure 4 using the 7400.
3. Vary the input voltage from zero to maximum by adjusting the potentiometer.
4. Measure the indicated voltages, Vi and VO, using either the digital Multimeter or
the oscilloscope. Record the readings in Table 2 of the report.
5. Remove the 7400, and replace it with the 74LS00 and repeat step 3 and 4.
Figure 4
Note: For the details of the pin-outs and other device characteristics, see the specification
sheets at the back of your manual, or the Motorola Web site.
18
Part B: Dynamic Behavior
1. Assemble the circuit in figure 5 using the 7400
2. Using the function generator, produce a 5V peak-to-peak triangular wave at 1
KHz. Adjust the DC Offset on the function generator to create a positive unipolar
wave, which means the signal never drops below zero.
3. Use channel 1 of the oscilloscope to measure Vi and channel 2 to measure VO. Set
both channels of the oscilloscope to DC coupling.
4. Sketch the waveform of VO versus Vi on the graphic 1 provided in the laboratory
report. Indicate the scales that were used.
5. To display the output voltage (VO) versus the input voltage (Vi) waveform on the
oscilloscope, Turn Time/division button to XY. The waveform that you obtain
displays channel 2 (VO) versus channel 1 (Vi). Channel 2 is on the y-axis and
channel 1 is on the x-axis.
6. Remove the 7400, and replace it with the 74LS00 and repeat step 2 to 5.
Figure 5
Part C: Fan-Out for the 7400 TTL NAND
1. Connect the circuit as shown in figure 6 using the 7400.
2. VS is a sine wave with amplitude of approximately 5 Volts and frequency
approximately 100 Hz. Set the oscilloscope in the DC and X-Y modes.
3. Plot the DC transfer curve displayed on the oscilloscope for a fan-out of 6 on the
graphic 2 of the report. Indicate the scales that were used.
19
Figure 6
4. Connect the output of one gate to the six inputs of the remaining three NAND
gates (as shown in Figure 7) and plot the DC transfer curve for a fan-out of 6 on
the graphic 3 of the report. Indicate the scales that were used.
5. Determine the average power dissipation in the IC by measuring the current being
supplied by VCC. Use an analog DC Multimeter for the dc current measurement.
Do NOT use the digital Multimeter for the current measurement.
6. Remove the 7400, and replace it with the 74LS00 and repeat the step 1 to 5.
Figure 7
20
Laboratory Report
Table 1
V-I Characteristic
Input current when pin 2 is high
Output voltage when pin 2 is high
Input current when pin 2 is low
Output voltage when pin 2 is low
7400
Table 2
Voltage Characteristics
v
i
0V
2V
4V
6V
8V
10V
Graphic 1(7400 and 74LS00)
7400
vO
74LS00
vO
74LS00
21
1. From the input current values that were measured in Part A-1, which is the power
dissipation for both chips? Explain your reasoning.
2. Using the table of measured values that you obtained in Part A-4 plot VO versus
Vi for the 7400 and 74LS00 in different colors.
3. Refer to the data sheet of the DM7400 to obtain the value of V IH. VIH is the
Manufacturer’s minimum level for an input 1. On the graph you just plotted, draw
a vertical line at Vi =VIH. Does the chip operate within this specification? Explain
your reasoning. You may want to look at the typical values for VOH and VOL.
22
4. From the data sheet of the DM7400, find the value of VIL. This is the
manufacturer’s maximum level for and input 0. On the graph of the previous
page, draw a vertical line at Vi = VIL. Does the chip operate within this
specification? Explain your reasoning.
5. Compare the static and dynamic measurements of the transfer characteristics for
the 7400 and explain your conclusions.
Graphic 2(7400 and 74LS00)
23
Graphic 3(7400 and 74LS00)
6. What are the noise margins (NML and NMH) for a fan-out of 2 and 6 for both
chips?
7. How much is average power dissipation in both chips?
24
EXPERIMENT 03
Analysis of a Schottky RTL inverter
Objectives
7.
8.
9.
Examine the Schottky RTL characteristics.
Familiarize with the internal working of the Schottky RTL circuits.
Design and analyze a Schottky RTL inverter and determine its input-output characteristics,
Propagation delay, and noise margins.
Required Equipments





Oscilloscope
Power supply
Function generator
Digital Multimeter
Bread-Board o Protoboard
Required Parts list






10 K ¼-watt resistor.
470  ¼-watt resistor.
0.1uF capacitor.
1N4148 diode rectifier.
2N2222 NPN silicon transistor or equivalent.
NTE583 or NTE584 Schottky diode.
Background
A serious problem that severely limits the switching speed of BJT inverter is the amount of time
required to remove the enormous stored charge from the base of a saturated BJT. The Schottky-clamped
transistor drawn in figure 1 was developed to solve this problem. The Schottky-clamped transistor consists
of a metal semiconductor Schottky barrier diode (SBD) in parallel with the collector-base junction of the
bipolar transistor.
When conducting, the forward voltage drop of the Schottky diode is designed to be approximately
0.30 to 0.45 V, so it will turn on before the collector-base diode of the bipolar transistor becomes strongly
forward-biased. Referring to Figure 1, we see that
v =v −v
CE
BE
SBD
= 0.70V − 0.30V = 0.4 V
25
Figure 1: Schottky-clamped transistor.
If the input current in increased, the SBD will begin to conduct at VSBD(ON) =
0.3V. Hence, the base-collector junction reaches the forward-bias of VBC = 0.3V. Any
further increase in current i’B entering this configuration will be diverted from the base of
the BJT, though the SBD, and turn into the collector of the BJT. Thus, VBC is limited to
VSBD(ON) = VBC(HARD)= 0.3V. This BJT – SBD combination is called a Schottkyclamped BJT (SBJT) or Schottky transistor and the BJT cannot operate in saturation.
Hence, the time consuming saturation stored-charge removal (and insertion) for the base
is eliminated.
The mode of operation where the BJT is forward active and the Schottky diode is
conducting is referred to as the “on hard” mode. This mode is similar to saturation with
VBE increased to 0.8V, except VBC is only forward biased to 0.3V. An SBJT inverter is
shown in Figure 2.
Figure 2: Schottky RTL inverter
Invention of this circuit required a good understanding of the exponential dependence of the BJT
collector current on base-emitter voltage as well as knowledge of the differences between Schottky and PN
junction diodes. Successful manufacture of the circuit relies on tight process control to maintain the desired
difference between the forward drops of the base-emitter and Schottky diodes.
26
Pre – Laboratory
Schottky RTL Inverter Propagation Delay
In this laboratory the concept of propagation delay is addressed for the Schottky RTL inverter
using PSPICE to simulate Transient behavior. The Schottky RTL inverter circuit is shown in Figure 3.
Figure 3: Schottky RTL Inverter
Circuit description and specific parameters
The input voltage VS is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time
(TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of 200 NS and a period (PER) of
approximately 500 NS. The transistor used in all simulations will be a 2N2222.
Pre – Laboratory Procedure
6.
Use PSPICE to get the transient response for the circuit shown in Figure 3.
7.
Plot both
8.
Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's
v
questions.
in and
v
OUT
as outputs superimposed on the same plot.
27
9.
Determine
τPHL and τPLH for the simulation and record the values in the report's questions.
10. Print the plot.
Pre – Laboratory Report
4.
5.
What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
Calculate
τPLH and τPHL for the simulation.
τPLH = __________________
6.
τPHL = _________
What is the propagation delay of the gate?
τP = _________
Laboratory Procedure
Schottky RTL Inverter Voltage Transfer Characteristic
8.
Wire the circuit shown in Figure 4, the input voltage VS = 0V.
9.
With your Multimeter, measure the base-emitter, base-collector, collector-emitter, and collector
DC voltages, with respect to ground, and measure the DC currents and record your values in table
1 of the report.
10. Set the input voltage at 5V and repeat the step 2.
11. Use the Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at
0.5 Volts/division.
12. Adjust the X zero reference to the screen center and the Y reference below the center.
28
Figure 4
13. Wire the circuit shown in Figure 5.
14. The input
v
S
is a sine wave from a function generator with a peak amplitude of 5 Volts and
frequency of 100 Hertz.
15. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 1(Indicate
the scales that were used) of the report and ask the question.
16. Determine VIL, VIH, VOL, and VOH for the VTC displayed on the oscilloscope and record the values
in the report's questions.
Figure 5
29
Laboratory Report
Table 1
DC Parameters
VC
VBC
VBE
VCE
I’B
IB
ISBD
I’C
IC
Graphic 1
Measured Measured
Valued
Valued
Vs = 0V Vs = 5V
30
4.
Record the values of VS corresponding to the VC values given below from the transfer curve
displayed on the oscilloscope.
5.
6.
VC = 4V
VS =______V.
VC = 3V
VS =______V.
VC = 2V
VS =______V.
What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
What are the noise margins for the Gate?
NMH = ____________
NML = ____________
7.
Compare this experiment’s results with experiment one’s result.
31
EXPERIMENT 04
NMOS Inverter
Objectives
1.
2.
3.
Design and analyze an NMOS Inverter.
Determine the voltage transfer characteristic (VTC) of NMOS inverter
Calculate and measure the propagation delays of the NMOS inverter.
Required Equipments





Oscilloscope
Power supply
Function generator
Digital Multimeter
Bread-Board o Protoboard
Required Parts list



10 K ¼-watt Potentiometer
100 nF capacitor.
NMOS
Background
A MOSFET can be used to achieve logic
inversion in the same fashion as the BJT inverter. The
generalized NMOS inverter is shown in Figure 1. The
load device may be a resistor, like that used in the BJT
inverter, but in an actual MOSFET inverter a better
choice for a load is another MOSFET. The input to this
inverter is applied directly to the gate. Hence, the input
voltage is equal to the gate to source voltage
VIN = VGS
No input resistor is needed to limit the input
current since the gate current IG of a MOSFET is
essentially Zero. The output is taken at the drain, and thus
VOUT = VDS
Note that the voltage VL across the load in
Figure 1 can be directly expressed as a function of the
output as follows
VL = VL(VOUT) = VDD - VOUT
Also, since the input current is negligible, the current though the load is equal to the drain current
through the channel of the MOSFET
IL = I D
32
These relations between the voltages and currents of the inverting NMOS and the load device are
used to determine the VTC and power dissipation for NMOS.
Figure 2 shows the NMOS inverter with resistive load, RL. The input to the inverter is at the gate
of the N-channel output transistor NO and VIN= VGS. The output is at the drain and VOUT = VDS = VDD - IL
RL. For VIN < VT, NO is cutoff and does not conduct drain current. Since the resistor current is equal to the
drain current, with VIN < VT, IRL = ID (OFF) = 0 and the output is VOUT = VDD.
As the input in increased slightly above the threshold voltage, NO begins to conduct. At this point,
only a small current flows and the drain voltage is slightly less than V DD. As long as VDS  VGS – VT NO is
operating in the saturation region. With further increase of the input, a larger drain current conducts and the
output voltage continues to fall. The analytical form of the VTC can be found by equating the drain current
with the resistor current to obtain
ID (sat) =IRL
or
k
VGS  VT 2  VDD  VDS
2
RL
Substituting VGS = VIN and VDS = VOUT yields
k
VIN  VT 2  VDD  VOUT
2
RL
Solving for VOUT, we have
VOUT  
kRL
VIN  VT 2  VDD
2
As VIN is further increased, ID increases and the voltage drop across RL can become sufficient to
reduce the drain voltage such that VDS  VGS – VT. Under this condition NO operates in the linear region.
The VTC of the resistor loaded NMOS inverter has the form shown in Figure 3.
33
Propagation Delay
MOS logic families have the lowest power dissipation per gate of any of the logic families. This is
because of the large values of MOSFET resistance and consequently small current levels.
An NMOS gate dissipates power in the same manner form as the BJT gates. That is, the power
dissipated is given by the product of the power supply voltage and average current for a NMOS inverter
PDD  VDD
I DD (OH )  I DD (OL )
2
Significant additional power dissipation also occurs for NMOS families driving switching from
one logic state to another. An expression for the MOS power dissipation during transient switching, called
the dynamic power dissipation, is given by
2
PD  C L vVDD
where CL is the total capacitance at the output of the gate and v is the frequency at which the gate is
switched.
Since the gate terminal is always an input terminal and the gate sinks zero current for all input
voltages fan-out for MOS families is unlimited. This is true for all load devices including a P-channel
MOSFET as is the case for the CMOS inverter. Thus, the fan-out based upon current limitations is infinite
for all NMOS gates. The maximum fan-out is restricted, however, by the maximum propagation delay
tolerable.
Resistor Loaded NMOS Inverter Dynamic Response
34
A capacitance is present between every pair of terminals for a MOSFET. The gate capacitance is
the dominant capacitance and can be evaluated as the approximated sum of the gate-source, gate-drain, and
gate-body capacitance.
The total gate capacitance is the input capacitance between the gate and ground of a resistor
loaded NMOS inverter. When the input logic state to a resistor loaded NMOS inverter is switched low-tohigh or high-to-low, this input (gate) capacitance must be charge or discharged, depending upon the
direction of the input change.
Load Capacitance on a Resistor Loaded
NMOS Inverter
When one resistor loaded NMOS
inverter drives other resistor loaded NMOS
inverters, the input capacitance of each load
inverter must be charged or discharge
simultaneously. A load capacitance on a resistor
loaded NMOS inverter is shown in Figure 4.
The dynamic response of a resistor
loaded NMOS inverter is determined considering
this capacitance load.
35
Output High-to-Low Transition
The transient characteristics of interest during the Output High-to-Low Transition are the fall time
τf and the High-to-Low propagation time τPHL.
The fall time
f 
τf and the High-to-Low propagation time τPHL are expressed as
 1.9VDD  2VT  0.9VOL
C L  2VT  0.1VOL  0.1VDD 
1
 '
ln 

2
'
W 
k VDD  VT   0.1VDD  0.9VOL
k VDD  VT 
L



and
 PHL 
As with
2C LVT
k VDD  VT 
'
2

 1.5VDD  2VT  0.5VOL 

ln 
 VT   0.5VDD  0.5VOL

CL
k ' VDD
τf, τPHL is directly proportional to the load capacitance and inversely proportional to
W/L.
Output Low -to-High Transition
The analysis of the output low-to-high transition involves the charging of the output load
capacitance through the load resistor R L of the inverter. The transient characteristics of interest during the
output low-to-high transition are the rise time
The rise time
τr and the low-to-high propagation time τPLH.
τr and the low-to-High propagation time τPLH are expressed as
 0.9VDD  0.9VOL 

 0.1VDD  0.1VOL 
 r  RL C L ln 
and
 PLH  RL CL ln( 2)
36
Pre-Laboratory
NMOS Inverter Propagation Delay
Simulate the NMOS inverters using PSPICE to determine the voltage transfer characteristic
(VTC) and calculate and measure the propagation delays. The NMOS inverters are shown in Figures 5, 6
and 7.
Circuit description and specific parameters
37
The input voltage VIN is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time
(TF) equal to 2 S, delay time (TD) equal to 0 S, a duration (PW) of 500 S and a period (PER) of
approximately 1 S. VGG = 10V.
The transistors used in the simulation will be a NMOS with the following model parameters for both
Netlist and Schematic circuit.
.MODEL parameters for the NMOS are:
(VTO=1 KP = 20u GAMMA = 0.37 PHI = 0.6 CBD = 3.1E-15 CBS=3.1E-15)
M1 (W=10u L =5u)
M2 (W=5u L =20u)
Pre – Laboratory Procedure
11. Use PSPICE to get the DC operating point for the circuits shown in Figures 5, 6, and 7 and
complete the Table 1 of the pre-laboratory report.
12. Use PSPICE to get the transient response for the circuit shown in Figure 5.
13. Plot both VIN and VDS as outputs superimposed on the same plot.
14. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's
questions.
15. Determine
τPHL and τPLH for the simulation and record the values in the report's questions.
16. Print the plot.
17. Vary W/L ratio of the NMOS M1 for the circuit shown in Figure 5 and repeat step 2 to 5
18. Vary RL for the circuit shown in Figure 5 and repeat step 2 to 5
38
Pre – Laboratory Report
Table 1
NMOS Inverters
DC Parameters
Measured
Valued
VIN=0V
Measured
Valued
VIN=5V
ID
Resistor Load
VDS(OUT)
ID
Saturated Load
VDS(OUT)
ID
Linear Load
7.
8.
VDS(OUT)
What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
Calculate
τPLH and τPHL for the simulation.
τPLH = __________________
9.
τPHL = _________
What is the propagation delay of the gate?
τP = _________
10. Make a comparative analysis of the table 1 data and explain yours reasoning.
39
Laboratory Procedure
NMOS Inverter Voltage Transfer Characteristic
1.
Connect the NMOS inverter shown in figure 5.
2.
Using the DC power supply, vary the input voltage
from 0 to 5 V and use the digital Multimeter to
determine the voltage at the output, and measure the
drain current, recording your values in table 1 of the
report.
3.
Vary the 10 k potentiometer and record the values in
Table 1 of the report.
4.
Replace the DC input voltage VIN with a sine wave
from a function generator with peak amplitude of 5
Volts and frequency of 100 Hertz.
5.
Use the Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at
0.5 Volts/division. Adjust the X zero reference to the screen center and the Y reference below the
center.
6.
Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 1(Indicate
the scales that were used) of the report. Comment on the important points of the graph such as
VOH, VOL, VM, noise margins, etc.
7.
Attach a load capacitance of 100 nF to the output node.
8.
Apply a 200 Hz 0 to 5 volt square wave to the input of the inverter. Set the DC offset to be 2.5V.
Use the oscilloscope to plot vIN and vOUT. Determine the propagation delays,
τPHL and τPLH, of the
inverter.
9.
Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 2(Indicate
the scales that were used) of the report. Comment on the important points of the graph such as
τr, τPHL and τPLH.
τf,
40
Laboratory Report
Table 1
Potentiometer
Position
1K
5 K
10K
Graphic 1
DC Parameters
ID
VDS
ID
VDS
ID
VDS
Measured Measured
Valued
Valued
VIN=0V
VIN=5V
41
Graphic 2
8.
Record the values of VIN corresponding to the VDS values given below from the transfer curve
displayed on the oscilloscope.
9.
VDS = 4V
VIN =______V.
VDS = 3V
VIN =______V.
VDS = 2V
VIN =______V.
What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
10. What are the noise margins for the Gate?
NMH = ____________
NML = ____________
42
EXPERIMENT 05
CMOS Technology
Objectives
4.
5.
6.
7.
Familiarize with the CMOS structure.
Design and analyze a CMOS Inverter.
Determine the voltage transfer characteristic (VTC) of CMOS inverter
Calculate and measure the propagation delays of the CMOS inverter.
Required Equipments





Oscilloscope
Power supply
Function generator
Digital Multimeter
Bread-Board o Protoboard
Required Parts list



.22 nF capacitor.
22 nF capacitor.
NMOS and PMOS transistors
Background
A CMOS inverter is an ingenious circuit which is built forms a pair of NMOS and PMOS transistors
operating as complementary switches as illustrated in Figure3.2. The main advantage of a CMOS inverter
over many other solutions is that it is built exclusively out of transistors operating as switches, without any
other passive elements like resistors or capacitors.
From Figure 1 note that the PMOS (pull-up transistor) is connected between VDD and the output node,
VOUT, whereas the NMOS (pull - down
transistor) is connected between the
output node, VOUT, and the ground,
GND.
The principle of operation is as follows
(refer also to the right part of Figure 2).


For small values of the input
voltage, VIN, the NMOS
transistor is switched off,
whereas the pull-up PMOS
transistor is switched on and
connects the output mode to
VDD.
For large values of the input voltage, VIN, the PMOS transistor is switched off, whereas the pulldown NMOS transistor is switched on and connects the output mode to GND = 0V.
43
A better inside into the working of the CMOS inverter can be obtain by
looking at its transfer and current characteristics presented in Figure 2.
The transfer characteristic presents the output voltage vOUT versus the input voltage vIN. Note that when
the input voltage increases from 0V to 5V the output voltage decreases from 5V to 0V.
The current characteristic presents the current flowing through the transistors between VDD and GND
also versus the input voltage VIN.
From the above characteristics we can observe the existence of three basic regions of operations denoted 1,
2, 3 in Figure 2.

In region 1 when 0 _ VIN < VTN
The NMOS transistor is cut off, the PMOS switch is closed and VOUT = VDD iD = 0

In region 3 when VIN > VDD - VTN
The PMOS transistor is cut off, the NMOS switch is closed and VOUT = 0 and iD=0
The fact that in regions 1 and 3 no current flows between VDD and GND, is very attractive because there is
no power dissipation at this stages. This very fact is the reason that all digital circuitry is now build in the
CMOS technology.
In region 2 when VN < VIN < VP
 The transistor remains only for a short period of time, when the input voltage switches between VL
and VH.

In this region there is non-zero current flowing between VDD and GND, and some power
dissipation, which is converted into heat.
Note that the same current flows through the PMOS and NMOS transistors, that is,
44
IDp = IDn
Transient properties of the CMOS inverter
In this section we will investigate basic transient properties of the CMOS inverter, that is, its dynamic
behavior during switching the input signals from low-to-high or high-to-low voltages and associated power
dissipation.
Propagation delay
Let us consider a CMOS inverter driven by a voltage pulse. Typical input/output waveforms are shown in
Figure 3. Basic characterization of the dynamic behavior of an inverter is given by its two propagation
delay times, HL and LH as illustrated in Figure 3. Note that these propagation times are specified with
respect to the mid voltage V0.5:
Figure 3.7: Input/output waveforms for a CMOS inverter.
The propagation delay times, HL (LH) specifies the input-to-output time delay during the high-to-low (lowto-high) transition of the output voltage.
Often, it is convenient to refer to the average propagation delay, p which specifies the average time
required for the input signal to propagate through the inverter:
Similarly, we can define the fall time, F , and the rise time, R, as the time required for the output voltage
to change between V90% and V10% .
Where V10% = VL + 0.1(VH − VL) , and V90% = VL + 0.9(VH − VL)
45
The physical reason for the propagation time delay is the existence of the parasitic capacitances
associated with a MOS transistor. We can combine all such capacitances into an equivalent load
capacitance, Cld, as illustrated in Figure 4.
As illustrated by the voltage and current characteristics from Figure 2, during transition between low and
high input voltages, there is a current flowing through the transistors forming the inverter. A part of this
current charges and discharges the load capacitance which is responsible for propagation delays.
If we approximate the current flowing through the load capacitance by its average value, Iavg, then the
propagation time can be estimated as:
where ΔV indicates the voltage change across the load capacitance, that is, the change of the output
voltage.
The value of the load capacitance of the inverter without the interconnecting lumped capacitance is in the
order of 0.01pF = 10fF. We can estimate that the propagation time is in the order of p = 100ps = 0.1ns
Pre-Laboratory
CMOS Inverter Propagation Delay
Simulate the CMOS inverters using PSPICE to determine the voltage transfer characteristic
(VTC) and calculate and measure the propagation delays. The CMOS inverter is shown in Figure 5.
46
Figure 5: CMOS Inverter
Circuit description and specific parameters
The input voltage VIN is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time
(TF) equal to 2 S, delay time (TD) equal to 0 S, a duration (PW) of 500 S and a period (PER) of
approximately 1 S.
The transistors used in the simulation will be a NMOS and PMOS with the following model
parameters for both Netlist and Schematic circuit.
Pre – Laboratory Procedure
19. Use PSPICE to get the DC operating point for the circuits shown in Figures 5 and complete the
Table 1 of the pre-laboratory report.
20. Use PSPICE to get the transient response for the circuit shown in Figure 5.
21. Plot both VIN and VOUT as outputs superimposed on the same plot.
22. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's
questions.
23. Determine
τPHL and τPLH for the simulation and record the values in the report's questions.
24. Print the plot.
47
25. Vary W/L ratio of the MOSFETs for the circuit shown in Figure 5 and repeat step 2 to 5
26. Vary CL for the circuit shown in Figure 5 and repeat step 2 to 5
48
Pre – Laboratory Report
Table 1
Circuit
DC Parameters
Measured
Valued
VIN=0V
ID
VOUT
CMOS Inverter
VOUT
11. What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
12. Calculate
τPLH and τPHL for the simulation.
τPLH = __________________
τPHL = _________
13. What is the propagation delay of the gate?
τP = _________
Measured
Valued
VIN=5V
49
Laboratory Procedure
CMOS Inverter Voltage Transfer Characteristic
10. Connect the CMOS inverter shown in
figure 6.
11. Using the DC power supply, vary the
input voltage from 0 to 5 V and use
the digital Multimeter to determine
the voltage at the output, and
measure the drain current, recording
your values in table 1 of the report.
12. Replace the DC input voltage VIN
with a sine wave from a function
generator with peak amplitude of 5
Volts and frequency of 100 Hertz.
13. Use the Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at
0.5 Volts/division. Adjust the X zero reference to the screen center and the Y reference below the
center.
14. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 1(Indicate
the scales that were used) of the report. Comment on the important points of the graph such as
VOH, VOL, VM, noise margins, etc.
15. Attach a load capacitance of 22 nF to the output node.
16. Apply a 200 Hz 0 to 5 volt square wave to the input of the inverter. Set the DC offset to be 2.5V.
Use the oscilloscope to plot vIN and vOUT. Determine the propagation delays,
inverter.
τPHL and τPLH, of the
50
17. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 2(Indicate
the scales that were used) of the report. Comment on the important points of the graph such as
τr, τPHL and τPLH.
τf,
51
Laboratory Report
Table 1
CL
.22nF
22nF
Graphic 1
DC Parameters
ID
VOUT
ID
VOUT
Measured Measured
Valued
Valued
VIN=0V
VIN=5V
52
Graphic 2
11. Record the values of VIN corresponding to the VOUT values given below from the transfer curve
displayed on the oscilloscope.
VOUT = 4V
VIN =______V.
VOUT = 3V
VIN =______V.
VOUT = 2V
VIN =______V.
12. What are the values for :
VIL =
_____
VIH =
_____
VOL =
_____
VOH =
_____
13. What are the noise margins for the Gate?
NMH = ____________
NML = ____________
53
EXPERIMENT 06
Logic Interfacing
Objectives
8.
9.
Familiarize with TTL open-collector devices, three state outputs and transceivers.
Design logic interface between different logic families.
Required Equipments



Digital Multi-meter
Digit-lab
Bread-Board o Protoboard
Required Parts list






10 K ¼-watt Potentiometer
470
TTL Open-collector NAND Gate 7401
TTL NAND Gate 7400
74244 Three stage buffer gate
2 LEDs
Background
Situation often arise where many components in digital system must share a common path to be
able to transfer data to one another. To reduce the number of interconnections, a small set of shared lines
called bus may be used. In general, outputs from different devices cannot be simultaneously present on the
bus. Consequently, for proper operation, that is, to prevent bus contention, only one of the devices
connected to a shared bus can place information on the bus at any time. TTL open-collector devices permit
the simultaneous connection of the outputs of two or more devices to form a bus.
In many applications such as bus-organized digital systems where various outputs must be
ANDed, using TTL gates with totem-pole outputs would require an AND gate with as many input lines as
there are signals to be ANDed.
Additional logic is created when the outputs of two or more open-collector gates are tied together,
as in Figure 1. This scheme is called the wired-AND and is used to save logic gates in comparison with
other methods.
54
It is not possible to interconnect
TTL gates with totem-pole output stages
in the configuration. Figure 2 depicts the
high level current path when the outputs
of totem-pole gates are tied together. Gate
A dissipate a large amount of power, and
Q3B is required to sink a current which
may exceed its guaranteed 16mA sink
capacity.
Although the main application of
the open collector gate is to allow the
formation of the wire-AND, it is also
useful for driving an individual load like
an LED or relay. The output stage for the
two-input open-collector NAND gate
7401 consists solely of the commonemitter transistor without even a collector
resistance. This gate, when supplied with
a proper load resistor RL, may be
paralleled with other similar TTL gates.
At the same time, it will drive from one to
nine standard loads of its own series.
When no other open-collector gates are
tied, it may be used to drive ten loads.
Their main disadvantage is that these
gates are inherently slowly and more
subject to noise than their totem-pole
counterpart. The pull-up resistor bias can
be raised to any voltage within the
breakdown voltage of the driver transistor
55
to enable interfacing to a system employing voltage swings, like a CMOS.
To determine the value of the external pull-up resistor, we should find the upper and lower limits
of the range of values the resistor can take. A maximum value is found which will ensure that sufficient
source current to the loads and off current through paralleled outputs will be available when the output is
logical 1. Therefore, the total leakage current determines the maximum value of R L when all driving
transistors are off, as shown in Figure 4. When Vo is high so that the drivers are off, the voltage drop across
RL must be less than
VRL(max) = VCC – VOH(min)
On the other hand, the total
current through RL is the sum of the
load current IIH and the leakage
current IOH through each driver.
Therefore,
IRL = IOH + NIIH
Where  is the number of gates
wired-AND connected, and N is the
number of standard loads. Note that
IOH is into the output terminal and
hence positive. Using equations 1
and 2, we find
RL(max) = VRL(max)/IRL
RL(max) = (VCC – VOH(min))/ (IOH +
NIIH)
A minimum value for the
pull-up resistor is established when
Vo is logical 0, so that the current
through RL and the total sinking
current from the load gates do not
cause the output voltage to rise
above VOL(max) even if only one driving gate is sinking all the current. Therefore, the current must be
limited to the recommended maximum IOL, which will ensure that the low-level output voltage will be
below VOL(max). Since part of IOL will be supplied from the loads, the amount of current that can be
allowed through RL will be reduced. Hence, neglecting the leakage currents of the turned-off drivers, we
have
RL(min) = VRL(min)/IRL
RL(min) = (VCC – VOL(max))/ (IOL(max) – N|IIL|)
Logical 0 circuit conditions to calculate RL(min) are illustrated in Figure 5. Table 1 provides the
electrical characteristics of the 7401 open-collector NAND gate.
56
Table1: Electrical Characteristics of the two-Input NAND Gate 7401
VOH (min)
2.4V
VIH (min)
2V
VOL (max)
.4V
IOH (min)
250uA
IIH (min)
40uA
IOL (max)
16mA
VIL (max)
.8V
IIL (max)
-1.6mA
PLH
35ns
PHL
8ns
CL
15pF
RL
4k for PLH
400 for PHL
57
Three-State Outputs
Another useful variant of TTL that can solve the problem of driving a common bus line by two or
more logic circuits is the three-state output arrangement shown in Figure 6. The term tri-state is also used.
However, it is registered trademark of National Semiconductor Corporation, which introduced this design
concept in 1970.
Figure 6
By combining the high-speed advantage of the totem-pole output with the advantages of an opencollector output, the three-state gates enable the connection of a number of gates to a common output line
or bus. In addition to a totem-pole output, these gates have another terminal, called the output enable,
which permits the device to function normally or the output signal to be disconnected from the rest of the
circuit by going into a third state in which both output transistors are turned off, resulting in an extremely
high output impedance. Therefore, a disabled gate can be assumed to have an open circuit in its output line,
so that the high impedance state may be equated to the voltage level of a conductor that has no sources
connected to it, that is, it is floating.
The two most frequently used three-state ICs in the standard TTL logic subfamily are the 74125
and 74126 quadruple-bus buffers with independent output controls. Both are non-inverting buffers, but the
former’s output for the 74125 is enabled by a logical 0 while the 74126 is enabled by an active high signal.
Three-State CMOS Buffers
The CMOS three-state output buffer
has logic elements in the gate connections to
each of the transistors in the final inverter, so
that both may be turned off under the control of
an enable function. Figure 7 illustrates the logic
diagram of such a buffer with active low-enable
input. Note that additional inverters are added as
buffers or to optimize timing. The truth table of
the CMOS Buffers is shown in table 2.
58
G'
0
0
1
1
A VGP VGN
0
0
0
1
1
1
0
1
0
1
1
0
Table 2: Truth table
Y
1
0
Z
Z
59
Pre-Laboratory
TTL Open-Collector Outputs
60
Pre – Laboratory Procedure
27. Simulate the circuit shows in Figure 8 using PSPICE. Use 7401 and 7400 TTL OpenCollector NAND and standard NAND respectively.
28. Sweep the value of the pull-up resistor and determine the value maximum and minimum for
optimum performance and complete the Table 1 of the pre-laboratory report.
29. Connect the circuit shows in Figure 9 using PSPICE and determine how many TTL inputs
can drive.
30. Simulate the circuit of Figure 10 using PSPICE and find the DC operating point and complete
the Table 2 of the pre-laboratory report.
31. Simulate the circuit shows in Figure 11 using PSPICE and prove the truth table of the circuit.
Pre – Laboratory Report
Table 1
TTL 7401
Figure 8
RL(Max)
RL(Min)
IRL(Max)
IRL(Min)
DC parameters
How many TTL inputs can drive the circuit of Figure 7
Table 2
Figure 10
DC parameters
VRL
(High)
VOL
IOL
61
Laboratory Procedure
Open-Collector TTL Outputs
18. Connect the circuit of Figure 12 with the 7401 and 7400 TTL Open-Collector NAND and standard
NAND respectively. Vcc = +5V
19. Add load to the output in order to
determine the fan-out of the gate. Use the digital
Multimeter to determine the output voltage and the
currents in the circuit when you are adding a gate and
record your values in table 1 of the report.
20. Co
nnect the circuit
of
Figure
13
using 7401 and
7400 TTL NAND and AND gate respectively with high
input voltages and record your values in Table 1 of the
report. Vcc = +5V
21. Vary the 10 k potentiometer and record the values in
Table 1 of the report.
22. Using the Digit lab DC switch to vary the input voltage
from 0 to 5 V and use the digital Multimeter to determine
the voltage at the output, and the currents in the circuit
recording your values in table 1 of the report.
23. Connect the circuit shown in Figure 14.
24. Using the Digit lab DC switch to vary the input
voltage from 0 to 5 V and use the digital Multimeter
to determine the voltage at the output, and the
currents in the circuit recording your values in table
3 of the report.
25. Change the 7401 TTL Open-Collector NAND by the
7400 standard NAND and repeat step 7.
62
26. Connect the circuit shown in Figure 15.
27. Using the Digit lab DC switch to vary the input
voltage from 0 to 5 V and use the digital Multimeter to
determine the voltage at the output, and the currents in the
circuit recording your values in table 4 of the report.
63
Laboratory Report
Table 1
Loads
VOL
VOH
IOH
IIH
IOL
IIL
1
2
3
4
5
Table 2
DC
Parameters
IRL(OH)=
IRL(OL)=
IRL(OH)=
IRL(OL)=
IRL(OH)=
IRL(OL)=
IRL(OH)=
IRL(OL)=
RL
Value
410
1k
2.3 k
5 k
VOL
VOH
IOH
IIH
IOL
IIL
64
Table 3
Figure 14
VRL
(High)
VOL
IOL
VOH
IOH
VRL
(High)
VOL
IOL
VOH
IOH
7401
7400
Table 4
Figure 15
7400
Compare the results obtain in table 3 and table 4 and explain your conclusions
Conclusions
65
EXPERIMENT 07
Regenerative circuits
Objectives
1.
2.
3.
Wire and observe the operation of an R-S flip-flop.
Wire and observe the operation of a Master-Slave J-K flip-flop level and edge triggered.
Compare the wave shaping action of a regular TTL IC with a Schmitt trigger IC.
Required Equipments




Digit-lab
Bread-Board o Protoboard
Function Generator
Oscilloscope
Required Parts list









7402 2-input NOR gate IC
7404 inverter TTL IC
7414 Schmitt trigger inverter TTL IC
74104 or 74105 J-K Master-Slave flip flop
74109 Dual J-K Positive-Edge-Triggered Flip-Flop with Clear and Preset
74112 Dual J-K Negative-Edge-Triggered Flip-Flop with Clear and Preset
74279 S-R flip flop with NAND
3 LEDs
(2) 150Ohms resistors
Background
Multivibrators are regenerative circuits that are used used to implement a variety of
simple two-state systems such as oscillators, timers and flip-flops. The most common
form is the astable or oscillating type, which generates a square wave - the high level of
harmonics in its output is what gives the multivibrator its common name.
There are three types of multivibrator circuit:



Astable, in which the circuit is not stable in either state - it continuously oscillates from one state
to the other.
Monostable, in which one of the states is stable, but the other is not - the circuit will flip into the
unstable state for a determined period, but will eventually return to the stable state. Such a circuit
is useful for creating a timing period of fixed duration in response to some external event. This
circuit is also known as a one shot. A common application is in eliminating switch bounce.
Bistable, in which the circuit will remain in either state indefinitely. The circuit can be flipped
from one state to the other by an external event or trigger. Such a circuit is important as the
fundamental building block of a register or memory device. This circuit is also known as a flipflop. A similar circuit is a Schmitt trigger.
In electronics and digital circuits, the flip-flop or bistable multivibrator is a pulsed digital circuit
capable of serving as a one-bit memory. A flip-flop typically includes zero, one, or two input signals; a
clock signal; and an output signal, though many commercial flip-flops additionally provide the complement
66
of the output signal. Some flip-flops include a clear input signal, which resets the current output. Because
flip-flops are implemented as integrated circuit chips, they also require power and ground connections.
Pulsing, or strobing, the clock causes the flip-flop to either change or retain its output signal, based
upon the values of the input signals and the characteristic equation of the flip-flop. Strobing here means
changing the clock; some flip-flops change output on the rising edge of the clock, and other change on the
falling edge.
Flip-flops can be split into two main categories: level-triggered and edge-triggered. They can
further be divided into four types that have found common applicability in clocked sequential systems:
these are called the T ("toggle") flip-flop, the SR ("set-reset") flip-flop, the JK flip-flop, and the D ("Data")
flip-flop. The behavior of the flip-flop is described by what is termed the characteristic equation, which
derives the "next" (i.e., after the next clock pulse) output, Q(next), in terms of the input signal(s) and/or the
current output, Q.
Level-triggered flip-flops respond whenever a signal level changes.
Set-reset flip-flops (SR flip-flops)
The SR (set-reset) flip-flop has two inputs: S (set) and R (reset). If R is active, the output goes to
zero. If S is active, the output goes to one. If neither is activated, the previous state is maintained. Both
inputs should not be activated simultaneously; however, if they are, the typical response is for both the
inverted and non inverted outputs to have the same level.
The behavior of an SR flip-flop can be written in the form of a truth table:
S
0
0
1
1
R
0
1
0
1
NOR
Q Q(next)
Q
Q(next)
1
0
0
1
Undetermined
S
0
0
1
1
R
0
1
0
1
NAND
Q
Q(next)
undetermine
x
0
x
1
Latch
Latch
Truth table for an SR flip flop with NOR and NAND gates
We can implement a SR flip-flop with a pair of either NAND or NOR gates. The NOR version is
conceptually easier as it has active high inputs. However, the NAND version is more widely known and
used, as NAND gates were cheaper in transistor-transistor logic.
We can also easily add an enable input. If this is implemented in the same gates as the flip-flop,
then it serves to further invert the inputs - meaning a NAND based device will now have active high inputs.
This input may be regarded as a clock but the flip-flop is still unsuitable for sequential design. When the
clock goes high, the signal will propagate through all flip-flops, not just from one to the next.
67
SR flip-flops circuit diagrams and the symbols for an un-clocked SR flip-flop
A
clocked SR flip-flop and the
symbol for a clocked SR flipflop
Edge-triggered flip-flops only change state on a particular edge (rising, falling, or very
occasionally both directions) of a designated clock signal.
JK flip-flop
The JK flip-flop augments the behavior of the SR flip-flop by interpreting the S = R =
1 condition as a "flip" command. Specifically, the combination J = 1, K = 0 is a command
to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and
the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to
the logical complement of its current value. Setting J = K = 0 results in a D-type flip-flop.
The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as
an SR flip-flop, a D flip-flop or a T flip-flop.
The symbol for a clocked J-K flip-flop
A circuit symbol for a JK flip-flop, where > is the clock input, J and K
are data inputs, Q is the stored data output, and Q' is the inverse of Q.
The characteristic equation of the JK flip-flop is:
and the corresponding truth table is:
J
0
0
1
1
1
K
0
1
0
1
1
Q
Latch
1
0
0
1
Q(next)
Latch
0
1
1
0
68
SCHMITT TRIGGER
In electronics, a Schmitt (or Schmidt) trigger is a comparator circuit that incorporates positive
feedback.
When the input is higher than a certain chosen threshold, the output is high; when the input is
below another (lower) chosen threshold, the output is low; when the input is between the two, the output
retains its value. The trigger is so named because the output retains its value until the input changes
sufficiently to trigger a change. This dual threshold action is called hysteresis, and implies that the Schmitt
trigger has some memory.
The benefit of a Schmitt trigger over a circuit with an only single input threshold is greater
stability (noise immunity). With only one input threshold, a noisy input signal near that threshold could
cause the output to switch rapidly back and forth from noise alone. A noisy Schmitt Trigger input signal
near one threshold can cause only one switch in output value, after which it would have to move to the
other threshold in order to cause another switch.
The Schmitt trigger was invented by US scientist Otto H. Schmitt.
The symbol for Schmitt triggers in circuit diagrams is a triangle with a
hysteresis symbol.
Pre-Laboratory
Regenerative circuits
Wire and test one J-K flip flop from the CMOS 4027 dual J-K flip flop IC. Observe and record your
values in table 1.
Pre – Laboratory Report
Table 1
Inputs
Mode of operation
Asynchronous
Outputs
Synchronous
PS
CLR
CLK
J
K
Asynchronous Set
0
1
x
x
x
Asynchronous reset
1
0
x
x
x
Prohibited
0
0
x
x
x
Hold
1
1

0
0
Reset
1
1
0
1
Set
1
1


1
0
1
1

1
1
Preset
Clear
Clock
Data
Data
Toggle
Q
Q'
1
1
No change
Laboratory Procedure
Regenerative circuits
1.
Wire the logic circuit of the R-S flip-flop shown in Figure. Wire outputs Q and Q’ to two LEDs.
69
2.
Operate the input switches R and S as shown in the truth table in Table 2. Observe and record the
results in the Q and Q’ columns.
3.
In the right column of Table 1, write the name of the condition of the outputs. Use the term
“Hold,” “Set,” or “reset.”
4.
Operate the input switches R and S as shown in the truth table in Table 3 using the 74279 R-S flipflop and record the results in the Q and Q’ columns. Wire outputs Q and Q’ to two LEDs.
5.
In the right column of Table 2, write the name of the condition of the outputs. Use the term
“Hold,” “Set,” or “reset.”
6.
Construct the circuit of the clocked R-S flip flop with NAND. Wire outputs Q and Q’ to two
LEDs.
7.
Operate the input switches R and S as shown in the truth table in Table 4. Observe and record the
results in the Q and Q’ columns.
8.
Insert the 74LS112 IC into the mounting board.
9.
Wire the synchronous inputs PS and CLR to two switches. Wire the
asynchronous inputs J and K to switches and the CLK input to a singlepulse clock. Wire outputs Q and Q’ to two LEDs.
70
10. Operate the asynchronous inputs PS and CLR and record the results in Table 5.
11. In the right-hand column of Table 5 write the condition of the output. Choices are listed.
12. Disable the asynchronous inputs (PS and CLR to 1).
13. Operate the synchronous inputs J, K and CLK of the 74LS112 IC according to the truth table in
Table 6. Observe and record the results in column Q and Q’.
14. In the right-hand column of Table 6 write the condition of the output. Choices are listed.
15. Insert the 7404 and 7414 ICs into the mounting board and wire the circuits shown in the Figure.
16. Set Vin with the function generator. Set the function generator to sine wave. Set the frequency
from 50 to 200 Hz. Adjust the function generator voltage to 2 to 4 V p-p.
17. Use the Oscilloscope to observe the output waveforms for the circuits. Draw a rough sketch of the
characteristic displayed on the oscilloscope in the Graphic 1 and 2(Indicate the scales that were used)
of the report.
71
Laboratory Report
Table 2
NOR
Name of
S
R
0
0
0
1
1
0
1
1
Q
Q(next)
condition
Table 3
R-S flip-flop 74279
Name of
S
R
0
0
0
1
1
0
1
1
Q
Q(next)
condition
Table 4
Inputs
Outputs
Clock
Data
Before clock pulse
After clock pulse
CLK
S
R
Q
Q'
Q
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
0
Q'
Name of condition
Prohibited
Prohibited
Hold, reset, or set
72
Table 5
Inputs
Outputs
Clear
Preset
0
0
0
1
1
0
1
1
Q
Q'
Name of Condition
Prohibited
Clear Q to 0
Disable
Preset Q to 1
Table 6
Inputs
Outputs
Before clock
After clock
pulse
pulse
Clock
Data
CLK
J
K
Q
Q'

0
0
0
1

0
1
0
1

1
0
0
1

1
1
0
1

0
0
1
0

0
1
1
0

1
0
1
0

1
1
1
0
PS and CLR=1
Q
Name of condition
Q'
Hold, reset, set, or toggle
73
Graphic 1(7404)
Graphic 2(7414)
Which IC seems to do the best job of converting the sine wave into a sharp square wave?
74
EXPERIMENT 08
D\A and A/D converters
Objectives
4.
5.
6.
7.
To connect an analog-to-digital (A/D) circuit and perform an A/D conversion
To calculate A/D accuracy and resolution
To connect an analog-to-digital (D/A) circuit and perform an D/A conversion
To calculate D/A accuracy and resolution
Required Equipments





Digit-lab
Bread-Board o Protoboard
Function Generator
Oscilloscope
Digital Multimeter
Required Parts list
Resistors






1 K (3)
2 K (6)
10 K
30 K
100 
2.5k
Integrated Circuits


LM741
DAC0808
Potenciometers

10 K (2)
Diodes

Led (2)
Capacitors

15 pF
Background
Analog-to-Digital Converter
The process of converting an analog voltage to a digital coded signal is known as analog-to-digital
conversion. It is usually referred to as A-to-D (A/D) conversion.
When an analog signal is digitized, the signal is
converted to an equivalent digital number at regular
intervals, called sample intervals, as seen in Figure
Figure 1: Analog signal is sampled at regular intervals
75
The typical A/D converter will have eight output lines. Each line is capable of being a logic 1 or 0.
Each binary digit is called a bit –an acronym for binary digit. Thus such an A/D device is called an 8 nit
A/D converter. Now assuming that each of the eight output lines could be a logic 1 or 0, there are 28, or
256, different binary codes which can be represented by the 8-bit A/D converter. Assume an input voltage
of 0V to the A/D converter; its output would be the binary equivalent, or 00000000. For each input voltage
level there will be a specific equivalent binary output on the eight output lines.
Resolution and accuracy
Resolution of an A/D converter is defined as the smallest increment input voltage that can be
determined by the converter. Resolution is primarily a function of the number of output bits. For example,
if the converter has 256 different outputs codes, the input signal is represented by binary numbers from
00000000 to 11111111. If the input ranges from 0 to 5 V, the resolution is
5V
 0.0195V
256
Thus, the binary output of 00000001 represents 0.0195 V. Likewise, 00000010 represents 0.039
V, and so on. What would be the binary representation of, say, 3.042V? Clearly,
3.042V
 156
0.0195
which, when converted to binary, is 10011100.
The accuracy of the A/D converter is determined by how closed the actual converter output is to
the theoretical output. For example, if the 8-bit A/D converter had an accuracy expressed as  1 least
significant bit (LSB), the accuracy could be expressed as
accuracy 
1
1
*100 
*100  0.4%
8
256
2
Digital-to-Analog converter
In electronics, a digital-to-analog converter (DAC or D-to-A) is a device for converting a digital
(usually binary) code to an analog signal (current, voltage or electric charge). Digital-to-analog converters
are the interface between the abstract digital world and the analog real life. Simple switches, a network of
resistors, current sources or capacitors may implement this conversion.
The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers)
into a physical quantity, usually an electrical voltage. Normally the output voltage is a linear function of the
input number. Usually these numbers are updated at uniform sampling intervals and can be thought of as
numbers obtained from a sampling process. These numbers are written to the DAC, sometimes along with a
clock signal that causes each number to be latched in sequence, at which time the DAC output voltage
changes rapidly from the previous value to the value represented by the currently latched number. The
effect of this is that the output voltage is held in time at the current value until the next input number is
latched resulting in a piecewise constant output (Figure 2). This is equivalently a zero-order hold operation
and has an effect on the frequency response of the reconstructed signal.
The fact that practical DACs do not output a sequence of dirac impulses (that, if ideally low-pass
filtered, result in the original signal before sampling) but instead output a sequence of piecewise constant
values or rectangular pulses, means that there is an inherent effect of the zero-order hold on the effective
frequency response of the DAC resulting in a mild roll-off of gain at the higher frequencies (a 3.9224 dB
loss at the Nyquist frequency). This zero-order hold effect is a consequence of the hold action of the DAC
76
and is not due to the sample and hold that might precede a conventional analog to digital converter as is
often misunderstood.
Figure 2: Piecewise constant signal typical of a practical DAC output.
77
Laboratory Procedure
D\A and A/D converters
1.
Wire the circuit of the D/A converter as shown in Figure 1.
Figure 1: Digital-to-Analog Converter
2.
Operate the input switches as shown in the Table 1. Observe and record the results of the
OPAMP output voltage. The output voltage can be calculated with the standard op-amp
theory.
3.
Connect the circuit shown in Figure 2.
4.
Apply the digital inputs shown in Table 2. For each input measure the analog output voltage
and record it in the table 2.
5.
Wire the circuit of the D/A converter as shown in Figure 3.
6.
Vary the potentiometers to change the comparator input voltage.
7.
Determine the switches combination to set on the LED indicator. Observe and record the
results of the OPAMP output voltage.
8.
Repeat steps 5 to complete the table 3.
78
79
Laboratory Report
Table 1
Input Voltage
Output Voltage
Calculated
Measured
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 2
Binary Inputs
00000001
00000010
00000011
00000100
00001000
00010000
00100000
01000000
10000000
11111111
Table 3
Measured analog output
% Error
80
Input Voltage
1V
3V
5V
10V
12V
15V
Output Voltage
Calculated
Measured
% Error