A FAST SETTLING REFERENCE GENERATOR WITH SIGNAL-DEPENDENT CHARGE
CANCELLATION FOR AN 8-BIT 1.5 BIT/STAGE PIPELINED ADC
A Project
Presented to the faculty of the Department of Electrical & Electronic Engineering
California State University, Sacramento
Submitted in partial satisfaction of
the requirements for the degree of
MASTER OF SCIENCE
in
Electrical and Electronic Engineering
by
Ian Wheeler
SUMMER
2013
A FAST SETTLING REFERENCE GENERATOR WITH SIGNAL-DEPENDENT CHARGE
CANCELLATION FOR AN 8-BIT 1.5 BIT/STAGE PIPELINED ADC
A Project
by
Ian Wheeler
Approved by:
__________________________________, Committee Chair
Perry Heedley, Ph.D.
__________________________________, Second Reader
Thomas W Matthews, Ph.D.
____________________________
Date
ii
Student:
Ian Wheeler
I certify that this student has met the requirements for format contained in the University format
manual, and that this project is suitable for shelving in the Library and credit is to be awarded for
the project.
______________________, Graduate Coordinator
Preetham B. Kumar, Ph.D.
Department of Electrical and Electronic Engineering
iii
________________
Date
Abstract
of
A FAST SETTLING REFERENCE GENERATOR WITH SIGNAL-DEPENDENT CHARGE
CANCELLATION FOR AN 8-BIT 1.5 BIT/STAGE PIPELINED ADC
by
Ian Wheeler
The reference voltage generator is an important circuitry block in pipelined analog-to-digital
converters (ADCs). The function of the reference generator is to provide accurate reference
voltages to the ADC which are compared to the unknown input signal in order to convert analog
data into digital. To maintain sufficient accuracy, the reference voltage generator often consumes
a substantial amount of area and power in relation to other circuits on the integrated circuit. This
project focuses on reducing the power and area required by reference voltage generators used for
pipelined ADCs while maintaining the required accuracy.
To minimize error in the ADC output, traditional reference voltage generator designs used for
pipelined ADCs strive to keep variations in the reference voltages much less than a
least-significant bit (LSB). This is accomplished using two different design methods. The first
method is to use large bypass capacitors on the reference voltage outputs to minimize the glitches
seen in the reference voltages when the residue stage capacitors connect to these outputs. The
iv
second method is to design the reference voltage output buffers to have a very low output
resistance to prevent errors due to the average current drawn from the buffer. Both of these
methods require a large amount of silicon area, and the second also requires a substantial amount
of power to achieve the low output resistances required.
This project proposes a design for the reference voltage generator that can save substantial area
and power compared to the previously described traditional design. Rather than minimizing
variations in the reference voltages, the proposed design described in this report allows the
reference voltages to vary much more as long as they quickly return to their correct values.
Analysis shows that this method requires far less area and power than traditional reference
voltage generator designs.
A second design technique also examined here employs signal-dependent charge cancellation.
Through the use of replica residue stages, the charge injected by the residue stages into the
reference voltage generator outputs can be made signal independent, thereby eliminating this
source of error in the ADC output codes. In combination with the first design improvement, this
signal-dependent charge cancellation allows the requirements on the reference voltage generators
to be further relaxed, thereby saving even more area and power.
This project presents an accurate 8-bit, 1.5-bit/stage pipelined ADC Matlab computer model that
has been derived from a pipelined ADC Matlab model previously developed by Professor Perry
Heedley. This new model was used to verify the proposed reference voltage generator design, as
well as the signal-dependent charge cancellation technique. Analysis of the new reference voltage
v
generator design and the signal-dependent charge cancellation technique was also performed
through Spice simulations of a previously designed 8-bit, 1.5-bit/stage pipelined ADC previously
designed by a team of graduate students at CSU, Sacramento. The end result was a design for
accurate reference voltage generators for pipelined ADCs that have greatly reduced area and
power when compared to conventional designs.
_______________________, Committee Chair
Perry Heedley, Ph.D.
_______________________
Date
vi
ACKNOWLEDGEMENTS
When I originally started this project, I was in a group of five students and the nickname for our
project was called “Odyssey.” This project has been a journey for me and I have learned an
enormous amount about myself and pipelined ADCs. Although my journey is over, I have many
to thank for helping me complete this project.
Most importantly, I would like to thank Professor Perry Heedley. He is the best teacher and
mentor I have ever had. My questions and concerns were always addressed and answered.
Professor Heedley always made his time available to me and others. Most other Professors do not
do this. But, most importantly, Professor Heedley spent his precious time editing my project
report when I didn’t deserve it because of my lack of constant dedication. Thank you very much
Professor Heedley.
I want to thank friends and family for all of their support. Thank you Mom, Aaron, and Lindsay
for constantly loving and supporting me. All your love and support has kept me moving and still
does. I’ll unconditionally love and support you all as well. Thank you to all my friends that
encourage me to succeed not only for this project, but in life as well – Phil Huppe, Chad Brower,
Nicolas Laporte, and Joshua Burkhart.
Also, thanks to everyone that has had some involvement in this project. Thank you Professor
Thomas Matthews for your inputs and edits. Thank you Sriharsha Manjunath and Pranav
Cherupalli. I could not have succeeded without your help and I wish you both the best in your
vii
professional careers. Thank you Chris Gonzales and John Michel for putting in some effort. And
thank you Dhruval Patel and Greg Fattig for help with a few of the other issues I have had.
viii
TABLE OF CONTENTS
Page
Acknowledgements ............................................................................................... vii
List of Tables ......................................................................................................... xi
List of Figures ....................................................................................................... xii
Chapter
1. INTRODUCTION ...............................................................................................1
2. BACKGROUND .................................................................................................3
2.1 Pipelined Analog to Digital Converters .................................................3
2.1.1 Theory of Operation ............................................................... 3
2.1.2 Residue Stage Architecture .................................................. 14
2.1.3 Reference Generator Architecture ....................................... 25
2.2 ADC Performance Measures ...............................................................31
2.2.1 DNL and INL ....................................................................... 33
2.2.2 ENOB, SNR, and SNDR ..................................................... 36
3. REFERENCE VOLTAGE GENERATOR MODELS ......................................39
3.1 Original Slow Reference Generator Model .........................................39
3.2 Fast Settling Reference Generator Model ............................................40
ix
3.3 Tortoise vs. Hare Model Comparison ..................................................42
4. CHARGE CANCELLATION ...........................................................................44
4.1 Charge Cancellation .............................................................................44
4.2 Simplified Charge Cancellation Model ...............................................49
5. CHARGE CANCELLATION PIPELINED ADC MODEL .............................55
5.1 Charge Cancellation Pipelined ADC Model Overview .......................55
5.2 Charge Correction ................................................................................57
5.3 Results ..................................................................................................59
5.4 Impact on Pipelined ADC Design........................................................63
6. CONCLUSION .................................................................................................65
Appendix ................................................................................................................67
References ..............................................................................................................68
x
LIST OF TABLES
Tables
Page
Table 2.1 1-bit/stage Transfer Function ......................................................................................... 5
Table 2.2 1.5-bit/stage Transfer Function .................................................................................... 10
Table 2.3 1.5-bit/stage Transfer Function Equations ................................................................... 22
Table 2.4 Target Reference Generator Values ............................................................................. 27
Table 4.1 Input Vref Connection Table ....................................................................................... 46
Table 4.2 Relationship Between the Input Voltage and the Total Charge Kicked Back
Using Charge Cancellation .......................................................................................... 48
Table 4.3 Values for the Simplified Charge Cancellation Simulations ....................................... 50
Table 5.1 Kickback Charge vs. Input Voltage Including the Charge Correction Circuit ............ 58
xi
LIST OF FIGURES
Figures
Page
Figure 1.1
Die Photograph of ADC2 Team’s Pipelined ADC ..................................................... 2
Figure 2.1
Comparison of ADC Architectures vs. Resolution and Sample Rate......................... 3
Figure 2.2
8-bit Pipeline ADC with 1-bit/stage Architecture ...................................................... 4
Figure 2.3
A Single Stage of the 1-bit/stage Pipelined ADC ....................................................... 5
Figure 2.4
A Visual Representation of the 1-bit/stage Transfer Function ................................... 6
Figure 2.5
A Visual Mapping of the 1-bit/stage Transfer Function for an Input of +Vref/4......... 7
Figure 2.6
Residue Plot for a 1-bit/stage Pipelined ADC ............................................................ 8
Figure 2.7
Residue Plot for a 1.5-bit/stage Pipelined ADC ......................................................... 9
Figure 2.8
Block Diagram of an 8-bit Pipelined ADC with 1.5 bit/stage Architecture ............... 9
Figure 2.9
A Single Stage of the 1.5-bit/stage Pipelined ADC .................................................. 10
Figure 2.10 A Visual Representation of the 1.5-bit/stage Transfer Function .............................. 11
Figure 2.11 A Visual 1.5-bit/stage Transfer Function for an Input Voltage of +Vref/2................ 11
Figure 2.12 Block Diagram of the 8-Bit 1.5-bit/stage Pipelined ADC ........................................ 12
Figure 2.13 Digital Error Correction Concept for an 8-bit, 1.5-bit/stage Pipelined ADC ........... 13
Figure 2.14 Resistor Implemented Using Switches and a Capacitor ........................................... 15
Figure 2.15 Non-overlapping Clocks ........................................................................................... 15
Figure 2.16 (a) Switched Capacitor Discrete-time Integrator
(b) The Circuit Response from a Constant Input Voltage ........................................ 16
Figure 2.17 Switched Capacitor Residue Stage Used by the ADC2 Team.................................. 18
Figure 2.18 Non-overlapping Clock Signals................................................................................ 20
Figure 2.19 Sampling Phase of Reside Stage .............................................................................. 21
xii
Figure 2.20 Settle and Hold Phase for the Residue Stage ............................................................ 23
Figure 2.21 Single-ended Settle and Hold phase with +Vref as the Sub-DAC Output ............... 23
Figure 2.22 Reference Generator Block Diagram........................................................................ 26
Figure 2.23 Voltage Reference Circuit ........................................................................................ 28
Figure 2.24 Reference Voltage Buffer Circuit ............................................................................. 29
Figure 2.25 Ideal Input/Output Transfer Curve for a 2-bit ADC ................................................. 32
Figure 2.26 Offset and Gain Errors for a 2-bit ADC ................................................................... 33
Figure 2.27 DNL and INL Illustrated for an ADC....................................................................... 34
Figure 2.28 Quantization Error .................................................................................................... 35
Figure 2.29 FFT of an N-bit ADC with a Sampling Frequency Fs .............................................. 36
Figure 2.30 An FFT Showing Harmonic Distortion .................................................................... 37
Figure 3.1
Simplified Circuit Showing the Switches Between Vin, Vref, and One of the
Residue Amplifier Capacitors................................................................................... 40
Figure 4.1
Dual Residue Amplifier Architecture with Reversed DAC Inputs........................... 45
Figure 4.2
Block Diagram Showing the Replica and Main Pipelined ADC Stages .................. 46
Figure 4.3
Simple Charge Cancellation Test Schematic ............................................................ 51
Figure 4.4
Results of the Simulations without Charge Cancellation ......................................... 52
Figure 4.5
Results of the Simulations with Charge Cancellation .............................................. 52
Figure 4.6
Expanded View of the Results with Charge Cancellation ........................................ 53
Figure 4.7
Maximum Vref Voltage Drops with and without Charge Cancellation ................... 53
Figure 5.1
ENOB vs. Rout with and without Charge Cancellation ........................................... 56
Figure 5.2
Charge Correction Circuit ........................................................................................ 58
xiii
Figure 5.3
ENOB vs. Rout with and without Charge Cancellation and Correction,
Cbypass = 250pF ...................................................................................................... 59
Figure 5.4 – ENOB vs. Rout with and without Charge Cancellation and Correction,
Cbypass = 100pF ...................................................................................................... 60
Figure 5.5 – ENOB vs. Rout with and without Charge Cancellation and Correction,
Cbypass = 10pF ........................................................................................................ 60
Figure 5.6 – Vrefp vs. Time for the Original ADC with Rout = 1800Ω, Cbypass = 10pF ........... 62
Figure 5.7 – Vrefp vs. Time for the ADC with Charge Cancellation and Correction,
with Rout = 1800Ω, Cbypass = 10pF ....................................................................... 62
xiv
1
Chapter 1
INTRODUCTION
Analog-to-digital converters (ADCs) are used virtually everywhere an analog signal has to be
processed by a digital system, such as a computer [1]. ADCs convert analog signals, which are
continuous in time and value, into digital signals, which are discrete in time and value. Once an
analog signal is converted into a digital format, it can then be easily manipulated in the
computing realm. Applications for ADCs include real-time recording for audio and video signals,
communication receivers, medical imaging equipment, microcontrollers, and electronic test
equipment.
Due to the large number of signal types which need to be digitized, a diverse selection of data
converters exist in terms of circuit architectures, resolution, and sampling rates [2]. Over the
years pipelined ADC architectures have become very popular mainly due to their low power, high
speed, high resolution, and high area efficiency [3,4].
In 2005, a team of graduate students at California State University, Sacramento designed and
implemented an 8-bit 20-Msample/s pipelined analog-to-digital converter using a 1.5-bit per stage
architecture [3]. The project was named ADC2. Their converter had a total static power
dissipation of 450mW from a 5-V supply, with 200mW of that due to the on-chip reference
voltage generator [5]. As seen from their die photo in Figure 1 below, the reference voltage
generator took up roughly one-third of the total chip area.
2
Figure 1.1 – Die Photograph of ADC2 Team’s Pipelined ADC [3]
The reference voltage generator in the ADC2 team’s pipelined ADC chip used almost half of the
total power for the entire chip and took up roughly a third of the area. When looking to improve
the power and area consumption in pipelined ADCs, an obvious starting point would be the
reference voltage generator. In this project, the designs of the ADC2 team have been modified to
incorporate a voltage reference charge cancellation technique using replica residue stages. This
charge cancellation technique reduces the area and power needed for the reference voltage
generator, as explained in Chapter 3.
3
Chapter 2
BACKGROUND
2.1 Pipelined Analog to Digital Converters
A deeper understanding of the pipelined ADC architecture, its functions, and its metrics of
performance are needed to understand the pipelined ADC model that was designed based on the
ADC2 team’s pipelined ADC. In this chapter, the theory of operation of pipeline ADCs will be
discussed as well as a deeper discussion of the main building blocks in the ADC2 team’s
architecture. The main blocks discussed are the residue stage and voltage reference circuits.
Performance metrics for analog-to-digital converters will also be discussed in this chapter.
2.1.1 Theory of Operation
Figure 2.1 – Comparison of ADC Architectures vs. Resolution and Sample Rate [6]
4
The main function of any analog-to-digital converter is to take an analog input signal and convert
it into a digital form. Pipelined ADCs are used because they provide a moderately high resolution
at higher sampling rates than most other ADC architectures [6]. Figure 2.1 shows the ADC
architectures that are currently being used depending on resolution and sample rate.
Pipelined ADCs convert data using multiple stages. Each consecutive stage more fully converts
the analog input from the previous stage. Figure 2.2 shows the 1-bit/stage (pronounced one bit per
stage) pipelined ADC architecture for an 8-bit converter [7]. This architecture is called 1-bit/stage
because one bit of information is determined in each stage. The first stage determines the value of
the most significant bit in the ADC output code, and each consecutive stage determines the next
bit in the output code, with each bit being less significant than the bit from the previous stage. In
Figure 2.2, the digital output code from the conversion would be B7 B6 B5 B4 B3 B2 B1 B0,
with B7 being the most significant bit (MSB) and B0 being the least significant bit (LSB). The
last stage in a pipelined ADC is usually just a simple 1 or 2-bit flash ADC because there is no
need to create a residue signal for the next stage, since no further stages are used.
Figure 2.2 – 8-bit Pipeline ADC with 1-bit/stage Architecture [7]
5
Stages 1-6 in Figure 2.2 are made up of a comparator, a sub-DAC (digital-to-analog converter),
and a residue amplifier. Figure 2.3 shows a block diagram for a single stage in a 1-bit/stage
pipelined ADC. The comparator compares the input voltage to the stage, V in, to a reference
voltage (VTH) of zero, as shown in Table 2.1. If Vin is higher than zero, the output of the
comparator, BN, is a 1. The sub-DAC then converts the digital output from the comparator into an
analog voltage of ±Vref. When BN is a 1, the sub-DAC outputs a voltage of +Vref to be subtracted
from the input voltage. When combined by the summer and residue amplifier, the output voltage,
Vout, becomes (2*Vin) – Vref. If VIN is lower or equal to zero, the output of the comparator,
BN is a 0. In this case, -Vref is subtracted from Vin, and Vout = (2*Vin) + Vref. The 1-bit/stage
transfer function as given in Table 2.1 gives the different possibilities for BN and Vout based on
the input voltage, Vin.
Condition
If Vin ≤ 0V
If Vin > 0V
Digital Output (BN)
BN = 0
BN = 1
Vout
Vout = (2 * Vin) + Vref
Vout = (2 * Vin) - Vref
Sub-DAC Output
-Vref
+Vref
Table 2.1 – 1-bit/stage Transfer Function
Figure 2.3 – A Single Stage of the 1-bit/stage Pipelined ADC [7]
6
Figure 2.4 further illustrates the 1-bit/stage transfer function by showing a visual mapping for
each condition of the 1-bit/stage transfer function. The input voltage is always between the two
reference voltages. Depending on the value of the input voltage, the residue stage creates the
input voltage for the next stage based on the equations in Table 2.1. An example of this is shown
in Figure 2.5.
+Vref
+Vref
0
0
-Vref
-Vref
a) Vin <= 0; Vout = (2 * VIN) + Vref
b) Vin > 0; Vout = (2 * Vin) - Vref
Figure 2.4 – A Visual Representation of the 1-bit/stage Transfer Function
7
If VIN is equal to +Vref/4, the transfer function will be:
Vout = Vin+1 = (2*(Vref/4)) – Vref = -Vref/2
Equation 2.1
Figure 2.5 – A Visual Mapping of the 1-bit/stage Transfer Function for an Input of +Vref/4
Figure 2.6a shows an ideal residue plot of Vout vs. Vin, illustrating the possible values for the
transfer function. Figure 2.6b shows the same transfer function, but with a comparator offset
voltage taken into account. Comparator offsets in a 1-bit/stage pipelined ADC will cause the
transition point in the transfer curve to shift, which leads to clipping and distortion in the output.
Other possible non-idealities in the transfer curve are caused by mismatches in the capacitors in
the residue amplifier, an offset in the residue opamp, and by low gain in the residue opamp. If the
non-idealities are great enough, the ADC will have missing codes which is devastating for
performance.
8
(a) Ideal
(b) With Comparator Offset
Figure 2.6 – Residue Plot for a 1-bit/stage Pipelined ADC [3]
A transfer curve that is not as prone to clipping is needed to achieve acceptable ADC
performance. Figure 2.7 shows the Vout vs. Vin transfer curve for a 1.5-bit/stage pipelined ADC.
The 1.5b/stage architecture is much more tolerant of comparator offsets, which cause the transfer
curve to shift, but not clip, as shown in Figure 2.7b. This improvement makes the 1.5-bit/stage
architecture much more robust than the 1-bit/stage architecture, which has lead to its
wide-spread acceptance as an industry standard architecture.
9
a) Ideal
b) With Comparator Offset
Figure 2.7 – Residue Plot for a 1.5-bit/stage Pipelined ADC [3]
The 1.5-bit/stage name originates from the fact that each pipelined stage divides the input range
into 3 sections, and outputs two bits to indicate in which section the input lies. Out of the 4
possible output codes provided by 2 bits, 3 are relevant. Three relevant codes out of a possible
four equate to one and a half bits of information provided by each stage, hence the name.
Figure 2.8 shows the block diagram of the 1.5-bit/stage architecture used by the ADC2 team.
Figure 2.8 – Block Diagram of an 8-bit Pipelined ADC with 1.5 bit/stage Architecture [7]
10
Three possible output codes means that there are also three distinct conditions for the
1.5-bit/stage transfer function. Table 2.2 shows the different input conditions and corresponding
outputs. The difference in architecture between the 1.5-bit/stage and the 1-bit/stage architectures
can be seen in Figure 2.9. A sub-ADC that consists of two comparators replaces the single
comparator in the 1-bit/stage architecture. There are now two digital output bits instead of one
and the sub-DAC now chooses between three possible analog voltages instead of two.
Condition
Vin ≤ -(Vref/4)
-(Vref/4) < Vin < +(Vref/4)
Vin ≥ +(Vref/4)
Digital Output
(AN, BN)
AN = 0, BN = 0
AN = 0, BN = 1
AN = 1, BN = 0
Vout
Vout = (2 * Vin) + Vref
Vout = (2 * Vin)
Vout = (2 * Vin) - Vref
Sub-DAC
Output
-Vref
0
+Vref
Table 2.2 – 1.5-bit/stage Transfer Function
Figure 2.9 – A Single Stage of the 1.5-bit/stage Pipelined ADC [7]
11
The visual representation of each 1.5-bit/stage transfer function condition is shown in
Figure 2.10.
+Vref
+Vref
+Vref
+Vref/2
+Vref/2
+Vref/4
+Vref/4
0
0
-Vref/4
-Vref/4
0
-Vref/2
-Vref/2
-Vref
-Vref
-Vref
b) -Vref/4 < Vin < +Vref/4
Vout = 2*Vin
a) Vin ≤ -Vref/4
Vout = 2*Vin + Vref
c) Vin ≥ +Vref/4
Vout = 2*Vin – Vref
Figure 2.10 – A Visual Representation of the 1.5-bit/stage Transfer Function
For a Vin of +Vref/2, the corresponding output becomes 0 as shown in Figure 2.11 and solved for
in the example below.
Vout = Vin+1 = (2*(Vref/2)) – Vref = 0
Equation 2.2
+Vref
+Vref/2
+Vref/4
0
0
-Vref/4
-Vref/2
-Vref
Figure 2.11 – A Visual 1.5-bit/stage Transfer Function for an Input Voltage of +Vref/2
12
Up to this point, the residue stages for the 1-bit/stage and 1.5-bit/stage pipelined ADC
architectures have been explained. However, the entire ADC used by the ADC2 team has more
than just these residue stages. The entire chip contains a reference generator, a non-overlapping
clock generator, the pipelined ADC residue stages, and a digital decode and error correction
circuit. These blocks are connected as shown in Figure 2.12. The non-overlapping clock generator
will be further explained in the next section. The reference generator will be explained in the
voltage reference architecture section.
Figure 2.12 – Block Diagram of the 8-Bit 1.5-bit/stage Pipelined ADC [7]
13
How the digital error correction is done is important in understanding 1.5-bit/stage pipelined
ADCs. The concept for the error correction circuit is illustrated in Figure 2.13. In this figure, the
14 encoded comparator bits from the pipelined stages are added together based on their relative
weights to create the final ADC output code. The current stage’s least significant bit (LSB) is
added to the next stage’s most significant bit (MSB), since the value of the bits from the next
stage are only worth half as much as the bits from the current stage in a 1.5-bit/stage pipelined
ADC. The exceptions to this rule would be the MSB in the first stage and the LSB in the last
stage since there is nothing more to add at either end.
MSB LSB
Stage 1
MSB LSB
Stage 2
MSB LSB
Stage 3
MSB LSB
Stage 4
MSB LSB
Stage 5
MSB LSB
Stage 6
MSB LSB
B7
B6
B5
B4
B3
B2
B1
B0
Stage 7
Digital
Output
Figure 2.13 – Digital Error Correction Concept for an 8-bit, 1.5-bit/stage Pipelined ADC
14
2.1.2 Residue Stage Architecture
In analog signal processing circuits which use discrete components, a combination of resistors
and capacitors are used to determine the time constant of amplifiers, active filters, and other
complex circuits [8]. In CMOS integrated circuit technology, building large resistors consumes
significant silicon area. Also, realizing precise time constants become difficult as the values of
resistors and capacitors do not track each other with process and temperature variations. These
issues can be overcome by adopting switched capacitor techniques for analog signal processing
on CMOS integrated circuits.
By using switched capacitor techniques, large resistors can be realized with switches and
capacitors. The ratio of the capacitors is used to accurately determine the gain constants in a
switched capacitor circuit. This eliminates the need to precisely control capacitor and resistor
values. Switches in a switched capacitor circuit are driven by non-overlapping clocks to make
sure that only the desired switches are on at the same time. There are several issues which can
decide the precision of switched capacitor circuits, such as channel charge injection, clock
feedthrough, and kT/C noise. To implement a resistor using switched capacitor techniques
requires two switches and a capacitor, as shown in Figure 2.14. The switches can sometimes be
implemented using simple NMOS transistors as shown in this figure, although full CMOS
transmission gates consisting of an NMOS FET in parallel with a PMOS FET may be needed for
large signal swings. The switches are driven by non-overlapping clocks, Ф1 and Ф2, as shown in
Figure 2.14. The importance of using non-overlapping clocks is explained later. During the clock
phase when Ф1 is high and Ф2 is low, capacitor C is charged to the voltage V1. When Ф1 is low
and Ф2 is high, C is charged to voltage V2.
15
The charge transferred from V1 to V2 due to the switching action during each clock cycle is
given by:
Q = C ∙ (V1 − V2)
Equation 2.3
Figure 2.14 – Resistor Implemented Using Switches and a Capacitor
Thus, the average current (Iavg) flowing from V1 to V2 is given by Equation 2.4, where FS is the
frequency of the non-overlapping clock.
Iavg 
Q
 Q  FS
t
Equation 2.4
Φ1
Φ2
T
Figure 2.15 – Non-overlapping Clocks
16
Substituting Equation 2.3 into Equation 2.4, we obtain:
Iavg = C ∙ (V1 − V2) ∙ FS
Equation 2.5
From Equation 2.5, we can see that the average current through the switched capacitor resistor
(Iavg) is proportional to the voltage across it. Thus, the equivalent “switched capacitor resistor” is:
R eq 
1
 FS  C 
Equation 2.6
Therefore, Equation 2.6 shows that by using switched capacitor techniques, large value resistors
can be built using relatively small amounts of silicon area just by choosing the correct capacitor
value [8]. For example, a switched capacitor resistor equivalent to 1MΩ can be built using a
capacitor value of 0.1pF and a non-overlapping clock frequency of 10MHz.
Figure 2.16a shows the implementation of a discrete time integrator using switched capacitor
techniques. When Ф1 = high and Ф2 = low, C1 charges to a value of Q = C1*V in and then
transfers that charge to C2 when Ф1 = low and Ф2 = high. For example, if V in is constant, the
output changes by -Vin*(C1/C2) every clock period, as shown in Figure 2.16b [7].
Figure 2.16 – (a) Switched Capacitor Discrete-time Integrator
(b) The Circuit Response from a Constant Input Voltage [8]
17
The final value of Vout in Figure 2.16a after every clock cycle can be written as [8]:
1
(Where TS =
)
FS
Vout  (kTS)  Vout [(k -1)TS] - Vin [(k -1)TS] 
C1
C2
Equation 2.7
Taking the Z transform of Equation 2.7 yields:
 C1  1
Vout (z) = ( z 1 )Vout - 
   z   Vin  z 
 C2 
Equation 2.8
Solving for the transfer function of the switched capacitor discrete-time integrator:
H(z) =
Vout
 C1  1
 

Vin
 C2  z  1
Equation 2.9
From Equation 2.9, we can conclude that the transfer function for this discrete-time integrator
implemented using switched capacitors has a gain equal to the ratio of two capacitances, C1 and
C2. This illustrates how a transfer function can be precisely implemented in an integrated circuit
using switched capacitor techniques.
18
Residue stages form the core of pipelined ADCs, as explained earlier. The residue stage is
implemented using switched capacitor circuits because of the accurate gains set by the ratio of the
capacitors, as was just illustrated. Figure 2.17 below shows the 1.5-bit/stage switched capacitor
residue stage used in the ADC2 team's design. This residue stage consists of a high gain
operational amplifier, two sampling capacitors (Cs), two feedback capacitors (Cf), and several
switches.
VinP
VrefP
X
VrefN
Y
VoutP
Ф1
Ф1
Ф2
ViCM
Cs
Ф1'
Cf
Cs
Y
VrefP
+
-
-
+
Ф1'
Z
X
Cf
Ф1
Ф1
Ф1
Ф1'
ViCM
Ф2
VrefN
VoutN
VinN
Figure 2.17 – Switched Capacitor Residue Stage Used by the ADC2 Team
All the switches are driven by non-overlapping clock signals. The sampling and feedback
capacitors are equal in size to achieve a gain of 2. The signal path was designed to be fully
differential to maximize the common-mode rejection ratio (CMRR), the power supply rejection
ratio (PSRR), and to minimize even order harmonic distortion [6]. The digital signals X, Y, and Z
are based on the comparator output bits from the sub-ADC for the stage, and control the operation
of the sub-DAC used to subtract +Vref, -Vref or zero from 2*Vin to form the residue signal. The
19
sub-DAC consists of the switches controlled by X, Y, Z and the differential reference voltage
Vref = VrefP – VrefN. The switches connect the sampling capacitors to the positive reference
voltage (VrefP), negative reference voltage (VrefN), or no reference voltage, to subtract either
+Vref, -Vref, or zero depending on the values of the comparator output bits from the sub-ADC.
The switched capacitor residue stage requires four non-overlapping clock signals. These clocks
are generated by a non-overlapping clock generator circuit which uses a single reference clock as
an input. The non-overlapping clock generator produces Ф1 and Ф2, along with advanced
versions of these 2 clocks which change slightly earlier in time, Ф1’ and Ф2’ respectively, as
shown in Figure 2.18 below. All the clocks shown are active high. The lag time, tlag, is the time
difference between the rising edge of the advanced clock Ф1’ and the rising edge of the nonadvanced version of the same clock, Ф1. The non-overlap time, or tnov, is the time difference
between the falling edge of Ф1 and the rising edge of Ф2.
20
tlag
tnov
Φ1
Φ1'
Φ2
Φ2'
Figure 2.18 – Non-overlapping Clock Signals
The advanced clock signals, Ф1’ and Ф2’, are used to mitigate the effects of channel charge
injection. Channel charge injection is the flow of charge from the drain and source of a MOS
switch into the signal path which happens when a MOSFET is turned off. This charge injection
can cause nonlinear errors in the signal path of an ADC which degrades the ADC performance.
Fortunately, these errors can be minimized through the proper use of advanced clocks in the
switched capacitor residue stage.
The two single-ended signals VinP and VinN in Figure 2.19 form the differential input signal to
the residue stage, VinP - VinN. These signals come from the output of the previous stage. When
Ф1 is high and Ф2 is low, the inputs of the operational amplifier are shorted together and
connected to the input common-mode voltage. This is done to bias the inputs of the opamp during
the sampling phase. An advanced version of Ф1 (Ф1') is used to control the switches at the
opamp’s inputs in order to reduce signal-dependent charge injection in the signal path. On the
21
falling edge of Ф1', the top plates of Cs and Cf are open circuited. Because Cs and Cf have an
open circuit on their top plates the charge stored on these capacitors cannot be changed after Ф1'
goes low. Therefore the signal-dependent charge injected later by the input switches controlled by
Ф1 does not cause an error in the charge stored on Cs and Cf.
VinP
VoutP
Ф1
Ф2
Ф1
Cs
Cf
ViCM
Ф1'
Ф1'
Cf
Cs
Ф1
Ф1
+
-
-
+
Ф1
Ф1'
ViCM
Ф2
VoutN
VinN
Figure 2.19 – Sampling Phase of Reside Stage
When Ф1 goes high, the top Cs and Cf capacitors are charged to VinP and the bottom Cs and Cf
capacitors are charged to VinN, as shown in Figure 2.19. This is known as the sampling phase.
Also when Ф1 is high the outputs of the operational amplifier are shorted together. This is to
avoid having the output voltage of the operational amplifier swing to a supply voltage, which
could occur due to the input offset voltage while the opamp is operating in an open loop
configuration.
22
At the end of the sampling phase, the falling edge of Ф1’ samples the input voltage onto the Cs
and Cf capacitors and simultaneously causes the comparators in the sub-ADC to begin their
comparisons. The sub-ADC is composed of two comparators that compare the input voltage to
two voltage references, +Vref/4 and –Vref/4. These comparisons must be done during the
non-overlap time between clock phases, since the comparator decisions are used immediately
during the following settle and hold phase to control the operation of the sub-DAC. The
non-overlap time (the time between the falling edge of Ф1’ and the rising edge of Ф2’) defines
the amount of time the comparators have to make their decisions [7]. In a 1.5-bit pipelined ADC,
the sub-ADC in each stage produces 2 output bits. These bits are used both by the decode and
error correction logic to help determine the final ADC output code, and by the sub-DAC to
choose the correct reference voltage for the next phase of operation, the settle and hold phase.
When Ф2 goes high, the feedback capacitors are connected to the outputs of the operational
amplifier. The sampling capacitors are connected to the sub-DAC outputs, in order to subtract the
appropriate reference voltage from the residue based on the comparator bits from the sub-ADC.
This is known as the settle and hold phase. Figure 2.20 shows the settle and hold phase for the
residue stage. The different output conditions are shown in Table 2.3 below.
Input Condition
Vin ≤ -(Vref/4)
-(Vref/4) < Vin < +(Vref/4)
Vin ≥ +(Vref/4)
Resulting VOUT
Ideal VOUT
 Cs 
 Cs 
Vout  1 
 Vin    Vref
 Cf 
 Cf 
 Cs 
Vout  1 
 Vin
 Cf 
 Cs 
 Cs 
Vout  1 
 Vin    Vref
 Cf 
 Cf 
Vout  2Vin  Vref
Vout  2Vin
Vout  2Vin  Vref
Table 2.3 – 1.5-bit/stage Transfer Function Equations
23
VrefP
VrefN
X
VoutP
Ф1
Y
Ф1
Ф2
ViCM
Cs
Ф1'
Cf
+
-
-
+
Ф1'
Z
Cs
Y
Ф1
X
VrefP
Cf
Ф1
Ф1'
ViCM
Ф1
Ф2
VrefN
VoutN
Figure 2.20 – Settle and Hold Phase for the Residue Stage
To understand the operation of this circuit better, consider the simplified circuit shown in
Figure 2.21. At the moment before the beginning of the settle and hold phase, Cs and Cf are
charged to Vin as shown. Using Kirchhoff’s Voltage Law (KVL), Vout is found in Equations
2.10 and 2.11.
-
+
Vin
+Vref
Vin
+
Cf
V+
+
Vout
Cs
-
Figure 2.21 – Single-ended Settle and Hold phase with +Vref as the Sub-DAC Output
Using KVL in Figure 2.21 at V+ results in:
 Vref
 Vin  V+  sCs    Vout  Vin  V+   sCf   0
Equation 2.10
24
Solving for Vout with V+ = 0 due to the virtual ground provided by the opamp yields:
 C +Cf
Vout  Vin  s
 Cf

 Cs 
   +Vref   


 Cf 
Equation 2.11
The solution for Vout reveals some important details about the circuit operation during the settle
and hold phase. First, the charge originally stored on Cs due to Vin is transferred to Cf. This
causes the input voltage to be multiplied by a factor of (Cs + Cf)/Cf. If Cs = Cf, the gain factor
is 2. Second, the output voltage of the sub-DAC is multiplied by a factor of Cs/Cf, or 1, and is
subtracted. This yields a final output voltage of Vout = 2*Vin – Vref, as desired. It is important to
note that Cs and Cf need to match each other accurately since the transfer function of the residue
amplifier, and therefore the accuracy of the pipelined ADC depends greatly on this capacitor
matching.
So far, the explanation of the settle and hold phase has only covered 2 out of the 3 conditions for
the sub-DAC, when a voltage is applied to Cs. The third condition shorts the inputs of the two Cs
capacitors together. When shorted, the signal charge on the two Cs capacitors cancel.
The combined charge for the two Cs capacitors is given by Qtotal = Q1 + Q2 =
VinP·Cs1 + VinN·Cs2 = 0 (since Cs1 = Cs2 and VinN = -VinP). Therefore Vout = 2Vin, with
zero volts subtracted due to the sub-DAC. This method of shorting the inputs of the two Cs
capacitors together allows the previous stage to set the common-mode voltage for VinP and
VinN, which eliminates another source of error.
25
In the 1.5-bit/stage pipeline ADC architecture, each residue stage produces two output bits
instead of the one bit produced for a 1-bit/stage architecture. Out of the possible four
combinations of two output bits, only 3 combinations (00, 01, 10) are used. Thus, a 1.5-bit/stage
architecture has 0.5 LSB of redundancy in each stage when compared to a 1-bit/stage architecture
which has no redundancy. To produce this extra 0.5 LSB of resolution, an extra comparator is
added to the 1-bit/stage sub-ADC block. The extra redundancy of the 1.5-bit/stage architecture
eases the accuracy requirements for the comparators in the sub-ADC by using a simple digital
error correction circuit [9]. This error correction allows much larger comparator offset voltages
when compared to a 1-bit/stage pipelined ADC architecture, allowing the use of smaller
comparators which use less power.
2.1.3 Reference Generator Architecture
In this section the architecture used for the voltage and current reference generator is discussed.
The voltages and currents created by this block are used by the residue amplifier and comparators
in each stage of the pipelined ADC, as previously discussed. The reference generator block
designed by the ADC2 team is shown in Figure 2.22. Using a bandgap reference voltage provided
from outside the chip, five reference voltages are generated. Vrefp, Vrefn, and Vocm are used by
the residue amplifiers and Vrefpc and Vrefnc are used by the comparators. The reference
generator also creates 22 bias currents needed for the opamps and comparators used in this ADC.
Twenty-one of these bias currents are used on-chip while one is provided to allow for off-chip
measurements during testing. The value of the bias currents provided to the residue stage opamps
can be varied during testing using a 3-bit current DAC, controlled by the 3 OA_CNTL bits. A
second 3-bit current DAC controlled by the 3 CMP_CNTL bits provides the same adjustment
capability for the bias currents used by the comparators. The descriptions and nominal values for
the voltage and current references are given in Table 2.4.
26
VDD
VBandgap
VREFP
VREF
VREFPC
VOCM
VDD
VREFNC
4
VREFN
IBIAS_VREF
OA_CNTL
CMP_CNTL
3
IREF
3
7
7
3
PD
R_EXT
VSS
IBIAS_OA
IBIAS_CMP
IBIAS_EXTRA
IBIAS_EXT
VSS
Reference Generator
Figure 2.22 – Reference Generator Block Diagram
Name
Vbandgap (off-chip)
Vrefp
Vrefpc
Vocm
Vrefnc
Vrefn
OA_CNTL[2:0]
CMP_CNTL[2:0]
PD
REXT (off-chip)
IBIAS_VREF[3:0]
IBIAS_OA[6:0]
IBIAS_CMP[6:0]
Description
Bandgap Reference Voltage (provided offchip)
Positive Residue Amplifier Reference
Voltage
Positive Comparator Reference Voltage
Common-Mode Output Reference Voltage
Negative Comparator Reference Voltage
Negative Residue Amplifier Reference
Voltage
Opamp Bias Current Control Bits
Comparator Bias Current Control Bits
Power Down Control Bit
External Resistor used for Current
Generation
Reference Generator Bias Currents
Opamp Bias Currents (25µA -175µA)
Comparator Bias Currents (25µA -175µA)
Target Value
1.262V
3.000V
2.625V
2.500V
2.375V
2.000V
0V or 5V
0V or 5V
0V or 5V
12KΩ
100µA
100µA
100µA
27
IBIAS_EXTRA[2:0]
IBIAS_EXT
VDD
VSS
Spare Bias Currents
Bias Current sent off-chip for measurement
Positive Power Supply Voltage
Negative Power Supply Voltage
100µA
100µA
5V
0V
Table 2.4 – Target Reference Generator Values
The schematic for the voltage reference circuit is shown in Figure 2.23 [10]. This circuit converts
a bandgap reference voltage provided from off-chip to an on-chip reference current using an
opamp and an on-chip resistor. This current is then mirrored and filtered to remove noise. The
output from the current mirror flows into a resistor string which converts the reference current
back into a reference voltage. This method is a technique commonly used in industry to allow
references to be sent long distances across a chip, without errors due to device mismatches and
differences in ground potential. Any desired reference voltage value can be created by scaling the
resistor and current mirror sizes, and variations in the on-chip resistor values cancel out as long as
the resistors match well [12]. The values of the resistors determine the reference voltages created
at each node, while bypass capacitors reduce voltage variations. Buffer amplifiers are needed for
the positive, negative, and output common-mode reference voltages to supply the current drawn
from these references. The Vrefpc and Vrefpn reference voltages are used only by comparators,
which are only small capacitive loads, and therefore do not require a buffer amplifier since no DC
current is drawn from these references.
28
VDD
Buffer
amplifiers
RC
Filters
Vrefp
Vrefpc
1.2V
+
Vocm
Bypass
Capacitors
-
Vrefnc
On-chip
resistor
Vrefn
VSS
VSS
Figure 2.23 – Voltage Reference Circuit [10]
29
The basic circuit for the reference voltage buffer is shown in Figure 2.24. This type of circuit uses
a “replica bias” scheme, and is commonly used in most pipelined ADCs and many other
integrated circuits in production [11]. In this circuit, there is a buffer opamp, four transistors in
two different bias legs, and an output bypass capacitor.
Vref
(resistor string)
+
M1
Vdd
M2
Buffer
Opamp
Vref
M3
Vbias
M4
Cbypass
Vss
Figure 2.24 – Reference Voltage Buffer Circuit
The output voltage is created using an opamp in feedback to set the voltage at the source of M1
equal to the input voltage, Vref. As long as good matching can be achieved between M1 and M2,
as well as between M3 and M4, then the source voltage of M2 is equal to the source voltage of
M1 and therefore Vout = Vref. In this circuit the bias leg formed by M1 and M3 creates a
“replica” of the main output leg formed by M2 and M4. This prevents the opamp from being
loaded by the large bypass capacitance which could cause its response to become unstable.
M2 and M4 can also be scaled up to be much bigger than M1 and M3 to obtain the low output
resistance needed for this buffer.
30
When the residue stage capacitors connect to the reference buffer outputs and draw current, Vref
must not vary more than a small amount or else signal-dependent distortion will reduce ADC
performance. (Further discussion about ADC performance measures is provided in section 2.2.)
Ideally, the reference voltage would never change even as the residue stage capacitors are
switched to connect to it. However, this is unrealistic due to the high costs of using a large
amount of chip area for the output transistors and bypass capacitor. Therefore the variations in the
reference voltage must be managed using reasonably sized devices.
The ADC2 team designed the reference voltage generator to minimize variations in the reference
voltage outputs. As previously mentioned, these variations in voltage come from the connection
of the reference buffer outputs to the residue stage capacitors. Since exactly when each residue
stage connects to the reference voltages depends on the input signal, any significant variation in
the reference voltages due to this will lead to signal-dependent distortion. This appears as glitches
in the reference voltage outputs because of the rapid transfer of charge between the reference
buffers and the residue stage capacitors. To keep these glitches small, the ADC2 design used a
large bypass capacitor on each reference buffer output [10]. In addition, when the reference buffer
connects to the residue stage capacitors, an average current is drawn from the reference buffer.
Depending on the output resistance of the reference buffer and the signal-dependent value of this
average current, a voltage error can be calculated as given in Equation 2.12.
Verror  Iaverage  R out
Equation 2.12
31
This error was kept small in the ADC2 design by keeping Rout small, through the use of large
FETs in the output buffers having large bias currents [10]. The large area and bias current of the
output buffer FETs make the gm of these transistors large, and therefore R out 
1
and Verror
gm
small.
2.2 ADC Performance Measures
All analog-to-digital converters are characterized by several performance measures, which are
discussed in this chapter in detail. In this section, the ideal transfer curve for an ADC will be
discussed, as well as quantization error, differential nonlinearity (DNL), integral nonlinearity
(INL), signal-to-noise plus distortion ratio (SNDR) and effective number of bits (ENOB).
Understanding the ideal specifications for an ADC is an important first step in determining ADC
performance. A key specification is the resolution, which is the number of distinct levels a data
converter can represent [12]. The resolution of an ADC is based upon the number of output bits it
has. An N-bit ADC can represent 2N different analog input signal levels in its digital output code.
The smallest step from one level to the next represents the size of one least significant bit (LSB).
The LSB value, VLSB is the ideal input voltage spacing between two adjacent output codes, and is
the smallest input voltage that can be represented in the ADC output code.
VLSB for a full-scale input voltage range equal to VFS is given by:
V
VLSB  FS
2N
Equation 2.13
Figure 2.25 shows the ideal input/output transfer curve for a 2-bit ADC. The dotted line
represents the analog input, and the solid line represents the digital output. It is important to note
that the entire ADC transfer curve is shifted left by 1/2 VLSB, so that the first step occurs at
32
1/2 VLSB instead of 1 VLSB. This shift in the transfer curve is used so that the output code first
underestimates and then overestimates the input voltage. This reduces the peak “quantization
error” from 1 LSB to ± 1/2 LSB. Quantization error refers to the unavoidable error which comes
from representing an infinite number of possible analog input voltages with a finite number of
digital output codes. This shift in the transfer curve is equivalent to having the ADC round off its
output code to the nearest value.
Figure 2.25 – Ideal Input/Output Transfer Curve for a 2-bit ADC [13]
33
2.2.1 DNL and INL
Determining an ADC’s accuracy is essential for evaluating its performance. Accuracy is the
extent to which the actual measured transfer curve agrees with the ADC’s ideal transfer curve.
Two different measures of accuracy are typically used, absolute and relative accuracy. Absolute
accuracy includes all errors in the ADC transfer curve while relative accuracy only includes
linearity errors after the linear offset and gain errors are removed.
Gain error is the difference between the slopes of the actual and ideal transfer curves, and offset
error is the shift of the actual transfer curve compared to the ideal transfer curve [12]. A graphical
representation of offset and gain errors is shown in Figure 2.26 [13].
Figure 2.26 – Offset and Gain Errors for a 2-bit ADC [13]
34
Two more measures which are important in evaluating ADC performance are differential
non-linearity (DNL) and integral non-linearity (INL). DNL is the difference between each step
size and the ideal step size of 1LSB [2]. DNL errors are evaluated for all codes and are used
together with INL to measure the linearity of the ADC transfer curve. INL is the difference
between the actual transfer curve and a straight line, after offset and gain errors are removed [12].
Figure 2.27 below shows the DNL and INL relationship for an ADC. The dotted line represents
the ideal transfer curve after gain and offset errors are removed by connecting the end points of
the actual transfer curve with a straight line.
111
110
Digital Output
DNL = actual step width - 1LSB
101
100
011
INL
010
001
000
Analog Input
Figure 2.27 – DNL and INL Illustrated for an ADC
35
Common to all ADCs is quantization error. Quantization error is the difference between the
actual analog input voltage and the ADC output code which represents it. Figure 2.28 shows the
quantization error for a ramped input. Quantization error cannot be avoided since an ADC must
represent an infinite number of input voltages with a finite number of digital output codes.
Quantization error can be thought of as noise in the converter which limits performance, even for
an ideal ADC.
Figure 2.28 – Quantization Error [13]
Other sources of error in ADCs occur due to the offset voltages of comparators and opamps,
mismatches in capacitors and/or resistors, low opamp gain, thermal noise, clock jitter, reference
noise, and other non-idealities which occur during manufacturing. The types of errors
encountered can differ greatly between different ADC architectures and even between similar
architectures with seemingly minor differences in design.
36
2.2.2 ENOB, SNR, and SNDR
ADC characterization is also typically done using Fast Fourier Transform (FFT) analysis. An FFT
is a computationally efficient algorithm that allows the frequency spectrum of the ADC output to
be analyzed. An analog sine wave is input to the ADC and an FFT of the digital output is
computed. The output spectrum is then analyzed to reveal ADC performance. Since a linear
system can only output the same frequencies that are contained in its input signal, any tones
observed in the ADC output spectrum other than the input sine wave frequency are the result of
distortion. The noise floor is the result of quantization noise, which appears as white noise and so
is approximately the same at all frequencies in the FFT.
An important ADC performance measure is the signal-to-noise ratio (SNR). Figure 2.29 shows an
example FFT that illustrates this. SNR is the ratio of the power in the desired signal to the total
power in the undesired noise. The SNR for an N-bit ADC can be calculated in decibels as shown
in Equations 2.14 and 2.15. Larger SNR values are preferred, but require more bits in the ADC.
Because quantization noise is fundamental to all ADCs, an ideal equation for SNR which only
takes quantization noise into account is useful, and is given in Equation 2.15.
Figure 2.29 – FFT of an N-bit ADC with a Sampling Frequency Fs [14]
37
Signal to Noise Ratio in decibels is given by:
 Psignal 
 Vsignal 
SNR dB  10  log 
 20  log 


 P

 V
noise 
noise 


Equation 2.14
Ideal SNRdB  6.02N  1.763
Equation 2.15
FFT analysis also reveals the harmonic distortion of the ADC. The sum of power in all the
harmonic distortion terms divided by the power in the fundamental is called the total harmonic
distortion (THD). Figure 2.30 shows a general example of harmonic distortion and Equation 2.16
shows the solution for the total harmonic distortion.
Figure 2.30 – An FFT Showing Harmonic Distortion [15]
38
Total Harmonic Distortion, where V2 through Vn are the harmonic distortion terms, and V1 is the
fundamental is given by:
V22  V32  ...Vn2
THD 
V1
Equation 2.16
The ratio of the input signal to the sum of the noise and harmonic terms is call the signal-to-noise
and distortion ratio, or SINAD. This is also often called the SNDR, or signal-to-noise-plusdistortion ratio. Once SINAD is found, the effective number of bits (ENOB) for the ADC can be
calculated. As shown in Equation 2.18, ENOB is directly related to the noise and distortion of the
ADC.
Signal to Noise and Distortion Ratio is given by:
SINAD 
Psignal
 PHarmonics   PNoise
Equation 2.17
Effective Number of Bits is given by:
ENOB 
SINADdB  1.76
6.02
Equation 2.18
ENOB can be thought of as the number of bits an ideal data converter would have if it had the
same SINAD. The ENOB performance metric is important because it shows an ADC’s accuracy
and allows for easy comparison between different ADCs.
39
Chapter 3
REFERENCE VOLTAGE GENERATOR MODELS
3.1 Original Slow Reference Generator Model
The main goal for this project was to verify a new voltage reference architecture by use of a
model. This new voltage reference architecture has the potential to reduce the silicon area and
power consumption of the voltage references compared to the previously fabricated ADC2
design. Therefore, the design of the previous voltage reference circuit has been carefully
examined. According to the specifications for the original design, the reference voltages provided
to the residue amplifiers could not vary by more than 4mV [10]. A maximum error of 3mV was
allowed for the reference voltage generator, and 1mV was allowed for the drop in voltage as
current flows through the resistance of the wires used to connect the reference generator to the
residue stages. In order to achieve this, the reference generator used output buffers with large
bypass capacitances on their outputs to minimize voltage variations as the residue stages connect
and disconnect. These buffers were also designed to have small output resistances to reduce
voltage errors due to the average current drawn from the buffers. The calculation for the
maximum voltage error that was used for the original design is shown in Equation 3.3. A bypass
capacitance of 250pF and an output resistance of 14Ω was chosen for this design [10]. Note that
in Equation 3.1 the maximum charge is supplied by the positive reference when the input voltage
that connects to Vrefp is Vrefpc. Similarly, the maximum charge is supplied by the negative
reference when the input voltage that connects to Vrefn is Vrefnc. A simplified circuit used to
model this is shown in Figure 3.1.
40
Qmax (when 3 residue stages connect to the same voltage reference) is given by:

Qmax   Cs  Vref  Vin
 3  Cs  Vrefp  Vrefpc
max

Equation 3.1
Qmax  3  0.5pF   3V  2.625V   0.5625pC
Equation 3.2
Which causes a maximum instantaneous voltage error of:
Verror  max  
Qmax
0.5625pC

 2.25mV
Cbypass
250pF
Equation 3.3
Φ1
Vin
Cs
Φ2
Vref
Figure 3.1 – Simplified Circuit Showing the Switches Between Vin, Vref, and One of the Residue
Amplifier Capacitors
3.2 Fast Settling Reference Generator Model
Instead of designing the voltage references to never vary outside of a specified limit, a new
architecture for the voltage references is presented here. To understand the operation of this new
architecture, first note that connections between the sampling capacitors in the residue amplifiers
and the voltage references are made at discrete times by the switched capacitor residue amplifiers.
More specifically, the connection between the sampling capacitors in half of the residue
amplifiers and the voltage references happen every 1/2 clock cycle. These connections are made
during the settling phase for each residue amplifier, which is when Ф1 is high for half (3) of the
residue amplifiers, and when Ф2 is high for the other half (3) of the residue amplifiers. Because
41
the voltage references only need to be accurate at discrete times during the data conversion
process, the output buffer can be redesigned so that it can recover to its required value before the
end of the clock phase. This recovery speed depends on the output resistance and bypass
capacitance of the voltage reference, and the amount of time that the residue amplifier is
connected to the voltage reference. For the 50ns clock that was used in the original pipelined
ADC, this is 20ns after the non-overlap time between clock phases is taken into account.
Calculations for the voltage references including this time dependence for the new architecture
are shown in Equations 3.4 and 3.5. These equations were solved assuming an immediate voltage
drop resulting from the connection made to the residue amplifiers and a recovery based on an RC
time constant where R is the output resistance of the output buffer and C is the bypass
capacitance of the output buffer. Note that the capacitances in the residue stages and the
resistance of the switches used to connect these capacitors is neglected here to simplify the
analysis. This is a good approximation as long as Cbypass is >> Cs.
The equation for Vref including the variation during recovery is given by:
Vref  Vref_ideal  Vdrop  e

t
Rout Cbypass
Equation 3.4
The error in Vref during a recovery period is given by:
Vref  Vdrop  e

t
Rout Cbypass
Equation 3.5
42
3.3 Tortoise vs. Hare Model Comparison
The new architecture presented in this report represents a fundamental change in the way the
reference buffers are designed. The original design used what is often called the "tortoise"
approach, meaning that the reference voltages were not allowed to change more than a small
amount during operation. The new design uses the "hare" approach, meaning that the reference
voltages are allowed to change, as long as they return to their original values quickly enough to
avoid signal dependent errors in the ADC output code.
Solving for ∆Vref using the values from the original design:
Vref  2.25mV  e

20ns
14Ω250pF  7.4μV
Equation 3.6
This shows that, for the original design, the change in Vref is only 7.4µV, which is less than
1/1000th of an LSB for the worst case! This shows that the voltage reference barely changes in
the original design, as was intended. If ∆Vref is kept at 3mV (using the same specifications as the
original design) and Cbypass is cut in half to 125pF, the value needed for Rout using the new
hare approach can be found using Equation 3.5, as shown in Equation 3.7.
R out 
t
 Vdrop
Cbypass  ln 
 Vref




20ns
 394.6Ω
 4.5mV 
125pF  ln 

 3mV 
Equation 3.7
Note that in this calculation Vdrop doubles since Cbypass was cut in half (see Equation 3.2). As
shown in Equation 3.7, the value needed for Rout increased by a factor of 28 compared to the
original design value of 14 Ohms, which also reduces the power and area needed for the reference
buffers by a factor of 28. Although decreasing the value of Cbypass increases the error voltage
43
temporarily, it also decreases the time needed for the voltage reference to return to its original
value. By more closely investigating and optimizing this behavior, the power and area needed for
the voltage references can be dramatically reduced. Also, because the area used by the voltage
reference represents a large fraction of the total area needed for the pipelined ADC, the hare
approach can save a large amount of chip area.
44
Chapter 4
CHARGE CANCELLATION
4.1 Charge Cancellation
Due to variations in the input signal, the amount of charge transferred, or "kicked back" from the
residue amplifiers to the reference voltage buffers also varies. For pipelined ADC designs that
focus on minimizing the amount of power and area used by the reference voltage circuits, the
resultant noise from this kickback charge can become the dominant factor contributing to the loss
of ENOB in a pipelined ADC. A new method of cancelling the signal-dependent part of this noise
charge was investigated as part of this project [11], as reported here.
To implement this new technique for cancelling the signal dependent portion of the charge kicked
back into the reference buffers from the residue amplifiers, a set of duplicate residue amplifiers
are needed to deliver a complimentary amount of kickback charge to each reference buffer. The
signal dependent portion of this complementary charge needs to be equal in magnitude and
opposite in sign compared to the signal-dependent portion of the original kickback charge. From
a differential signal point of view, these complementary charges cancel each other out, which is
where the name charge cancellation originates. From a single-ended point of view, this appears as
if a capacitor twice as big was constantly switching between reference buffers and the
common-mode output voltage. While this doesn't eliminate the glitch seen at the outputs of the
reference voltage buffers, it does make the noise charge kicked back constant, providing glitches
that are signal independent. Since this error source no longer varies with the input signal,
distortion in the pipelined ADC is greatly reduced.
45
The duplicate residue amplifiers are exact copies of the original residue amplifiers except that the
reference voltage inputs to the DACs are reversed. These duplicate residue amplifiers are referred
to as replica residue amplifiers. Figure 4.1 shows how the replica residue amplifiers were
implemented. By reversing the reference voltage inputs to the replica residue amplifiers, the
charge kicked back to each voltage reference will be the sum of the charge from the input
voltages Vinp and Vinn on the Cs capacitors. Because of the differential nature of the input
signal, the sum of these charges will always have the same value which eliminates the
signal-dependent portion of the noise charge kicked back into the reference voltage buffers.
Vinp
Residue Amplifier
Vrefp Vrefn
Cs1
DAC
Cf1
Cs2
Vrefn Vrefp
References
Reversed
Vop
-
+
Von
Vinn
Vinp
Cs3
Replica Residue Amplifier
Cf3
Cs4
Vrefp Vrefn
-
Cf2
Vrefn Vrefp
Replica
DAC
+
+
-
-
+
Cf4
Vinn
Figure 4.1 – Dual Residue Amplifier Architecture with Reversed DAC Inputs
46
Vinp and Vinn for the replica residue amplifiers come from the outputs of the previous residue
stage. Figure 4.2 shows a block diagram of how the replica residue amplifiers connect to the main
residue stages.
Vinp
Vinn
Vinp1
Vinp2
Vinn1
Sample /
Hold
Vinn2
Residue
Stage 1
Vrefp
Vrefp
Vrefn
Vrefn
Vinp1
Vinn1
Residue
Stage 2
Vinp2
Vinn2
Replica
Residue
Amp 1
Vrefn
Vrefn
Vrefp
Vrefp
Replica
Residue
Amp 2
Figure 4.2 – Block Diagram Showing the Replica and Main Pipelined ADC Stages
To better understand how this signal-dependent charge cancellation works, an understanding of
how the DAC functions in a residue stage is needed. Table 4.1 shows which reference voltage
each Cs capacitor will connect to, depending on the input voltage, Vin. The columns in Table 4.1
refer to the Cs capacitors from Figure 4.1.
Original
Replica
Vin
Cs1
Cs2
Cs3
Cs4
Vin ≥ Vref/4
Vrefp
No Vref
connection
Vrefn
Vrefn
No Vref
connection
Vrefp
Vrefn
No Vref
connection
Vrefp
Vrefp
No Vref
connection
Vrefn
+Vref/4 > Vin > -Vref/4
Vin ≤ -Vref/4
Table 4.1 – Input Vref Connection Table
47
For charge cancelling pipelined ADCs, a sampling capacitor from the original residue amplifier
and a sampling capacitor from the replica residue amplifier will connect to each reference
voltage. These sampling capacitors from the original and replica residue amplifiers are charged to
opposite input voltages, Vinp and Vinn, respectively (or vice versa). Since the two capacitors
which connect to each reference voltage are charged to signal voltages which are equal in
magnitude and opposite in sign, their differential signal voltage cancels. For example, if the
positive reference voltage, Vrefp, connects to the Cs capacitor charged to Vinn from the main
residue amplifier it will also connect to the Cs capacitor charged to Vinp from the replica residue
amplifier. Likewise, if the negative reference voltage, Vrefn, connects to the Cs capacitor charged
to Vinp from the main residue amplifier it will also connect to the Cs capacitor charged to Vinn
from the replica residue amplifier. Equations 4.1 and 4.2 show the total amount of charge
transferred to each reference voltage from both the main and replica residue amplifiers. ∆V is the
difference between each input voltage and the reference voltage.
QTotal   V  Cs  Vr  Csr   Cs   V  Vr 
Equation 4.1
Which yields Equation 4.2:
QTotal   Cs   Vrefp  Vinp    Vrefp  Vinn   Cs  2 Vrefp  Vcm
As this shows, when the charge cancellation technique is applied the same amount of charge will
always be kicked back to the voltage references irrespective of the input signal voltage. This is
because the term (∆V + ∆Vr) in Equation 4.1 will always sum up to the same value,
2(Vrefp - Vcm). This eliminates the signal-dependent portion of the charge kicked back, which
will greatly reduce distortion in the ADC due to changes in the reference voltages. Note that the
use of the charge cancellation circuit actually increases the total amount of charge kicked back
48
onto the reference voltage, thereby also increasing the glitch seen on the reference voltage.
However, since this glitch is signal-independent, this does not cause distortion in the ADC the
way that the smaller signal-dependent glitch in the original circuit did. It is also important to note
that there is no kickback charge when +Vref/4 > Vin > -Vref/4. This means that the amount of
charge kicked back still has some signal dependence, which will limit the effectiveness of this
technique when applied to a 1.5-bit/stage pipeline architecture. Note that this limitation isn't
present in a 1-bit/stage pipeline architecture, but that architecture is much more sensitive to
comparator offset voltages, as previously discussed. Table 4.2 shows the relation of the
differential input signal voltage, Vin, to the kickback on each voltage reference. In Table 4.2, Csr
refers to the Cs capacitor in the replica residue amplifier used for charge cancellation.
Vin > +Vref/4
+Vref/4 > Vin > -Vref/4
Vin < -Vref/4
Vin
Vinp
Vinn
∆Q
∆Qr
Total
∆Q
1.0V
0.8V
0.6V
3.0V
2.9V
2.8V
2.0V
2.1V
2.2V
0fC
500fC
500fC
50fC
100fC
450fC
400fC
500fC
500fC
0.4V
2.7V
2.3V
150fC
350fC
500fC
0.2V
0.0V
2.6V
2.5V
2.4V
2.5V
0fC
0fC
0fC
0fC
0fC
0fC
-0.2V
2.4V
2.6V
0fC
0fC
0fC
-0.4V
2.3V
2.7V
150fC
350fC
500fC
-0.6V
-0.8V
2.2V
2.1V
2.8V
2.9V
100fC
400fC
500fC
50fC
450fC
500fC
-1.0V
2.0V
3.0V
0fC
500fC
500fC
Table 4.2 – Relationship Between the Input Voltage and the Total Charge Kicked Back Using
Charge Cancellation
49
Since the total amount of ∆Q with charge cancellation is always 500fC for each pipelined stage
that connects to a reference voltage, and since there are a maximum of 3 stages connecting to
each voltage reference every half clock cycle, the maximum total charge kicked back into each
reference becomes:
QTotal  3 Cs   V  Vr   3  500fC  1.5pC
Equation 4.3
4.2 Simplified Charge Cancellation Model
A simplified charge cancellation test simulation was created to validate the theory of charge
cancellation. The testbench for this simplified simulation is shown in Figure 4.3. Capacitor Cres1
represents the Cs capacitor in the original residue amplifier and Cres2 represents the Cs capacitor
in the replica residue amplifier. The exact sizes of the sampling capacitors and the exact clock
timings used in the testbench were the same ones used in the original pipelined ADC design.
During the clock 1 phase, Cres1 and Cres2 are charged to the input signals, Vsig_p and Vsig_n.
Then during the clock 2 phase, the Cres1 and Cres2 capacitors connect to the positive reference
voltage, which is 3V. Clock 3 was added as an extra feature to easily change from simulations
where only Cres1 connects to Vref to simulations where both Cres1 and Cres2 connect to Vref.
The results of these simulations are shown in Figures 4.4 through 4.6. Six different input voltages
ranging from +Vref to +Vref/4 were tested with the results given in Table 4.3. The response of
the positive reference voltage in the simulations employing charge cancellation is nearly invariant
to changes in the input signal voltage, while the response of this same voltage reference in the
simulations without charge cancellation vary by much more. The variation in the reference
50
voltage without charge cancellation was 700µV compared to a variation of only 6µV in
simulations with charge cancellation. This is over a 100 fold decrease in variability, which shows
that the reference voltage outputs are nearly independent of the input signal voltage when this
charge cancellation technique is used. Note that, while the variations in the reference voltage
mentioned above may seem small, these variations will be much larger as the reference buffers
and bypass capacitors are reduced in size, which is the goal of this effort.
Single-Ended Value
Peak Vdrop
Simulation Vin (differential) Vsig_p
Vsig_n
Without Charge
Cancellation
With Charge
Cancellation
1
2
3
4
5
6
2.0V
2.075V
2.15V
2.225V
2.3V
2.375V
0.12mV
0.25mV
0.39mV
0.60mV
0.67mV
0.81mV
2.078mV
2.080mV
2.082mV
2.083mV
2.083mV
2.082mV
1.0V
0.85V
0.7V
0.55V
0.4V
0.25V
3.0V
2.925V
2.85V
2.775V
2.7V
2.625V
Table 4.3 – Values for the Simplified Charge Cancellation Simulations
Figure 4.3 – Simple Charge Cancellation Test Schematic
51
52
Figure 4.4 – Results of the Simulations without Charge Cancellation
Figure 4.5 – Results of the Simulations with Charge Cancellation
53
Figure 4.6 – Expanded View of the Results with Charge Cancellation
Figure 4.7 – Maximum Vref Voltage Drops with and without Charge Cancellation
54
The maximum voltage drop in the simulations without charge cancellation was 0.8mV. This
compares well to the theoretical calculation of 0.75mV in Equation 3.1. The reason for the
simulation’s slightly higher voltage drop stems from the charge injected by the switches when
they turn off. The maximum voltage drop in the simulations with charge cancellation was 2.1mV.
This drop is much higher, which was expected because additional charge is kicked back onto the
voltage reference from the replica residue amplifier capacitor, Cres2. The comparison of
maximum voltage drops is shown in Figure 4.7. Although the voltage drop is much larger with
this new charge cancellation technique, the response of the voltage reference is much more signal
independent which will allow smaller reference buffer devices and bypass capacitors to be used
without sacrificing performance.
55
Chapter 5
CHARGE CANCELLATION PIPELINED ADC MODEL
5.1 Charge Cancellation Pipelined ADC Model Overview
In order to make good decisions about the redesign of the reference voltage buffers in the original
pipelined ADC, more information was needed regarding how modifying the bypass capacitance
and the output resistance in these reference voltage buffers would effect the performance of the
ADC. In this section, a modified version of a 1.5-bit/stage Pipelined ADC Matlab model is
discussed [11]. In the original model, a 1.5-bit/stage pipelined ADC was modeled to include
common pipelined ADC error sources such as capacitor mismatch, finite opamp gain, and
comparator offset. The original model calculates important performance metrics such as ENOB
and SNDR. The Matlab model used for this project was modified from the original model to
include errors due to the voltage references. This was accomplished by modeling the time
response of the voltage references as a single time constant RC circuit, where R is the output
resistance of the reference buffer and C is the bypass capacitance. This change allows the new
Matlab model to include time dependent voltage reference errors.
When using the Matlab model, the frequency used for the input signal was carefully chosen to
avoid sampling the same points on the input sine wave over and over again. It was also chosen
such that an integer number of periods of the input sine wave were contained in the total sampling
time, so that rectangular windowing could be used during Fast Fourier Transform (FFT) analysis
of the ADC output codes. Both objectives were accomplished by using a prime number for the
integer number of periods of the input sine wave that were contained in the total sampling time..
Specifically, the input frequency used was 1.044921875Mhz which was found using
Equations 5.1 and 5.2.
56
Fin (prime) 
Prime Number
 Fsample
Number of Samples
Equation 5.1
Fin (prime) 
107
 20MHz  1.044921875MHz
2048
Equation 5.2
Figure 5.1 shows how ENOB changes as Rout, the output resistance of the reference voltage
buffers is varied. The blue curve is for the original ADC without the charge cancellation circuit,
and the red curve is for the new ADC with the charge cancellation circuit added. The bypass
capacitor used at the output of the reference voltage buffers was kept constant at the original
value of 250pF for these simulations. As Rout was increased, the input voltage amplitude was
also decreased to avoid clipping since the average value of the reference voltages goes down as
Rout is increased. The input amplitude was kept at approximately 1dB below the maximum full
scale input level for all of these simulations.
8
7.5
ENOB
7
6.5
6
Blue = Original ADC
Red = New ADC with charge cancellation
5.5
0
200
400
600
800
1000
1200
1400
Rout
Figure 5.1 – ENOB vs. Rout with and without Charge Cancellation
1600
57
5.2 Charge Correction
The ADC with charge cancellation exhibits lower ENOB as Rout is increased. This is because the
reference voltage is still somewhat signal dependent. As shown in Table 4.2, when
+Vref/4 > Vin > -Vref/4, there is no charge transfer from the voltage references to the residue
amplifiers. Since the amount of charge kicked back onto the voltage references is different for
this range of input voltages, the voltage reference varies with input voltage, and this signal
dependence leads to distortion and therefore lower ENOB. To correct for the case of no kickback
charge when +Vref/4 > Vin > -Vref/4, charge needs to be added to each reference for this range
of input signal values and this added charge also needs to be the same amount of charge that is
kicked back for other input values (see Table 4.2). To supply this charge, two extra capacitors
were added to supply the missing 500fC of charge to each reference voltage. The implementation
of this charge correction circuit is illustrated in Figure 5.2. This charge correction circuit ensures
that the same amount of charge is kicked back onto the voltage references for the case where
+Vref/4 > Vin > -Vref/4, as shown in Table 5.1. The S0 signal is from the DAC in the main
residue amplifier, and causes these extra charge correction capacitors to connect to the references
during the settling phase of the clock for the appropriate values of input voltage. Note that the
capacitors shown inside the dotted lines are not a part of the charge correction circuit, but instead
are the capacitors in the main and replica residue amplifiers, shown here to aid in understanding
how the entire circuit works together. It is worth noting that, if this were a 1-bit per stage
pipelined ADC instead of a 1.5-bit per stage pipelined ADC, a charge correction circuit would not
be needed since the same amount of charge would be kicked back from the residue amplifiers
onto the voltage references for all values of input voltage after the charge cancellation circuit is
added.
58
+
Vinp Vicm
Capacitors in the
main and replica
residue amplifiers
Cs
S0
+
Vinn Vicm
±Vref
CS
S0
Vicm
S0
VCM
2·Cs
Figure 5.2 – Charge Correction Circuit
Vin > +Vref/4
+Vref/4 > Vin > -Vref/4
Vin < -Vref/4
Vin
Vinp
Vinn
∆Q
∆Qr
∆Q
Total
Correction ∆Q
1.0V
3.0V
2.0V
0fC
500fC
0fC
500fC
0.8V
0.6V
2.9V
2.8V
2.1V
2.2V
50fC
100fC
450fC
400fC
0fC
0fC
500fC
500fC
0.4V
2.7V
2.3V
150fC
350fC
0fC
500fC
0.2V
2.6V
2.4V
0fC
0fC
500fC
500fC
0.0V
2.5V
2.5V
0fC
0fC
500fC
500fC
-0.2V
2.4V
2.6V
0fC
0fC
500fC
500fC
-0.4V
2.3V
2.7V
150fC
350fC
0fC
500fC
-0.6V
-0.8V
2.2V
2.1V
2.8V
2.9V
100fC
50fC
400fC
450fC
0fC
0fC
500fC
500fC
-1.0V
2.0V
3.0V
0fC
500fC
0fC
500fC
Table 5.1 – Kickback Charge vs. Input Voltage Including the Charge Correction Circuit
59
5.3 Results
Figures 5.3 - 5.5 illustrate how ENOB varies as Rout, the output resistance of reference voltage
buffers, is changed with the charge correction circuits included. Three bypass capacitance values
were used in these simulations to show the variability of ENOB versus not only Rout, but also
versus the value of the bypass capacitance, Cbypass, as well.
8
ENOB
7.5
7
Blue = Original ADC
Red = New ADC with charge cancellation
Black = New ADC with charge cancellation and correction
6.5
0
200
400
600
800
1000
1200
1400
Rout
Figure 5.3 – ENOB vs. Rout with and without Charge Cancellation and Correction,
Cbypass = 250pF
1600
60
8
7.5
ENOB
7
6.5
6
5.5
0
Blue = Original ADC
Red = New ADC with charge cancellation
Black = New ADC with charge cancellation and correction
200
400
600
800
1000
1200
1400
1600
Rout
Figure 5.4 – ENOB vs. Rout with and without Charge Cancellation and Correction,
Cbypass = 100pF
8
7.5
ENOB
7
6.5
6
5.5
5
0
Blue = Original ADC
Red = New ADC with charge cancellation
Black = New ADC with charge cancellation and correction
200
400
600
800
1000
1200
1400
Rout
Figure 5.5 – ENOB vs. Rout with and without Charge Cancellation and Correction,
Cbypass = 10pF
1600
61
When Rout and Cbypass are increased to a point where the voltage references cannot recover
before the end of the settling phase, ENOB degrades. In all three figures, as Rout gets larger, the
ENOB values in the charge cancellation simulation (with charge correction) degrade more slowly
than the other two cases. Although the voltage references in the charge cancellation case do not
recover to their original value, they do recover to a steady-state value. Figures 5.6 and 5.7 show a
plot of Vrefp over approximately 2000 clock cycles, as measured at the end of the settling phase
when it connects to the residue amplifiers. In these figures Rout was increased to 1800Ω and
Cbypass was decreased to only 10pF. Figure 5.6 shows the large fluctuations that Vrefp has with
these values for Rout and Cbypass if charge cancellation and correction are not used. These large
changes in Vrefp lead to increased distortion and lower ENOB, as previously discussed. In sharp
contrast, Figure 5.7 shows that even with this large value for Rout and low value for Cbypass
Vrefp reaches a steady state value that is signal independent.
It should be noted that Vdrop is larger when charge cancellation is used because of the additional
kickback charge from the replica residue amplifiers. However, since the reference voltages are
signal independent with charge cancellation added, distortion is reduced and ENOB increased.
The larger Vdrop does cause the effective value of the references to be slightly smaller, which
causes a gain error in the ADC response. However this is preferable, since this gain error is linear
and does not cause distortion. Figure 5.7 shows the voltage reference Vrefp at the end of the
settling phase is 47.6mV lower than its original value of 3V. This drop in reference level
represents an 4.76% linear gain error in the ADC transfer function based on the ADC's nominal
full-scale differential input signal range of ± 1V, and assuming a similar error in Vrefn. If this
much gain error cannot be tolerated, then smaller values of Rout must be used.
62
2.998
2.996
Vrefp (V)
2.994
2.992
2.99
2.988
2.986
0
20
40
60
Time (us)
80
100
Figure 5.6 – Vrefp vs. Time for the Original ADC with Rout = 1800Ω, Cbypass = 10pF
2.9526
Vrefp (V)
2.9525
2.9524
2.9523
2.9522
0
20
40
60
Time (us)
80
100
Figure 5.7 – Vrefp vs. Time for the ADC with Charge Cancellation and Correction,
with Rout = 1800Ω, Cbypass = 10pF
63
5.4 Impact on Pipelined ADC Design
To implement the new reference voltage architecture with charge cancellation, carefully planned
design changes would need to be made to the reference voltage buffers in the original pipelined
ADC. As shown in the simulation results in the previous section, a much smaller bypass
capacitance and higher output resistance for the reference voltage buffers can be used without
loss in ADC performance. Both raising the output resistance of the replica bias circuit (recall
Figure 2.24) and lowering the bypass capacitance on the outputs of the reference voltage buffers
will greatly decrease the amount of silicon area used by these circuits, as well as save power.
Therefore, these changes are highly desirable. However, some of this area and power will be used
by the new charge cancellation and correction circuits, which must be added to make this new
architecture function correctly. Overall area and power would be reduced for the 8-bit Pipelined
ADC examined here, with this tradeoff becoming even more favorable for higher resolution
Pipelined ADCs.
The reference voltage buffers would not be the only circuit in the pipelined ADC that would need
to be redesigned. Because of the addition of the replica residue amplifiers, the redesign of certain
ADC blocks are needed. The clock buffers must drive additional capacitance due to the loading of
the replica residue amplifier switches (see Figure 4.2). A test simulation was run to verify that the
existing clock buffers can drive this extra load, negating the need for redesign. The comparators
in the original residue stages will see extra load capacitance due to the DACs in the replica
residue amplifiers. Redesign of the comparator digital output buffers may need to be performed in
order to handle this extra load. Additional bias currents would also need to be added to bias the
operational amplifiers in the replica residue amplifiers. Most importantly, the input capacitance of
the replica residue stages will present an additional load to the main residue amplifiers that have
64
to drive their inputs. This will likely require the opamps in these amplifiers to need to be
redesigned to accommodate this additional load capacitance.
65
Chapter 6
CONCLUSION
Optimizing power and area for reference voltage generators in pipelined ADCs can prove
to be a difficult process. For reference voltage generators in general, decreasing power
and area directly decreases stability. Because of this fact, designing reference voltages
generators becomes a difficult balancing act of trying to decrease power and area while
also trying to provide voltages that have adequate stability for its application.
In a conventional pipelined ADC, reference voltage generators are designed to be stable
for all input scenarios at all times. This paper shows that reference voltage generators
only need to be stable, or “at value” during the end of the settle and hold phase when the
analog output of one residue stage is being sampled by the next stage. By loosening the
constraints on the reference voltage generator, the area used for the reference voltage
bypass capacitance and the area and power required for the reference voltage buffer can
be greatly reduced. As shown in Chapter 3, the power and area of the reference voltage
buffer could be reduced by a factor of 28 or more.
This project also investigated signal-dependent charge cancellation, the process of
kicking back an equal amount of charge to the voltage references regardless of the input
signal voltage. Charge cancellation is achieved by adding a replica residue stage to each
original residue stage that kicks back a complimentary charge so that the total charge that
is kicked back is invariant with the input signal voltage. The Matlab model in Chapter 5
66
illustrates that a pipelined ADC using charge cancellation can outperform a conventional
pipelined ADC by decreasing the area required for the reference voltage buffer.
Although charge cancellation allows for smaller reference voltage buffers, other circuits
must be added to make charge cancellation work, such as the replica residue stages and
the charge correction circuits, which reduces the area and power savings. Also, it was
found that charge cancellation is better suited for use with a 1-bit/stage pipelined ADC
than with a 1.5-bit/stage architecture since the additional charge correction circuits aren’t
required with the 1-bit/stage architecture. Higher resolution ADCs are also better
candidates for use with the charge cancellation technique because the area and power of
the voltage reference generator increases more rapidly with increased resolution than the
added charge cancellation circuits.
67
APPENDIX
See attached compact disc for Matlab code related to this project.
68
REFERENCES
[1] “Analog-to-digital converter.” Wikipedia. Feb 7, 2011. Feb 18, 2011.
< http://en.wikipedia.org/wiki/Analog-to-digital_converter>.
[2] Robert H. Walden, “Analog-to-Digital Converter Survey and Analysis.” IEEE J.
Selected Areas in Communications, vol. 17, no. 4, April 1999.
[3] Vilaysack Savengsveksa, Perry L. Heedley, Thomas Matthews, Kamel Ahmad, and
Jose Negrete. “An 8-b 20-Msample/s Pipelined A/D Converter in 0.5-µm CMOS with 7.8
ENOB.” IEEE International Midwest Symposium on Circuits and Systems, 2005.
[4] Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, and Omid Shoaei.
“Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters.”
International Conference on Computer-Aided Design, Nov. 11-13, 2003.
[5] Vilaysack Savengsveksa. “The Design of an 8-bit 20-MSample/s Pipelined Analogto-Digital Converter in 0.5-µm CMOS with 7.8 ENOB.” Master of Science project
report, California State University, Sacramento, May 2007.
[6] Tamara Schmitz. “Trade-Offs in New Generation Ics.” Aug 21st 2011. Sep 14th 2011.
<http://www.eeweb.com/blog/tamara_schmitz/balancing-the-tradeoffs-in-newgeneration-adcs>.
[7] Kevin B. Geoghegan. “Design of an 8-bit, Pipelined, Analog-to-Digital Converter
implemented in a 0.5µm CMOS process.” Master of Science project report, California
State University, Sacramento, Fall 2006.
[8] Behzad Razavi. “Design of Analog CMOS Integrated Circuits.” McGraw-Hill. New
York, New York. 2001.
[9] S.H. Lewis, H.S. Fetterman, G.F. Gross, Jr., R. Ramachandran, and T.R. Viswanathan. “A 10b 20-Msample/s Analog-to-Digital Converter.” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp.
351-358, March 1992.
[10] Anas Ahmad. “Design of Reference Voltages and Bias Currents Generation Circuits
For an 8 Bit 20 MHz Pipelined Analog-to-Digital Converter in 0.5µm CMOS.” Master of
Science project report, California State University, Sacramento, Fall 2005.
[11] Discussions with Dr. Perry Heedley.
[12] Dr. Perry Heedley’s Class Notes.
69
[13] Ken Martin and David Johns. “Analog Integrated Circuit Design.” John Wiley &
Sons, Inc. 1997.
[14] “Demystifying Delta-Sigma ADCs.” maxim-ic.com. Jan 31, 2003.
<http://www.maxim-ic.com/app-notes/index.mvp/id/1870>.
[15] Len Staller. “Embedded Systems Design.” digital95.blogspot.com. Feb 24th, 2005.
< http://digital95.blogspot.com/2009_02_01_archive.html>.