Workshop 1 - 2-1 MUX
P.K. Oct 2012
VHDL Workshop 1 - 2 to 1 Multiplexer
Objective:

Introduce digital circuit simulation in VHDL using the AlteraModelsim Simulator.
Background.
A 2 to1multiplexer is as digital switch that selects between two 1-bit input signals.
One of the two inputs is brought to the output pin depending on the state of a single
bit “selector” input.
Figure 1 shows a schematic implementing a 2:1 multiplexer using four Boolean gates
Fig1: Schematic of a 2:1 Multiplexer.
The output F will have the value of either A or B, depending on the value of C.
The Boolean equation describing this circuit is
F = A.C + B.C’
The VHDL model of the circuit shown in Fig1 is provided in the file mux21.vhd. This
uses four concurrent Boolean assignments, one for each gate. The entity mux21, that
represents the circuit interface is modelled by two different architectures, one labelled
boolean_no_delay having no propagation delays and the other boolean_with_delay
with the gate propagation delay of 2 ns.
The file cnfg_ mux21.vhd contains the configuration statement that allows to select
the particular architecture one wishes to use in the simulation.
The file mux21_tb.vhd represents a test circuit, the so called Test Bench, that can be
used to evaluate the functional behaviour of the mux21 component. It allows the user
to specify input test vectors for the three inputs A,B and S.
TASK 1:
Work through the accompanying ModelSim tutorial to learn how to simulate this
circuit.
TASK 2:
The VHDL listing shown below is a structural implementation of the mux21 entity
using the three gates, this time represented as separate entities of their own.
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Workshop 1 - 2-1 MUX
P.K. Oct 2012
In the “declaration” part of the architecture labelled structure, the gates are declared
as components named and2_gate, inv1_gate and or2_gate. Then in the “executive”
part of the architecture they are instantiated into the mux21 circuit.
a. Insert this third architecture “structure” into the existing file mux21.vhd.
b. Create three new VHDL files named and2_gate.vhd, inv1_gate.vhd and
or2_gate.vhd, one for each new entity of the same name yet to be defined.
Write new VHDL code defining each of the entities using an architecture with
a single Boolean assignment. All three gates should exhibit a propagation
delay of 3 ns. Save the three files and add them to the Modelsim Project
created for the earlier tutorial.
c. Modify the code given in cnfg_ mux21.vhd to configure the component
mux21 to use the architecture labelled structure. Run the simulation and show
that the circuit exhibits a static hazard 1.
ARCHITECTURE structure OF mux21 IS
-- Insert declarations
-- Declare the components
COMPONENT inv1_gate IS
PORT( data
: IN
bit;
result
: OUT bit);
END COMPONENT;
COMPONENT and2_gate IS
PORT( data0, data1
result
END COMPONENT;
: IN
: OUT
COMPONENT or2_gate IS
PORT( data0, data1
result
END COMPONENT;
: IN
: OUT
bit;
bit);
bit ;
bit);
--Declare the internal interconnecting wires
SIGNAL c_not, x, y
: bit;
BEGIN
-- Executive part
--Instantiate the components and interconnect the wires
U1: inv1_gate port map (data => C, result=>c_not);
U2: and2_gate port map (data0 => c_not, data1 =>B, result=>y);
U3: and2_gate port map (data0 => C, data1 => A, result => x);
U4: or2_gate port map (data0 => y, data1 => x, result =>F);
END structure;
TASK 3:
a. Modify the circuit in figure 1 to remove the static hazard.
b. Implement the modified circuit as a new architecture for the entity mux21
called improved_structure. Add the architecture improved_structure into the
mux21.vhd file.
c. Modify the code given in cnfg_ mux21.vhd to configure the component
mux21 to use the architecture improved_structure.
d. Simulate to show that the architecture improved_structure of the mux21
component is free of static hazard.
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