Simple design:
top.v:
module top
(
input registerLocalClock,
input registerLocalReset,
input control_RESETWrite,
output control_RESET_ext_fpga,
output control_RESET_si5347,
output control_RESET_spi,
output control_RESET_i2c,
output control_RESET_apb,
input [4:0] registerLocalWriteData
);
ConfigurationRMRegister #(5) RESET_ConfigurationRM (
.clock(registerLocalClock),
.reset(registerLocalReset),
.load(control_RESETWrite),
.out({
control_RESET_ext_fpga,
control_RESET_si5347,
control_RESET_spi,
control_RESET_i2c,
control_RESET_apb
}),
.data({
registerLocalWriteData[4],
registerLocalWriteData[3],
registerLocalWriteData[2],
registerLocalWriteData[1],
registerLocalWriteData[0]
}),
.defaultValue(5'h1e),
.writeMask(5'h00)
);
endmodule
ConfigurationRMRegister.v:
module ConfigurationRMRegister #(
parameter BITS = 1
)(
input
clock,
input
reset,
input
load,
input [BITS-1:0] defaultValue,
input [BITS-1:0] writeMask,
input [BITS-1:0] data,
output reg [BITS-1:0] out
);
always @(posedge clock or posedge reset)
if (reset)
out <= defaultValue;
else if(load)
out <= (writeMask & out ) | (~writeMask & data);
endmodule
Synthesis snapshot of simple design:
Synthesis snapshot of same module instance in original design: