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校 輔仁大學
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所 電子工程學系
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494505305
號
研
究
林彥宏
生
(中
)
研
究
Yen Hung Lin
生
(英
)
論
文 一個具有變動的完成時間之同步乘模運算電路
名
稱
(中
)
論
文
名 A Synchronous Modular Multiplier with Variable Latency Design
稱
(英
)
其
他
題
名
指
導
教 林寬仁
授
(中
)
指
導
教 Kuan Jen Lin
授
(英
)
校
內
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文 2008.8.11
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案 封面 摘要(中) 摘要(英) 誌謝 目次 內文 參考文獻
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明
電
子 01 02 03 04 05 06 07
全
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位 碩士
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畢
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96
學
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版 97
年
語
文 英文
別
關
鍵
乘模運算 SRT 演算法 除法
字
(中
)
關
鍵
modular multiplication SRT algorithm division
字
(英
)
乘模 (modular multiplication) 運算在加密系統和餘數算術系統都有極為重要
摘 的應用。這篇論文實作了一個具有變動的完成時間之同步乘模運算電路，
其中完成時間係依據運算元數值而定。而模運算是利用 radix-2 SRT 除法演
要
算求得餘數。但是其判斷商數之函數，我們則為了電路面積與速度而在不
(中
同運算步驟中有所調整。我們在 TSMC 0.18um 製程環境下，成功合成與驗
)
證了此一設計。其實驗結果與固定運算完成時間之設計相比，明顯可降低
大量運算時間，而只增加了之 8%電路面積。
Modular multiplication is a very important arithmetic operation in cryptography
systems and residue-based computation. This paper presents a synchronous modular
摘
multiplier that has variable computation latency depending on operand values. The
要 modular reduction operation is based on SRT radix-2 division. However, the quotient
(英 selection function in certain stages is adapted for reducing delay and area. The
) proposed variable latency design was synthesized and verified with TSMC 0.18um
technology. It can achieve significant computation time reduction compared to a
fixed-latency design, while needing only 8% larger area.
論
文
目
次
Abstract (in Chinese) ………………………………………………………………i
Abstract …………………………………………………………………ii
Acknowledgement …………………………………………………………………
…iii Contents …………………………………………………………………iv
List of Tables …………………………………………………………………… vi
List of Figures ………………………………………………………vii 1
Introduction ………………………………………………………………………1
1.1 Modular Multiplication in Cryptographic Application ………………1 1.1.1
Cryptographic Systems …………………………………………1 1.1.2 Residue
Number System ………………………………………………4 1.2 Purpose of This
Thesis …………………………………………………4 1.3
Organization …………………………………………………6 2 Modular
multiplications …………………………7 2.1 Division After Multiplication versus
Division During Multiplication ………7 2.1.1 Division During
Multiplication .......................................7 2.1.2 Division After
Multiplication ....................................9 2.2 Direct Method versus Montgomery
Method ………………………………11 2.2.1 Direct
Method …………………………………………………………12 2.2.2
Montgomery Method ………………………………………13 2.3 Modular
Addition …………………………………………14 2.4 Pre-calculate H 2n mod
D …………………………………………………15 2.5 Redundant
Representation ………………………………………………17 2.6
Division ………………………………………………19 2.7 Array
Design …………………………………………21 3 Synchronous Variable Latency
Design ………22 3.1 SRT Division in Carry-Save
Representation ………………………………22 3.2 Fixed Latency
Design …………………………………………………24 3.3 Adapting the
Quotient Selection Function ………………………………25 3.4 Selective
Bypassing …………………………………………………………………………
…26 3.5 Overlapping Quotient
Selection ……………………………………………27 3.6 Control
Circuits ……………………………………………………………………27 3.7
Variable Stage Number ……………………………………………………28 4
Implementation and Experimental Results ……………………………………30 4.1
Design Flow ………………………………………………………30 4.2 Delay
Analysis …………………………………………………31 4.3 Experimental
Results ………………………………………………………32 4.4 ARM
Integrator ……………………………………………………………35 4.5
AMBA-Compliant
Design ……………………………………………………………37 5
Conclusions ……………………………………………………………40
References ……………………………………………………41
參
考
文
獻
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