Peter Wu
TA: JM
Lab Partner: Win Ton
Section 1
10/25/11
PW1
Lab Station #8
Op Amp Design Lab Report
Experiment Section
Task #1
Experimental Introduction
Title: Basic Inverting Amplifier
Design Objective: The objective and purpose of this task is to build a circuit using an op amp,
resistors, and bypass capacitors that inverts an input signal from the function generator and also
amplifies this signal to a maximum of 16 Vpp.
Schematic:
Figure 1: Inverting Op Amp Circuit
PW 2
Theory of Operation: This circuit is composed of an op amp, two bypass capacitors, and two
resistors with one of the resistors being the feedback resistor. The combination of an input
voltage source into the negative terminal of the op amp, negative feedback network, and the
grounding of the positive terminal of the op amp creates an inverting amplifier that inverts the
input voltage, or in other words, changes the polarity of the input signal and also amplifies it by
the factor of the gain of the circuit. The gain in this circuit is determined by the negative of the
feedback resistance divided by the input resistance. The bypass capacitors connected to the
power supply that powers the op amp act to cancel out the noise that comes from the circuitry.
Derivations and Analysis: Vout = Gain * Vin  Vout / Vin = Gain  Vout / Vin = -Rf / Rin since
the gain of an inverting amplifier is –Rf / Rin with Rf being the feedback resistance and Rin being
the input resistance. -16 Vpp / 0.2 Vpp = -80 = Gain = -Rf / Rin. So the ratio of Rf / Rin is 80. The
resistors chosen that abide by this ratio were 120kΩ for the feedback resistor and 1.5kΩ for the
input resistor.
Experimental Results
Measurements:
Table 1: Resistor Values
Input Resistor (Rin)
Feedback Resistor (Rf)
Multisim Simulation Results:
Output Voltage = 16 Vpp
Input Voltage = 200 mVpp
Physical Implementation Results:
Output Voltage = 15.8 Vpp
Input Voltage = 206 mVpp
Nominal Resistance (Ω)
1500 Ω
120 kΩ
Measured Resistance (Ω)
1485 Ω
117.2 kΩ
PW 3
Figure 2: Input and Output Signal Voltages for Inverting Amplifier
Calculations:
Theoretical Case:
Vout = (-Rf / Rin) * Vin  Vout = (-120 kΩ / 1.5 kΩ) * (0.2 Vpp) = -80 * 0.2 Vpp = -16 Vpp
Experimental Case:
Vout = (-Rf / Rin) * Vin  Vout = (-117.2 kΩ / 1.485 kΩ) * (0.2 Vpp) = -78.9 * 0.2 Vpp = -15.8 Vpp
Percent Error:
% Error = | nominal value – measured value | * 100% = | 16 Vpp - 15.8 Vpp | * 100% = 1.25%
Nominal value
16 Vpp
PW 4
Discussion of Results / Concluding Thoughts
From figure 2, one can tell that the inverting amplifier did its job as the input signal
reaches a maximum at a time when the output signal reaches a minimum. This is evidence of the
inverting of the input signal. One can also see the input signal of about 200 mVpp amplified to
about 15.8 Vpp for a gain of around -78.9 which is very close the theoretical gain of -80 based on
the resistors used in table 1. The percent error of the theoretical and actual output voltages was
only 1.25% which shows how well our design worked.
A possible source of error that attributed to the tiny percent error in our output voltage is
the 5% tolerance of the resistors, meaning that the actual resistance values of the resistors can be
off from the nominal resistance values by 5% as our measured resistance values were 1485 Ω
and 117.2 kΩ compared to their nominal resistance values of 1500 Ω and 120 kΩ. Another
possible source of error lies in our not accounting for the internal resistance in the wires in the
circuit. Other sources of uncertainty lie in the precision of the function generator, oscilloscope,
op amp, and other devices due to their limitations. What one could do differently to get better
results is to get resistors closer to the nominal resistance values and to use as few wires as
possible to minimize the internal resistance of the wires that affects our results.
Answer to Question 1: To change our design and get a variable-gain amplifier with an output
signal in the voltage range of 8Vpp to 16Vpp, we could replace the input resistance with a 500Ω
resistor and replace the feedback resistance to consist of a 20kΩ resistor in series with a 20kΩ
potentiometer so that one could get a gain of 40 to 80 that amplifies the 0.2Vpp input signal to an
output range of 8Vpp to 16Vpp.
PW 5
Task #2
Experimental Introduction
Title: Weighted Summing Amplifier
Design Objective: The objective and purpose of this task is to design a circuit using an op amp,
feedback and input resistors, and bypass capacitors that takes two unbalanced input signals;
inverts and amplifies each signal so that the a 16 Vpp output is produced that is the balanced and
inverted sum of these two channels. In other words, the amplification or gain done to each input
signal has to be different and cause individual outputs that are the same to add up to that 16 Vpp
output.
Schematic:
Figure 3: Inverted Weighted Summing Op Amp Circuit
PW 6
Theory of Operation: This circuit is composed of an op amp, two bypass capacitors, a feedback
resistor and two input resistors, one connected to each input channel. The positive terminal of the
op amp is grounded. The negative terminal of the op amp is connected to two different input
signals with their respective input resistors and also connected to the feedback network with its
respective feedback resistor. The combination of all of these elements create a weighted
summing amplifier that takes two input signals, amplifies each one by their respective gains
affected by their respective input resistances (since the feedback resistor is the same for both
input channels) and inverts these signals to get an output signal that is the sum of these two
respective inverted, amplified signals.
Derivations and Analysis: Vout = (GainR * Vin,R) + (GainL * Vin,L) with the subscripts R and L
representing the right and left channels Vout = ((-Rf / RR) * Vin,R) + ((-Rf / RL) * Vin,L) with Rf
being the feedback resistor and RR and RL being the input resistors at the right and left channels
 -16 Vpp = ((-Rf / RR) * 0.2 Vpp) + ((-Rf / RL) * 0.5 Vpp) and to get a balanced left and right
channel output, Rf / RR can be 5 and Rf / RL can be 2. So the ratio of RR / RL = (Rf / RL) / (Rf /
RR) = 2/5. Also, ((Rf / RR) * 0.2 Vpp) and ((Rf / RL) * 0.5 Vpp) has to each equal -8 Vpp in order
for it to be considered balanced as this adds up to the output voltage of -16 Vpp. The resistors
chosen that satisfy this were 120kΩ for the feedback resistor, 3 kΩ for RR and 7.5 kΩ for RL.
Experimental Results
Measurements:
Table 2: Resistor Values
Right Input Resistor (RR)
Left Input Resistor (RL)
Feedback Resistor (Rf)
Multisim Simulation Results:
Output Voltage = 14.7 Vpp
Right Input Voltage = 200 mVpp
Physical Implementation Results:
Output Voltage = 14.0 Vpp
Input Voltage = 212 mVpp
Nominal Resistance (Ω)
3 kΩ
7.5 kΩ
120 kΩ
Measured Resistance (Ω)
3.008 kΩ
7.41 kΩ
117.2 kΩ
PW 7
Figure 4: Right Channel and Output Signal Voltages for Weighted Summer
Calculations:
Theoretical Case:
Vout = ((-Rf / RR) * Vin,R) + ((-Rf / RL) * Vin,L) = ((-120 kΩ / 3 kΩ) * 0.2 Vpp) + ((-120 kΩ / 7.5
kΩ) * 0.5 Vpp) = (-40 * 0.2 Vpp) + (-16 * 0.5 Vpp) = -8 Vpp – 8 Vpp = -16 Vpp
Experimental Case:
Vout = ((-Rf / RR) * Vin,R) + ((-Rf / RL) * Vin,L) = 14.0 Vpp
Percent Error:
% Error = | nominal value – measured value | * 100% = | 16 Vpp – 14.0 Vpp | * 100% = 12.5%
Nominal value
16 Vpp
PW 8
Discussion of Results / Concluding Thoughts
From figure 4, one can tell that the inverting amplifier did its job as the input signal
reaches a maximum at a time when the output signal reaches a minimum. This is evidence of the
inverting of the input signal. The percent error of the theoretical and actual output voltages was a
substantial 12.5% which shows how satisfactorily our design worked. The theoretical output
voltage was 16 Vpp while the actual output was 14.0 Vpp.
A possible source of error that attributed to the percent error in our output voltage is the
inexact calibration of our unbalanced audio signals to their respective voltages. It is relatively
difficult to get the left channel to have a maximum output of 500 mVpp and at the same time get
the right channel to have a maximum output of 200 mVpp through adjusting the volume on the
computer. There is also uncertainty in the precision of our instruments that could have
contributed to the percent error on top of the 5% tolerance of the resistors, meaning that the
actual resistance values of the resistors can be off from the nominal resistance values by 5%.
Another possible source of error lies in our not accounting for the internal resistance in the wires
in the circuit. What one could do differently to get better results is to get resistors closer to the
nominal resistance values and to adjust the volume to get the input voltages as close to their
theoretical values of 500 mVpp and 200 mVpp as possible. I believe that the inaccuracy in our
design lies in the calibration of the right and left audio channels.
Answer to Question 2: If one did not want to invert the balanced signal, one has a problem
because the circuit is an inverting summing amplifier circuit with the input signals going into the
negative terminal of the op amp. To fix this problem, one can use another op amp right after the
first op amp with the inverted balanced output of the first op amp going into the negative
terminal of the second op amp which is a basic inverting amplifier with a selected gain of -1 (-Rf
/ Ri = -1) to invert the inverted signal back to the polarity of the input voltages so as a result,
one’s balanced output signal would be non-inverted.
PW 9
Task #3
Experimental Introduction
Title: Two Channel Mixer with Balanced Inputs
Design Objective: The objective and purpose of this task is to design a circuit using an op amp,
feedback and input resistors, potentiometers, and bypass capacitors that takes two balanced input
signals; inverts and amplifies each signal so that the overall output of the circuit ranges between
0.4 Vpp when both channels are set to minimum gain and 16 Vpp when both channels are set to
maximum gain. The role of the potentiometer is to independently vary the gain on each
respective channel. The bypass capacitors cancel the noise created by the circuit.
Schematic:
Figure 5: Inverted Weighted Summing Op Amp Circuit (maximum gain)
PW 10
Figure 6: Inverted Weighted Summing Op Amp Circuit (minimum gain)
Theory of Operation: This circuit is composed of an op amp, two bypass capacitors, two
identical input resistors, a feedback resistor, and two 20 kΩ potentiometers connected in series
after each of the two input resistors. The positive terminal of the op amp is grounded. The
negative terminal of the op amp is connected to two different input signals with their respective
input resistors and also connected to the feedback network with its respective feedback resistor.
The combination of all of these elements create a weighted summing amplifier that takes two
input signals, amplifies each one by their respective gains affected by their respective input
resistances (since the feedback resistor is the same for both input channels) and inverts these
signals to get an output signal that is the sum of these two respective inverted, amplified signals.
To get an overall output range of 0.4 Vpp to 16 Vpp, potentiometers are adjusted at each input to
vary the voltage seen at the negative terminal and the two individual gains in the circuit.
Derivations and Analysis: Vout = (GainR * Vin,R) + (GainL * Vin,L) with the subscripts R and L
representing the right and left channels Vout = ((-Rf / (RR + Rpot)) * Vin,R) + ((-Rf / (RL + Rpot))
* Vin,L) with Rf being the feedback resistor, Rpot being the resistance of the potentiometer, and RR
and RL being the input resistors at the right and left channels. To get a balanced input of 8Vpp for
PW 11
maximum gain and 0.2 Vpp for minimum gain from each channel, one needs a gain of -16 and 0.4 respectively. One also knows that RL = RR because the input voltage is balanced. Using this
the maximum gain occurs when the potentiometer is at 0%, so -16 = Gainmax = -Rf / RR and the
minimum gain occurs when the potentiometer is at 100%, -0.4 = -Rf / (RR + 20 kΩ)  solving
the equations simultaneously  16RR / (RR + 20) = 2/5  80RR = 2RR + 40  RR = 40/78 =
512 Ω and Rf = 16RR = 16(512 Ω) = 8.20 kΩ
Experimental Results
Measurements:
Table 3: Resistor Values
Right Input Resistor (RR)
Left Input Resistor (RL)
Feedback Resistor (Rf)
Potentiometer 1
Potentiometer 2
*note: did not have 512 Ω resistors
Nominal Resistance (Ω)
499 Ω
499 Ω
8.2 kΩ
20 kΩ
20 kΩ
Multisim Simulation Results:
Output Voltage (max gain) = 15.8 Vpp
Right Input Voltage (max gain) = 500 mVpp
Output Voltage (min gain) = 395 mVpp
Right Input Voltage (min gain) = 500 mVpp
Physical Implementation Results:
Output Voltage (max gain) = 15.0 Vpp
Input Voltage (max gain) = 460 mVpp
Output Voltage (min gain) = 360 mVpp
Input Voltage (min gain) = 460 mVpp
Measured Resistance (Ω)
498 Ω
499 Ω
8.15 kΩ
20.17 kΩ
20.66 kΩ
PW 12
Figure 7: Right Channel and Output Signal Voltages (max gain)
Figure 8: Right Channel and Output Signal Voltages (min gain)
PW 13
Calculations:
Theoretical Case:
Vout, min gain = ((-Rf / (RR + 20 kΩ)) * Vin,R) + ((-Rf / (RL + 20 kΩ)) * Vin,L) = ((-8.2 kΩ / 0.512 kΩ
+ 20 kΩ) * 0.5 Vpp) + ((-8.2 kΩ / (0.512 kΩ + 20 kΩ)) * 0.5 Vpp) = (-0.40 * 0.5 Vpp) + (-0.40 *
0.5 Vpp) = -0.20 Vpp – 0.20 Vpp = -0.40 Vpp
Vout, max gain = ((-Rf / (RR + 0) * Vin,R) + ((-Rf / (RL + 0) * Vin,L) = ((-8.2 kΩ / 0.512 kΩ) * 0.5 Vpp)
+ ((-8.2 kΩ / 0.512 kΩ) * 0.5 Vpp) = (-16.0 * 0.5 Vpp) + (-16.0 * 0.5 Vpp) = -8.0 Vpp – 8.0 Vpp = 16.0 Vpp
Experimental Case:
Vout, min gain = ((-Rf / (RR + 20 kΩ)) * Vin,R) + ((-Rf / (RL + 20 kΩ)) * Vin,L) = -0.36 mVpp
Vout, max gain = ((-Rf / (RR + 0 kΩ)) * Vin,R) + ((-Rf / (RL + 0 kΩ)) * Vin,L) = -15.0 Vpp
Percent Error:
Vout, min gain:
% Error = | nominal value – measured value | * 100% = | 0.40 Vpp – 0.36 Vpp | * 100% = 10.0%
Nominal value
0.40 Vpp
Vout, max gain:
% Error = | nominal value – measured value | * 100% = | 16.4 Vpp – 15.0 Vpp | * 100% = 8.54%
Nominal value
16.4 Vpp
Discussion of Results / Concluding Thoughts
Our theoretical values for the output signal voltage were 0.40 Vpp and 16.0 Vpp for their
respective minimum and maximum gain set-ups due to the extremes of the potentiometer. Our
actual values were 0.36 Vpp and 15.0 Vpp respectively. These values resulted in percent errors of
10.0% and 8.54% which is substantially off but not enough to say that the experiment was
PW 14
designed improperly. Based on these percent errors, one would conclude that the design worked
satisfactorily.
A possible source of error that attributed to the percent error in our output voltage is the
inexact calibration of our unbalanced audio signals to their respective voltages. It is relatively
difficult to get the left channel to have a maximum output of 500 mVpp and at the same time get
the right channel to get the same output through adjusting the volume on the computer. There is
also uncertainty in the precision of our instruments that could have contributed to the percent
error on top of the 5% tolerance of the resistors, meaning that the actual resistance values of the
resistors can be off from the nominal resistance values by 5%. Another possible source of error
includes the actual value of the potentiometer compared to its theoretical value. Another possible
source of error lies in our not accounting for the internal resistance in the wires in the circuit.
What one could do differently to get better results is to get resistors closer to the nominal
resistance values and to adjust the volume to get the input voltages as close to their theoretical
values of 500 mVpp as possible. I believe that the inaccuracy in our design lies in the calibration
of the right and left audio channels.
Answer to Question 3: It is not possible to get an output of 0 Vpp with this setup as the input
resistance consisting of the input resistor and potentiometer would have to be infinitely-many
times greater than the feedback resistance. To address this problem, one would have to make it a
level shifting amplifier by adding a voltage source to the positive terminal.
PW 15
Task #4
Experimental Introduction
Title: Level-shifting amplifier
Design Objective: The objective and purpose of this task is to design a circuit using an op amp,
feedback and input resistor that inverts, amplifies, and removes the DC offset of an input signal
and achieve maximum signal amplification without exceeding the 16 Vpp input limit.
Schematic:
Figure 9: Level-shifting Amplifier
Theory of Operation: This circuit is composed of an op amp, two bypass capacitors, a feedback
and input resistor connected to the negative terminal of the op amp. The positive terminal of the
op amp is connected to a voltage source that acts to change the DC level of the input signal
PW 16
which can remove or amplify the DC component depending on polarity of the voltage source.
The other half of the op amp at the negative terminal acts just like a regular inverting amplifier
with an equation of Vout, partial = (-Rf / Rin) * Vin with its corresponding feedback resistor and input
resistor components. The overall output is given by combining this inverting amplifier output
with the output due to the voltage source at the positive terminal given by Vout, partial = (1 + Rf /
Rin) Vb with Vb being that voltage source at the positive terminal. The input signal voltage is
inverted and amplified and the offset is also canceled as a result of this combination of
components in the circuit.
Derivations and Analysis:
To get the resistor values: -8 Vp = (-Rf / Rin) * 0.3 Vp  Rf / Rin = 26.67 so choose Rf = 26.67
kΩ and Rin = 1 kΩ
The output voltage due to DC “source” causing the DC offset = DCout = Vin,DC * (-Rf / Rin) = 2.5
V * (-26.67) = -66.67 V
To cancel out DCout, Vb * (1 + Rf / Rin), which is the equation for the non-inverting part of the
level shifting op amp, has to be the component that cancels the DC offset. So 66.67 V = Vb * (1
+ Rf / Rin)  66.67 V = Vb * (1 + 26.67) 66.67 V = 27.67 * Vb  Vb = 2.41 V
Experimental Results
Measurements:
Table 4: Resistor Values
Nominal Resistance (Ω)
Input Resistor (Rin)
1 kΩ
Feedback Resistor (Rf)
27 kΩ
*note: chose resistor closest to 26.67 kΩ
Multisim Simulation Results:
Output Voltage = 16.2 Vpp
Input Voltage = 600 mVpp
Physical Implementation Results:
Output Voltage = 15.9 Vpp
Measured Resistance (Ω)
0.998 kΩ
26.57 kΩ
Input Voltage = 800 mVpp
PW 17
Figure 10: Input and Output Signal Voltages
Calculations:
Theoretical Case:
Vout = (1 + Rf / Rin) * Vb + (-Rf / Rin) * Vin  Vout = (1 + 27 kΩ / 1 kΩ) * 2.41 V – (27 kΩ / 1
kΩ) * 2.8 Vp = 67.48 Vp – 75.6 Vp = 8.12 Vp = 16.24 Vpp
Experimental Case:
Vout = (1 + Rf / Rin) * Vb + (-Rf / Rin) * Vin = 15.9 Vpp
Percent error:
% Error = | nominal value – measured value | * 100% = | 16.24 Vpp – 15.9 Vpp | * 100% = 2.09%
Nominal value
16.24 Vpp
PW 18
Discussion of Results / Concluding Thoughts
Our theoretical value for the output voltage of this level-shifting amplifier was 16.24 Vpp,
which one may think is above the output limit of 16.24 Vpp. However, one must note that the
ideal feedback resistor of 26.67 kΩ would have given the desired output voltage, but there were
no actual 26.67 kΩ resistors in the stockroom so we chose the 27 kΩ resistor and our theoretical
values are based off of that resistor. Our theoretical value of 16.24 Vpp and actual value of 15.9
Vpp accounted for a measly 2.09% error which justifies how extremely well our design worked in
canceling out the DC offset created by the function generator.
A possible source of error that may have played a role in our tiny percent error is the 5%
tolerance of the resistors, meaning that the actual resistance values of the resistors can be off
from the nominal resistance values by 5% as our measured resistance values were 0.998 kΩ and
26.57 kΩ compared to their nominal resistance values of 1 kΩ and 27 kΩ. Another possible
source of error lies in our not accounting for the internal resistance in the wires in the circuit.
Other sources of uncertainty lie in the precision of the function generator, oscilloscope, op amp,
and other devices due to their limitations. What one could do differently to get better results is to
get resistors closer to the nominal resistance values and to use as few wires as possible to
minimize the internal resistance of the wires that affects our results, but overall, the lesser
amount of devices used in this task resulted in fewer possible sources of error compared to the
other tasks which involved the use of potentiometers.
Answer to Question 4: One cannot have a variable signal amplification or gain in this circuit in
addition to the removal of the DC offset because one would have to add potentiometers
somewhere in the circuit whether it is at the feedback network or the input channel to vary the
gain of the circuit. However, this changes the canceling voltage provided by the voltage source at
the positive terminal by a different amount since their equations are not the same. The former is
governed by (1 + Rf / Rin) * Vb and the other by (-Rf / Rin) * Vin. There is a 1 in the first
expression used in an addition step while there is no 1 in the second expression.
PW 19
Task #5
Experimental Introduction
Title: Variable Level-shifting amplifier
Design Objective: The objective and purpose of this task is to design a circuit using an op amp,
feedback and input resistors that inverts, amplifies, and removes the DC offset of an input signal
that is between 1 and 3 V, and achieve maximum signal amplification without exceeding the 16
Vpp input limit. This level-shifting amplifier circuit can be adjusted to cancel any DC offset
between 1 Vdc and 3 Vdc. Use a potentiometer that cancels either 1 Vdc or 3 Vdc at its
extremes.
Schematic:
Figure 11: Variable Level-shifting Amplifier (1 V)
PW 20
Figure 12: Variable Level-shifting Amplifier (3 V)
Theory of Operation: This circuit is composed of an op amp, two bypass capacitors, a feedback
and input resistor connected to the negative terminal of the op amp. The positive terminal of the
op amp is connected to a voltage source that acts to change the DC level of the input signal
which can remove or amplify the DC component depending on polarity of the voltage source. In
addition to this voltage source, there is a voltage divider composed of a 20 kΩ potentiometer and
10 kΩ resistor that has the ability to cut the voltage at the positive terminal by two thirds the
voltage source at the positive terminal. The other half of the op amp at the negative terminal acts
just like a regular inverting amplifier with an equation of Vout, partial = (-Rf / Rin) * Vin with its
corresponding feedback resistor and input resistor components. The overall output is given by
combining this inverting amplifier output with the output due to the voltage source at the positive
terminal given by Vout, partial = (10 kΩ / (10 kΩ + pot resistance))(1 + Rf / Rin) Vb with Vb being
that voltage source at the positive terminal. The input signal voltage is inverted and amplified
and the offset is also canceled as a result of this combination of components in the circuit.
PW 21
Derivations and Analysis:
To get the resistor values: -8 Vp = (-Rf / Rin) * 0.3 Vp  Rf / Rin = 26.67 so choose Rf = 26.67
kΩ and Rin = 1 kΩ
The output voltage due to DC “source” causing the DC offset for (1 V) = DCout = Vin,DC * (-Rf /
Rin) = 1 V * (-26.67) = -26.67 V
The output voltage due to DC “source” causing the DC offset for (3 V) = DCout = Vin,DC * (-Rf /
Rin) = 3 V * (-26.67) = -80.0 V
To cancel out DCout, Vb * (1 + Rf / Rin), which is the equation for the non-inverting part of the
level shifting op amp, has to be the component that cancels the DC offset. So for the (1 V offset
case) 26.67 V = Vb * (1 + Rf / Rin)  26.67 V = Vb * (1 + 26.67) 26.67 V = 27.67 * Vb  Vb
= 0.96 V
To cancel out DCout, Vb * (1 + Rf / Rin), which is the equation for the non-inverting part of the
level shifting op amp, has to be the component that cancels the DC offset. So for the (3 V offset
case) 80.0 V = Vb * (1 + Rf / Rin)  80.0 V = Vb * (1 + 26.67) 80.0 V = 27.67 * Vb  Vb =
2.89 V
Now we will use a voltage source at the positive terminal of 2.89 V and set up a voltage divider
at that positive terminal to get 1/3 of that value which is 0.96 V through the use of a 20 kΩ
potentiometer and a 10 kΩ resistor. So when the potentiometer is at 0%, a voltage of 2.89 V will
be present at the positive terminal canceling out the 3V offset and when the potentiometer is at
100%, a voltage of 0.96 V will be present at the positive terminal canceling out the 1V offset.
Any voltage between 1 V and 3 V can be canceled by adjusting the wiper on the potentiometer
between its extremes.
Experimental Results
Measurements:
Table 5: Resistor Values
Input Resistor
Feedback Resistor
Potentiometer (100% Resistance)
Resistor in Voltage Divider at Positive
Terminal
Multisim Nominal Resistance (Ω)
1kΩ
27kΩ
20kΩ
10kΩ
PW 22
Multisim Simulation Results:
Output Voltage = 16.2 Vpp (for both 1 V and 3 V offset)
Input Voltage = 600 mVpp (for both 1 V and 3 V offset)
Discussion of Results / Concluding Thoughts
There are no results of physical implementation of the circuit as we ran out of time during
the lab session and were unable to physically test the circuit. Therefore, the simulation results are
all the data that we were able to collect. We believe that our simulation results are accurate
because the output voltage for both position extremes of the potentiometer is 16.2 Vpp and this is
very close to the theoretical value of 16.0 Vpp as defined in the task. Another reason is that one
can see the offset in the input channel on the oscilloscope alongside identical, unchanged output
signal waveforms which further supports the notion that the offset is canceled in both cases to
obtain identical output voltages. Therefore, these simulation results follow the theory of
operation as the use of the voltage divider consisting of a potentiometer and resistor indeed
cancels any DC voltage offset between 1 V and 3 V.
Answer to Question 5: In the variable level-shifting amplifier design, a problem would arise if
the unknown DC offset could be either positive or negative because this would require the
polarity of the voltage source at the positive terminal to be the opposite as the polarity of the
offset out of the op amp in order for them to cancel. If the offset is positive on the output side of
the op amp, then the voltage source at the positive terminal would have to have a negative
polarity to cancel it out. To address the problem, I would observe whether the expected output is
shown when the voltage source at the positive terminal is at one polarity and if the output is not
the expected output, then I would reverse the polarity of the voltage source.