Pseudorandom Bit Generation using Coupled
Congruential Generators
ABSTRACT:
In this paper we propose the generation of a pseudorandom bit sequence (PRBS) using a
comparative linear congruential generator (CLCG) as follows. A bit “1” is output if the first LCG
produces an output that is greater than the output of the second LCG and a bit “0” is output
otherwise. Breaking this scheme would require one to obtain the seeds of the two independent
generators, given the bits of the output bit sequence. We prove that the problem of uniquely
determining the seeds for the CLCG requires (i) a knowledge of at least log2 m2 (m being the
LCG modulus) bits of the output sequence and (ii) the solution of at least log2 m2 inequalities
where each inequality (dictated by the output bit observed) is applied over positive integers.
Computationally, we show that this task is exponential in n (where n = log2 m is the number of
bits in m) with complexity O (22n). The quality of the PRBS so obtained is assessed by
performing a suite of statistical tests (NIST 800-22) recommended by NIST. We observe that a
variant of our generator that uses two CLCGs (called dual CLCG), pass all the NIST pseudo
randomness tests with a high degree of consistency.
Keywords: comparative linear congruential generator (CLCG), pseudorandom number generator
(PRNG), Linear Feedback Shift Registers (LFSRs), Parameter Generation Algorithm (PAR)
INTRODUCTION:
A pseudorandom number generator (PRNG) is a deterministic algorithm that produces a
long sequence of numbers that appear random and in practice, indistinguishable from a stream
of truly random numbers. PRNGs are routinely used in several computing applications and are
indispensable in cryptographic operations. Chaotic dynamical systems, characterized by
sensitivity to initial conditions and topological transitivity provide a basis for the construction of
pseudorandom bit generators (PRBG). Exploiting the phenomenon of chaos for cryptographic
applications has also been suggested. PRBGs based on chaotic maps and Linear Feedback Shift
Registers (LFSRs), have also been studied. However, chaotic systems implemented in finite
precision can suffer from degradation of dynamical characteristics which in turn can lead to
weaker cryptographic properties. Techniques to circumvent this issue include using LFSRs to
perturb the output of chaotic systems and more recently, the idea of coupling two or more
chaotic systems, it is shown that PRBGs based on coupled chaotic maps (with subsequent
perturbation by LFSRs) result in secure bit sequences with good statistical properties, thereby
making them good candidates for cryptographic applications. In, this idea is exploited in
conjunction with arithmetic coding to design a compression and encryption scheme.
VEDLABS, #112, Oxford Towers, Old airport Road, Kodihalli, Bangalore-08,
www.vedlabs.com , Email id: projects@vedlabs.com, Ph: 080-42040494.
Page 1
Algorithm PAR LCG (Linear Congruential Generator Parameter Generation Algorithm):
Input: x i+1’s and yi+1’s from Eqns. with parameters satisfying the maximum period conditions.
Both seeds (x0, y0) are not simultaneously even or odd and m is a small modulus.
Output: Parameters aj and bj for LCG of the form x i+1 = aj xi + bj (mod M), large M, maximum
period.
The integer outputs of the CQCG system: Eqns. 1 and 2 that are not simultaneously odd or even
are used as the inputs to algorithm PARLCG. Note that the integer outputs of the QCG lie in [0,
(m − 1)]. We discard the integers if any one of these outputs is a zero. The LCG parameter a is
chosen such that a(mod 4) equals 1. The LCG parameter b is the integer output that is odd.
Hence the parameters a and b meet the conditions for maximum period for an LCG.
HARDWARE AND SOFTWARE REQUIREMENTS:
Software Requirement Specification:

Operating System: Windows XP with SP2

Synthesis Tool: Xilinx 12.2.

Simulation Tool: Modelsim6.3c.
VEDLABS, #112, Oxford Towers, Old airport Road, Kodihalli, Bangalore-08,
www.vedlabs.com , Email id: projects@vedlabs.com, Ph: 080-42040494.
Page 2
Hardware Requirement specification:

Minimum Intel Pentium IV Processor

Primary memory: 2 GB RAM,

Spartan III FPGA

Xilinx Spartan III FPGA development board

JTAG cable, Power supply
REFERENCES:
[1] F. Dachselt and W. Schwarz, “Chaos and Cryptography”, IEEE Trans. on Circuits and SystemsI, Fund. Theory and Applications, 48(12), pp: 1498-1509, 2001.
[2] M. Jessa, “Designing security for number sequences generated by means of the sawtooth
chaotic map”, IEEE Trans. on Circuits and Systems-I, Vol. 53, No. 5, pp: 1140-1150, May 2006.
[3] T. Addabbo, M. Alioto, A. Fort, A. Pasini, S. Rocchi and V. Vignoli, “A class of macimumperiod nonlinear congruential generators derived from the Renyi chaotic map”, IEEE Trans. on
Circuits and Systems-I, Vol. 54, No. 4, pp: 816-828, April 2007.
[4] R. Kuehnel, J. Theiler and Y. Wang, “Parallel random number generators for sequences
uniformly distributed over any range of integers”, IEEE Trans. on Circuits and Systems-I, Vol. 53,
No. 7, pp: 1496-1505, July 2006.
[5] R. Bose and S. Pathak, “A Novel Compression and Encryption Scheme Usign Variable Model
Arithmetic Coding and Coupled Chaotic System”, IEEE Trans. Circuits and Systems-I, 53(4), PP;
848-857, 2006.
VEDLABS, #112, Oxford Towers, Old airport Road, Kodihalli, Bangalore-08,
www.vedlabs.com , Email id: projects@vedlabs.com, Ph: 080-42040494.
Page 3