P.E.S. Istitute of Technology( Bangalore South Campus)
Hosur Road, ( 1Km Before Electronic City), Bangalore 560100.
Department of Electronics and Communication
Second Internals
Date
: 26/03/2014
Subject & Code :Digital System design using Verilog(10EC666)
Name of faculty : M Raghavendra
Answer any 5 Questions
Marks : 50
Section : 6th “A &B”
Time : 1Hr:30Mins
Q.No
Questions
Marks
1
Develop a Verilog model for a pipelined circuit that computes the average of
corresponding values in three streams of input values, a, b
and c. The pipeline consists of three stages: the fi rst stage sums values of a and
b and saves the value of c; the second stage adds on the saved value of c; and
the third stage divides by three. The inputs and output are all signed fixed-point
numbers indexed from 5 down to _8.
a. Develop a Verilog model for an accumulator that calculates the sum of a
sequence of fixed-point numbers. Each input number is signed with 4 prebinary-point and 12 post-binary-point bits. The accumulated sum has 8 prebinary-point and 12 post-binary-point bits. A new number arrives at the input
during a clock cycle when the data_en control input is 1. The accumulated sum
is cleared to 0 when the reset control input is 1. Both control inputs are
synchronous.
b. Write Verilog code for a negative-edge-triggered D-flip-flop with clock
enable, negative-logic asynchronous preset and clear, and both active-high and
active-low outputs. It is illegal for both preset and clear to be active together.
Develop a Verilog model for this fl ip-fl op.
Construct a combinational and sequential multiplier for two 16-bit operands
containing just one adder that adds successive partial products over successive
clock cycles. The final product is 32 bits.
a. Develop a Verilog behavioral model of an adder/subtracter for 12-bit
unsigned binary numbers. The circuit has data inputs x and y, a data output s, a
control input mode that is 0 for addition and 1 for subtraction, and an output
ovf_unf that is 1 when an addition overfl ow or a subtraction underflow occurs.
10M
2
3
4
10M
10M
10M
b. Develop a verifi cation testbench for the adder/subtracter that compares the
result with the result of addition or subtraction performed on values of type
integer.
5
a. Develop a Verilog model for a thermostat that has two 8-bit unsigned binary
inputs representing the target temperature and the actual temperature in degrees
Fahrenheit (˚F). Assume that both temperatures are above freezing (32˚F). The
detector has two outputs: one to turn a heater on when the actual temperature is
more than 5˚F below target, and one to turn a cooler on when the actual
temperature is more than 5˚F above target.
b. Develop a Verilog model of a code converter to convert the 4-bit Gray code
10M
to a 4-bit unsigned binary integer.
6
7
a. What values are represented by the 8-bit 2s-complement numbers 00110101
and 10110101?
b. What number is represented by the fixed-point binary number 01100010,
assuming the binary point is four places from the right?
c. What number is represented by the signed fixed-point binary number
111101, assuming the binary point is four places from the right?
d. Show how to use an adder for two signed fixed-point signals: a, with 4 prebinary-point and 7 post-binary-point bits, and b, with 6 pre-binary-point and 4
post-binary-point bits. The result c should have 6 pre-binary-point and 4 postbinary-point bits.
1. Express the number 4.510 in fl oating-point format with 5 bits of exponent
and 12 bits of mantissa magnitude.
2. What values are represented by the following bit vectors, interpreted in
floating-point format with 4 bits of exponent and 11 bits of mantissa
magnitude: 0000000000000000, 0111100000000000 and 0100010000000000?
3. Determine the minimum number of exponent and mantissa bitsrequired to
represent a floating-point value in the range _100 to 100 with a precision of at
least 4 decimal digits.
10M
10M
P.E.S. Istitute of Technology( Bangalore South Campus)
Hosur Road, ( 1Km Before Electronic City), Bangalore 560100.
Department of Electronics and Communication
SCHEME AND SOLUTION
SECOND INTERNAL TEST
Faculty: M RAGHAVENDRA
Subject: Digital system design using Verilog
Questi
on No.
1.
Semester: 6th “A & B”
Sub. Code:10ECL666
module average_pipeline ( output reg signed [5:–8] avg,
input signed [5:–8] a, b, c,
input clk );
wire signed [5:–8] a_plus_b, sum, sum_div_3;
reg signed [5:–8] saved_a_plus_b, saved_c, saved_sum;
assign a_plus_b = a + b;
always @(posedge clk) begin // Pipeline register 1
saved_a_plus_b <= a_plus_b;
saved_c <= c;
end
assign sum = saved_a_plus_b + saved_c;
always @(posedge clk) // Pipeline register 2
saved_sum <= sum;
assign sum_div_3 = saved_sum * 14'b00000001010101;
always @(posedge clk) // Pipeline register 3
avg <= sum_div_3;
endmodule
Mark
s
5M
2.
a.
5M
module accumulator
( output reg signed [7:-12] data_out,
input signed [3:-12] data_in,
input data_en, clk, reset );
wire signed [7:-12] new_sum;
assign new_sum = data_out + data_in;
always @(posedge clk)
if (reset) data_out <= 20'b0;
else if (data_en) data_out <= new_sum;
endmodule
b.
module flip_flop_n ( output reg Q,output Q_n,
input pre_n, clr_n, D,
input clk_n, CE );
always @( negedge clk_n or
negedge pre_n or negedge clr_n ) begin
if (!pre_n && !clr_n)
$display("Illegal inputs: pre_n and clr_n both 0");
if (!pre_n) Q <= 1'b1;
else if (!clr_n) Q <= 1'b0;
else if (CE) Q <= D;
end
5M
assign Q_n = ~Q;
endmodule
3. Combinational Multiplier
5M
5M
Sequential Multiplier
4.
a.
3M
module adder_subtracter ( output [11:0] s,
output ovf_unf,
input [11:0] x, y,
input mode );
assign {ovf_unf, s} = !mode ? (x + y) : (x – y);
endmodule
b.
`timescale 1ns/1ns
module test_add_sub;
reg [11:0] x, y;
wire [11:0] s;
reg mode;
wire ovf_unf;
integer x_num, y_num, s_num;
7M
task apply_test ( input integer x_test, y_test,
input mode_test );
begin
x = x_test; y = y_test; mode = mode_test;
#10;
end
endtask
adder_subtracter duv ( .x(x), .y(y), .s(s),
.mode(mode), .ovf_unf(ovf_unf) );
initial begin
apply_test( 0, 10, 0);
apply_test( 0, 10, 1);
apply_test( 10, 0, 0);
apply_test( 10, 0, 1);
apply_test(2**11, 2**11, 0);
apply_test(2**11, 2**11, 1);
// ... further test cases
#10 $finish;
end
always @* begin
#5 x_num = x; y_num = y; s_num = s;
if (!mode)
if (x_num + y_num > 2**12–1) begin
if (!ovf_unf)
$display("Addition overflow: ovf_unf should be 1");
end
else begin
if (!(!ovf_unf && s_num = = x_num + y_num))
$display("Addition result incorrect");
end
else
if (x_num – y_num < 0) begin
if (!ovf_unf)
$display("Subtraction underflow: ovf_unf should be 1");
end
else begin
if (!(!ovf_unf && s_num = = x_num – y_num))
$display("Subtraction result incorrect");
end
end
endmodule
5.
a.
module thermostat ( output heater_on, cooler_on,
input [7:0] target, actual );
4M
assign heater_on = actual < target – 5;
assign cooler_on = actual > target + 5;
endmodule
6M
b.
module gray_converter ( output reg [3:0] numeric_value,
input [3:0] gray_value );
always @*
case (gray_value)
4'b0000: numeric_value = 4'b0000;
4'b0001: numeric_value = 4'b0001;
4'b0011: numeric_value = 4'b0010;
4'b0010: numeric_value = 4'b0011;
4'b0110: numeric_value = 4'b0100;
4'b0111: numeric_value = 4'b0101;
4'b0101: numeric_value = 4'b0110;
4'b0100: numeric_value = 4'b0111;
4'b1100: numeric_value = 4'b1000;
4'b1101: numeric_value = 4'b1001;
4'b1111: numeric_value = 4'b1010;
4'b1110: numeric_value = 4'b1011;
4'b1010: numeric_value = 4'b1100;
4'b1011: numeric_value = 4'b1101;
4'b1001: numeric_value = 4'b1101;
4'b1000: numeric_value = 4'b1111;
endcase
endmodule
6.
a.
b.
c.
10M
d.