CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
SMUAPR15
ASSESSMENT_CODE MCA2050_SMUAPR15
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
17524
QUESTION_TEXT
Explain the different types of addressing modes.
a.Implied mode
b.Immediate mode
c.Register mode
d.Register Indirect mode
e.Auto-increment or Auto-decrement mode
SCHEME OF EVALUATION
f.Direct addressing mode
g.Indirect addressing mode
h.Relative address mode
i.Indexed Addressing mode
j.Base Register addressing mode
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
17526
QUESTION_TEXT Explain First generation to Fifth generation computer.
SCHEME OF
EVALUATION
1. First generation computer: The first generation of computer (
1946-1954) was marked by the use of vacuum tubes or values as their
basic electronic component. They were very large in size. They
consumed too much power and generated too much heat, when used
for even short duration of time. Some example of first generation
computers are ENIAC, EDVAC, EDSAC, UNIVAC-I
2. Second Generation computers: The second generation of
computers (1953-64) was marked by the use of transistors in place of
vacuum tubes. The second – generation computers were smaller in
size and generated less heat than first generation computers.
Although they were slightly faster and more reliable than earlier
computer. They also had many disadvantages. They had limited
storage capacity, consumed more power and were also relatively slow
in performance. Some examples of second generation computers are
IBM 701, and IBM 650.
3. Third Generation Computer: The third generation of computer
(1964-1978) was marked by use of Integrated Circuits(IC) in place of
transistors. As hundred of transistors could be put on a single small
circuit, so IC were more compact than transistors. The third
generation computers were even smaller in size, very less heat
generated and required very less power as compared to earlier two
generation of computers. These computers required less human
labour at the assembly stage. Some examples of third generation
computers are IBM 360, PDP-8, Cray -1 and VAX.
4. Fourth Generation Computers: The fourth generation of
computers(1978-till date) was marked by use of large-scale
Integrated (LSI) circuits in place of ICs. LSI circuits are still more
compact than ICs. In 1978, it was found that millions of components
could be packed onto a single circuit, known as Very Large Scale
Integration(VLSI). VLSI is the latest technology of computer that led
to the development of the popular Personal Computer(PCs) also
called as Microcomputers.Example of fourth generation computers
are IBM PC, IBM PC/AT, 386, 486, Pentium and CRAY-2
5. Fifth Generation Computer: The fifth generation computers are
still under research and development stage. These computers would
have artificial intelligence. They will use USLI chips in place of
VLSI chips. One USLI chip contains millions of components on a
single IC. Robots have some features of fifth generation computers.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73360
QUESTION_TEXT
What is Dynamic Scheduling with a scoreboard. Explain the four
steps in the scoreboard technique.
SCHEME OF
EVALUATION
Dynamic Scheduling with a ScoreboardIn a dynamically scheduled
pipeline, all instructions pass through the issuestage in order (inorder issue); however, they can be stalled or bypass eachother in the
second stage (read operands) and thus enter execution out oforder.
Score board is a method of permitting out-of-order
instructionexecution when sufficient resources are available and
there are no datadependencies.(2 Marks)
Four steps in the scoreboard technique.
1. Issue: Issue step is used as a replacement of a part of ID step of
DLXpipeline. In this step the instruction is forwarded to FU. The
internal dataconstruction is also modified here. It is done only in two
situations:
FU for the instruction is jobless.
No other active instruction has the same register as destination.
Thisensures that the operation is free from WAW (Write after Write)
datahazard.
When any structural or WAW hazards are detected, the stall occurs
andthe issue of all subsequent instructions is stopped until these
datahazards have been corrected. when a stall occurs in this stage,
thebuffer between instruction issue and fetch is filled. If buffer
contains asingle instruction then the instruction fetch also stalls at
once but if thebuffer space contains a queue, it creates stalls only
after the bufferqueue is fully filled.
2. Read operands: The scoreboard examines if the source operands
isavailable or not. The source operand is said to be available when
nopreviously issue active instruction is ready to write to it. The
scoreboard prompts the FU to start reading the operands from data
registers and start execution as soon as the source operands
become available. Read after Write (RAW) hazards are resolved in a
dynamic manner during thisstage. It may also send instructions for
out-of-order execution. Issue and read operand step together
completes the functions of the ID step ofDLX pipeline.
3. Execution: After receiving the operands, the FU starts execution.
Oncompletion of execution, the result is generated. Thereafter FU
informsthe scoreboard about the completion of execution step.
execution step isused in place of EX step of DLX pipeline but in latter
it may involve multiple cycles.
4. Write result: after the FU completes execution, the scoreboard
detects whether the WAR hazards are present or not. If the WAR
hazard is detected, it stalls the instruction. WAR hazard occurs when
there is an instruction code as in our earlier example of ADDD &
SUBD where bothutilize F8.(2 Marks each )
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73363
QUESTION_TEXT
Describe components of a vector register processor.
SCHEME OF
EVALUATION
1. Vector registers: there are many vector registers that can
perform different vector operations in an overlapped manner. Every
vector register is affixed –length bank that consists of one vector
with multiple elements and each element is 64-bit in length
2. Scalar registers the scalar registers are also linked to the
functional units with the help pf the pair of crossbars. They are used
for various purposes such as computing addresses for passing to the
vector load/store unit and as buffer for input data to the vector
registers.
3. Vector functional units these units are generally floating –points
units that are completely pipelined, they are able to initiate a new
operation on each clock cycle. They comprise all operation units that
are utilized by the vector instruction
4. Vector load and store unit This unit can also be pipelined and
perform an overlapped but independent transfer to or from the vector
registers
5. Control unit this unit decodes and coordinates among
functional units. It can detect data hazards as well as structural
hazards. Data hazards are the conflicts in register accesses while
functional hazards are the conflicts in functional units.
( 5x2=10 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125202
QUESTION_TEXT
What you mean by RAID? Explain different RAID levels RAID 1,
RAID 3, RAID 5.
RAID is the acronym for ‘redundant array of inexpensive disks’.
There are several approaches to redundancy that have different
overhead and performance. The Patterson, Gibson, and Katz 1987
paper introduced the term RAID. (1 mark)
RAID 1
Mirroring or shadowing is the traditional solution to disk failure. It
uses twice as many disks. Data is simultaneously written on two
disks, one non-redundant and one redundant disk so that there are
two copies of the data. The system goes to the mirror disk in case
one disk fails to get the required information. This technique is the
most expensive solution…. (3 marks)
RAID 3
SCHEME OF
EVALUATION
Bit-Interleaved parity is an error detection technique where
character bit patterns are forced into parity so the total number of
one(1) bit is always odd or even. This is done by adding a “1” or “0”
bit to each byte as the character/byte is transmitted. At the other
end of the transmission the parity is checked for accuracy. BIP is also
a method used at the physical layer (high speed transmission of
binary data) level to monitor errors…… (3 marks)
RAID 5
This level uses the same ratio of disks (data disks and check disks) as
RAID 3, but data is accessed differently. In the prior organisation
every access went to all disks. Some applications would prefer to do
smaller accesses, allowing independent accesses to occur in parallel.
That is the purpose of this next RAID level…..
(3 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125205
QUESTION_TEXT
Explain the features of Fine-Grained SIMD Architecture. How MPP
algorithm operates?
SCHEME OF
EVALUATION
The features of fine-grained architecture:
Complexity is minimal and the degree of autonomy is lowest feasible
in each Processing Element (PE).
Economic constraints are applicable on the maximum number of PEs
provided.
It is assumed by the programming model that there is equivalence
between the number of PEs and the number of data items, and
hides any mismatch as far as possible.
The 4-connected nearest neighbour mesh is used as the basic
interconnection method.
A simple extension of a sequential language with parallel-data
additions is the usual programming language
(5 Marks)
The MPP algorithm operates as follows:
For each pixel in one of the images (the reference image) a local
neighbourhood area is defined. This is correlated with the similar
area surrounding each of the candidate match pixels in the second
image.
The measure applied is the normalised mean and variance cross
correlation function. The candidate yielding the highest correlation
is considered to be the best match, and the locations of the pixels in
the two images are compared to produce the disparity value at that
point of the reference image.
The algorithm is iterative. It begins at low resolution, that is, with
large areas of correlation around each of a few pixels. When the first
pass is complete, the test image is geometrically warped according
to the disparity map.
The process is then repeated with a higher resolution (usually
reducing the correlation area. and increasing the number of
computed matches, by a factor of two), a new disparity map is
calculated and a new warping applied, and so on.
The procedure is continued either for a predetermined number of
passes or until some quality criterion is exceeded.
(5 Marks)